Chip package structure, preparation method thereof, and package system

Abstract

The application provides a chip packaging structure, a preparation method thereof, and a packaging system. The chip packaging structure comprises a packaging substrate, a chip Die, and a first encapsulant. The packaging substrate has opposite first and second surfaces. The chip is coupled to the packaging substrate and has a hot spot. The first surface of the packaging substrate is provided with a heat dissipation connecting point. A heat conduction channel is formed in the packaging substrate and connects the heat dissipation connecting point and the hot spot. The second surface is provided with a first connecting terminal for an external device. The first encapsulant is arranged on the first surface, and a heat conduction structure is formed in the first encapsulant. The heat conduction structure extends from the heat dissipation connecting point to the surface of the first encapsulant. The heat dissipation connecting point corresponds to the position of the hot spot of the chip. The heat dissipation connecting point and the heat conduction structure can dissipate heat from the hot spot of the chip. The heat conduction structure can be flexibly arranged and combined with the manufacturing process of the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure, its preparation method, and packaging system. Background Technology

[0002] Compared to traditional packaging, which only encapsulates a single semiconductor chip, System-in-Pack (SIP) packaging can integrate one or more semiconductor chips and their peripheral devices into a package structure. In traditional 2D or 2.5D SIP packaging, the semiconductor chip and peripheral devices are placed on the same side of the substrate or RDL (redistribution layer), limiting device layout utilization. 3D system packaging can fully utilize the layout space of SIP packaging, placing the semiconductor chip and peripheral devices on different sides or positions (above, below, and inside) of the substrate or RDL using techniques such as embedded technology, double-sided mounting technology, and injection molding, thereby increasing device layout density and further realizing advanced packaging forms for SIP miniaturization.

[0003] With the continued booming sales of 5G smartphones and wearable products, the demands for motherboard utilization and customized differentiated modules are constantly increasing. Against this backdrop, the widespread application of SiP (System-in-Package) has become a hot topic. Currently, traditional SiP and 3D SiP are widely used in electronic products to enhance product competitiveness. However, the increasing number of components in 3D SiP leads to higher power density in each chip, resulting in greater energy consumption and heat generation during operation. Therefore, the thermal performance of chip packaging is receiving increasing attention. However, current heat dissipation paths for 3D SiP structures have relatively high thermal resistance and lack specific heat dissipation targeting. Summary of the Invention

[0004] This application provides a chip packaging structure and its fabrication method and packaging system, which can target heat dissipation of concentrated hot spots on the chip to improve the heat dissipation effect of the structure.

[0005] In a first aspect, this application provides a chip packaging structure that can be coupled with a circuit board to form a packaging system. The chip packaging structure includes a packaging substrate, a chip die, and a first package body. The packaging substrate provides support for the entire structure and has opposing first and second surfaces. The chip is coupled to the packaging substrate and has hot spots, which generate significant amounts of heat during chip operation. A heat dissipation connection point is provided on the first surface of the packaging substrate, and a thermally conductive channel is formed within the packaging substrate connecting the heat dissipation connection point and the hot spot. A first connection terminal for connecting external devices is provided on the second surface, specifically, the first connection terminal is coupled to the circuit board when the chip packaging structure is coupled. The first package body is disposed on the first surface, and a thermally conductive structure is formed within the first package body, extending from the heat dissipation connection point to the surface of the first package body.

[0006] In the above chip packaging structure, since the heat dissipation connection point corresponds to the hot spot location of the chip, the hot spot of the chip can be targeted for heat dissipation through the heat dissipation connection point and the heat conduction structure; it is equivalent to setting a heat conduction structure inside the chip packaging structure, which can be flexibly set according to different packaging structures and can also be closely integrated with the chip packaging structure manufacturing process.

[0007] It should be understood that the thermally conductive structure in the aforementioned chip packaging structure can be made of a material with low thermal resistance, possessing good thermal conductivity, which is beneficial for guiding heat from hot spots from the heat dissipation connection point to the surface of the structure. Specifically, the thermal resistance value of the thermally conductive structure is at least lower than that of the first package body, improving the heat dissipation efficiency; in some possible implementations, the thermal resistance value of the thermally conductive structure can be lower than that of other non-conductive wrapping materials to adapt to more application scenarios.

[0008] The chip packaging structure also includes electronic components disposed on a first surface. The first package encapsulates the electronic components, and an electrical channel connecting the electronic components and the chip is formed within the packaging substrate. A second connection terminal for connecting to the packaging substrate is also provided on the side of the chip facing the first package. To protect the chip packaging structure, a protective coating can be formed on the surface of the first package. When the protective coating is made of metal, it can quickly dissipate heat conducted from the heat-conducting structure, further improving the heat dissipation effect. The heat dissipation connection point can specifically be a heat-conducting pad. The shape of the heat-conducting structure is not limited here and can be set according to specific implementation conditions.

[0009] In practical applications, chip packaging structures have various structural forms. Taking the 3D SIP structure as an example, when the chip packaging structure is a double-sided surface mount SIP, the packaging substrate includes a substrate. A first solder resist layer is formed on the side of the substrate facing the first package, and a second solder resist layer is formed on the side of the substrate away from the first package. The chip is coupled to the side of the second solder resist layer away from the first package. A second package covering the chip is also provided on the side of the second solder resist layer away from the first package, and a first connection terminal protrudes from the second package.

[0010] When the chip packaging structure is a Semiconductor In-Package (SIP) system, the packaging substrate includes a substrate, a first solder resist layer is formed on the side of the substrate facing the first package, and a second solder resist layer is formed on the side of the substrate away from the first package; the chip is embedded in the substrate.

[0011] When the chip packaging structure is a stacked Fanout SIP, along the direction from the first surface to the second surface, the packaging substrate includes a first sub-wiring layer, a molding compound layer, and a second sub-wiring layer stacked together. The molding compound layer contains connectors for connecting the first and second sub-wiring layers. The chip is coupled between the first and second sub-wiring layers and circumferentially covered by the molding compound layer. The second sub-wiring layer contains first pads for connecting first connection terminals, and vias for connecting the first pads and the connectors are also formed within the second sub-wiring layer. A dielectric layer is also placed between the chip and the second sub-wiring layer. This dielectric layer is used to fix the chip to the second sub-wiring layer, and double-sided adhesive can be used for the dielectric layer.

[0012] Secondly, based on the chip packaging structure, this application also provides a packaging system, which includes a circuit board and any of the aforementioned chip packaging structures. The circuit board is coupled to the chip packaging structure through a first connection terminal. When in application, the circuit board can export the chip's signals and connect them to external devices, thereby helping the system to achieve its functions. The circuit board here can be a PCB (printed circuit board), an FPC (flexible circuit board), or an FPCB (flexible printed circuit board).

[0013] Thirdly, based on the structure of the chip packaging structure, this application also provides a method for preparing the chip packaging structure, specifically including the following steps:

[0014] A packaging substrate with a chip coupled thereto is provided, the chip having a hot spot; the packaging substrate has a first surface and a second surface opposite to each other, and a thermally conductive channel communicating with the hot spot is provided within the packaging substrate.

[0015] A heat dissipation connection point connected to a heat conduction channel is provided on the first surface of the packaging substrate;

[0016] A first package with a thermally conductive structure is formed on the first surface of the packaging substrate, the thermally conductive structure extending from the heat dissipation connection point to the surface of the first package;

[0017] A first connection terminal is formed on the second surface of the packaging substrate.

[0018] The step of forming a first package with a thermally conductive structure on a first surface of a packaging substrate, wherein the thermally conductive structure extends from a heat dissipation connection point to the surface of the first package, may include the following steps:

[0019] Thermally conductive structures are generated at heat dissipation connection points using techniques such as growth and welding.

[0020] A first package is formed on the first surface of the packaging substrate, and the end of the thermally conductive structure away from the heat dissipation connection point is located on the surface of the first package.

[0021] Alternatively, the step of forming a first package with a thermally conductive structure on a first surface of a packaging substrate, wherein the thermally conductive structure extends from a heat dissipation connection point to the surface of the first package may include the following steps:

[0022] A first package is formed on the first surface of the packaging substrate;

[0023] An inwardly vented opening is made on the surface of the first package to form a pre-set hole communicating with a heat dissipation connection point;

[0024] A heat-conducting structure is generated within the pre-drilled holes through methods such as pouring or implantation. Attached Figure Description

[0025] Figures 1a to 1c This is a schematic diagram of a packaging structure that dissipates heat downwards through a circuit board.

[0026] Figures 1d to 1f This is a schematic diagram of a packaging structure that dissipates heat upwards through the overall structure.

[0027] Figures 2a to 2c This is a cross-sectional view of a chip packaging structure provided in an embodiment of this application.

[0028] Figures 3a to 3f This is a schematic diagram of a heat-conducting structure in a chip packaging structure provided in an embodiment of this application;

[0029] Figure 4a This is a cross-sectional view of a chip packaging structure provided in an embodiment of this application.

[0030] Figure 4b for Figure 4a Schematic diagram of the cross-sectional structure of AA;

[0031] Figure 4c This is a schematic diagram illustrating the positional relationship between multiple concentrated hot spots and thermally conductive structures in a chip packaging structure provided in an embodiment of this application.

[0032] Figure 4d for Figure 4c Schematic diagram of the heat-conducting structure;

[0033] Figure 4e This is a schematic diagram illustrating the positional relationship between multiple concentrated hot spots and thermally conductive structures in a chip packaging structure provided in an embodiment of this application.

[0034] Figure 4f for Figure 4e Schematic diagram of the heat-conducting structure;

[0035] Figure 5a This is a cross-sectional view of a chip packaging structure provided in an embodiment of this application.

[0036] Figure 5b for Figure 5a Schematic diagram of the cross-sectional structure of BB;

[0037] Figure 6a This is a cross-sectional structural diagram of a chip packaging structure provided in an embodiment of this application;

[0038] Figure 6b for Figure 6a A schematic diagram of the cross-sectional structure of CC;

[0039] Figure 7 This is a schematic diagram of a method for fabricating a chip packaging structure according to an embodiment of this application;

[0040] Figure 8 This is a partial structural diagram of a chip packaging structure provided in an embodiment of this application;

[0041] Figure 9 This is a schematic diagram of the process for preparing a thermally conductive structure in a method for preparing a chip packaging structure according to an embodiment of this application;

[0042] Figure 10 for Figure 9 A schematic diagram of structural changes in the preparation method shown;

[0043] Figure 11 This is a schematic diagram of the process for preparing a thermally conductive structure in a method for preparing a chip packaging structure according to an embodiment of this application;

[0044] Figure 12a and Figure 12b for Figure 11 A schematic diagram of structural changes in the preparation method shown;

[0045] Figures 13a to 13c This is a cross-sectional structural diagram of a packaging system provided in this embodiment. Detailed Implementation

[0046] As smart electronic products increasingly trend towards miniaturization, the heat dissipation of chip packaging within encapsulation systems is receiving significant attention. Taking 3D SIP structures as an example, current heat dissipation methods for packaging structures mainly include downward heat dissipation through the circuit board and upward heat dissipation through the overall device structure. Specifically, downward heat dissipation through the circuit board in the packaging structure can be referenced... Figures 1a to 1c As shown, Figure 1a The diagram shows a double-sided surface mount SIP structure, in which chip 2' and electronic device 3' are coupled to opposite sides of substrate 1'. Chip 2' is encapsulated by a first package 41', and electronic device 3' is encapsulated by a second package 42'. Chip 2' has a concentrated hot spot 21', and the heat from the concentrated hot spot 21' is directed to circuit board 7' for heat dissipation through heat dissipation paths s1 (indicated by solid arrows) and s2 (indicated by dashed arrows). Specifically, s1 passes through pads 5', substrate 1', and solder balls 6', while s2 passes through chip 2', the first package 41', and adhesive 8'. Figure 1b In a SIP structure embedded in a semiconductor substrate, chip 2' dissipates heat from hot spot 21' to circuit board 7' via heat dissipation paths s3 (indicated by solid arrows) and s4 (indicated by dashed arrows). Specifically, s3 passes through via 11', substrate 1', via 11', and solder ball 6', while s4 passes through chip 2', substrate 1', and solder ball 6'. Figure 1c In the stacked fanout SIP structure shown, chip 2' directs heat from the concentrated hotspot 21' to circuit board 7' via heat dissipation paths s5 (indicated by solid arrows) and s6 (indicated by dashed arrows) to achieve heat dissipation. Specifically, s5 passes through via 11', circuit layer 12', copper pillar 13', and solder ball 6', while s6 passes through chip 2', adhesive layer 9', circuit layer 12', and solder ball 6'. The upward heat dissipation through the overall structure of the package can be referenced... Figures 1d to 1f As shown, a housing 10' (which can be a graphite sheet or a complete housing) is provided on one side of the second housing 42' of the packaging structure. Figure 1d Chip 2' directs the heat from the concentrated hotspot 21' to the overall structural components via heat dissipation path s7, specifically through pad 5', substrate 1', second package 42', and outer casing 10'; Figure 1e In the SIP structure embedded in a semiconductor substrate shown, chip 2' dissipates heat from concentrated hotspot 21' through heat dissipation path s8, which directs heat from the hotspot 21' to the overall structural components. Specifically, s8 passes through substrate 1', via 11', second package 42', and outer casing 10'. Figure 1fIn the stacked fanout SIP structure shown, chip 2' directs the heat from concentrated hotspot 21' to the overall structural components via heat dissipation path s9, specifically passing through circuit layer 12', second package 42', and housing 10'. Both of these heat dissipation methods involve relatively long heat dissipation paths, and some materials along these paths have high thermal resistance (e.g., the highly thermally conductive second package 42'). In particular, they cannot provide targeted heat dissipation for the chip, thus failing to meet increasingly demanding heat dissipation requirements.

[0047] Therefore, embodiments of this application provide a chip packaging structure to improve the heat dissipation capacity of the packaging structure and to provide targeted heat dissipation for the chip. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings.

[0048] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more” unless the context clearly indicates otherwise.

[0049] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0050] Please refer to Figure 2aThe schematic cross-sectional view of a chip packaging structure 10 provided in this application embodiment is shown below. For clarity, only a few simple essential structures and their approximate locations are shown here. The chip packaging structure 10 includes a packaging substrate 1, which is a multilayer plate structure and may include multiple RDLs, having opposing first surfaces a1 and second surfaces a2. An electronic device 2 and a first package 31 encapsulating the electronic device 2 are coupled to the first surface a1 of the packaging substrate 1. A chip 4 is coupled to the packaging substrate 1 (the position of the chip 4 on the packaging substrate 1 is not limited; it can be coupled to the surface of the packaging substrate 1 or embedded inside the packaging substrate 1; here, the example is that the chip 4 is embedded inside the packaging substrate 1). An electrical channel P connecting the electronic device 2 and the chip 4 is formed within the packaging substrate 1. An internal connection terminal 81 for connecting to the packaging substrate 1 is provided on the surface of the chip 4 facing the first package 31. A first connection terminal 82 is provided on the second surface a2 of the packaging substrate 1, which is used for coupling with a circuit board or other devices to achieve electrical signal connection.

[0051] exist Figure 2a In the chip package structure 10 shown, chip 4 has a hot spot R, which is, for example, a region where chip 4 generates concentrated and high heat during operation. To dissipate the heat from the hot spot R of chip 4, a heat dissipation connection point 5 is provided on the first surface a1 of the package substrate 1. The heat dissipation connection point 5 is shown as a pad structure. A thermally conductive channel Q is formed inside the package substrate 1, connecting the heat dissipation connection point 5 and the hot spot R. A thermally conductive structure 6 is provided inside the first package body 31. One end of the thermally conductive structure 6 is connected to the heat dissipation connection point 5, and the other end is located on the surface of the first package body 31, meaning the thermally conductive structure 6 extends from the heat dissipation connection point 5 to the surface of the first package body 31. The first package body 31 can be made of a material with low thermal resistance and good thermal conductivity. Since the heat dissipation connection point 5 corresponds to the location of the hot spot R of chip 4, targeted heat dissipation can be achieved for the hot spot R of chip 4 through the heat dissipation connection point 5 and the thermally conductive structure 6.

[0052] It should be understood that the thermal resistance of the thermally conductive structure 6 is lower than that of the first package 31. Compared to the prior art, the thermally conductive structure 6 provides a faster heat conduction channel, improving heat conduction efficiency. The thermal resistance of the thermally conductive structure 6 can also be further lower than that of other non-conductive encapsulating materials, so that the encapsulation structure 10 provided in this application embodiment can adapt to a wider range of application scenarios. Figure 2b As shown, a protective coating 7 can be formed on the surface of the first package 31 by a sputtering process. When the protective coating 7 is made of metal, the heat conducted by the heat-conducting structure 6 can be quickly dissipated through the protective coating 7, which can enhance the heat dissipation effect of the structure. Figure 2cAs shown, a protective coating 7 can also be formed on other surfaces of the chip packaging structure 10, except for the side where the first connection terminal 82 is set (the side for docking with the circuit board), by sputtering. The protective coating 7 can realize the function of a shield, and the protective coating 7 has smaller requirements in terms of area and height than traditional shields, which is conducive to miniaturization of the entire structure.

[0053] The electronic device 2 in the above embodiments can be a passive device, an active device, or other devices, such as one or more combinations of resistors, capacitors, and inductors. It should be understood that the chip 4 here is an unpackaged bare die.

[0054] The heat-conducting structure 6 can be formed on the heat dissipation connection point 5 by at least one method, including welding, growth, injection molding, or implantation.

[0055] like Figures 3a to 3e Several different shapes of heat-conducting structures 6 are illustrated. On a plane perpendicular to the extending direction of the heat-conducting structure 6, the cross-section of the heat-conducting structure 6 can be rectangular. Figure 3a As shown), it can be circular ( Figure 3b As shown), it can be a polygon ( Figure 3c As shown), it can be cross-shaped ( Figure 3d As shown), it can be a polygonal shape ( Figure 3e As shown), it can even be an irregular shape (as shown). Figure 3f As shown in the image, no restrictions are imposed here.

[0056] In practical applications, chip packaging structures have various structural forms. Taking the 3D SIP structure as an example, it can include double-sided surface mount SIP, embedded semiconductor substrate SIP, stacked fanout SIP, and other structures. Next, we will further introduce the chip packaging structure 10 provided in this application using different forms of 3D SIP structures as examples.

[0057] like Figure 4aA double-sided surface mount chip package structure 10 is shown. The package substrate 1 specifically includes a substrate 11 and a first solder resist layer 12 and a second solder resist layer 13 formed on two surfaces of the substrate 11. The substrate 11 specifically includes multiple redistribution layers. The surface of the first solder resist layer 12 facing away from the substrate 11 corresponds to the first surface a1 of the package substrate 1, and the surface of the second solder resist layer 13 facing away from the substrate 11 corresponds to the second surface a2 of the package substrate 1. An electronic device 2 is disposed on the surface of the first solder resist layer 12 and is encapsulated by a first package body 31. A chip 4 is disposed on the surface of the second solder resist layer 13 and is encapsulated by a second package body 32. An internal connection terminal 81 is disposed on the surface of the chip 4 facing the first package body 31. A first connection terminal 82 is disposed on the side of the second solder resist layer 13 facing away from the substrate 11 and protrudes from the second package body 32 to facilitate coupling with a circuit board for electrical signal connection. An electrical channel P formed within the substrate 11 for connecting the electronic device 2 and the chip 4 specifically includes vias 101 and inner layer circuits 102 disposed within the substrate 11. The vias 101 and inner layer circuits 102 are distributed within the substrate 11 as required. On the surface of the substrate 11 where the first solder mask layer 12 is disposed, a first solder point 103 (connected to the via 101) is also provided, connecting to the electrical channel P. The electronic device 2 is connected to the first solder point 103. On the surface of the substrate 11 where the second solder mask layer 13 is disposed, a second solder point 104 (connected to the via 101) is provided, connecting to the electrical channel P. A portion of the second solder points 104 are connected to internal connection terminals 81 disposed on the chip 4 to achieve signal connection between the chip 4 and the packaging substrate 1, and a portion of the second solder points 104 are connected to first connection terminals 82 to achieve signal connection between the first connection terminals 82 and the packaging substrate 1. In this chip package structure 10, except for the side where the first connection terminal 82 is located (the side used to connect to the circuit board), the other surfaces are coated with a protective film 7 by sputtering.

[0058] To dissipate heat from the hot spot R on chip 4, the heat dissipation connection point 5 is specifically located on the surface of the substrate 11 where the first solder resist layer 12 is disposed, and the first solder resist layer 12 has an opening exposing the heat dissipation connection point 5 (equivalent to the heat dissipation connection point 5 being located on the first surface a1 of the packaging substrate 1); the electrical channel P located between the heat dissipation connection point 5 and the hot spot R can act as a heat conduction channel Q, in Figure 4a In the example structure, the heat conduction channel Q is equivalent to being formed by the via 101 and the inner layer circuit 102, so that the heat of the hot spot R on the chip 4 is transferred to the surface of the first package 31 through the internal connection terminal 81, the via 101, the inner layer circuit 102, the heat dissipation connection point 5 and the heat conduction structure 6.

[0059] Will Figure 4a The structure shown is cut along the plane containing AA to obtain Figure 4bAs shown in the structure, the hot spot R on chip 4 corresponds to the position of the heat conduction structure 6. There is an overlapping area between the two on the projection of the two on the packaging substrate 1, which allows the heat of the hot spot R to be dissipated in time, achieving a good heat dissipation effect.

[0060] It should be understood that Figure 4a and Figure 4b In the illustrated chip package structure 10, there is one hotspot R on chip 4, and one heat dissipation connection point 5 and one heat conduction structure 6. When the number of hotspots R on chip 4 is greater than one, the number of corresponding heat dissipation connection points 5 and heat conduction structures 6 can also be increased to ensure that the hotspots R, heat dissipation connection points 5, and heat conduction structures 6 can correspond one-to-one, achieving a good heat dissipation effect. Alternatively, when the number of hotspots R on chip 4 is greater than one, each hotspot R corresponds to one heat dissipation connection point 5, but multiple hotspots R can correspond to one heat conduction structure 6. Please refer to [reference needed]. Figure 4c and Figure 4e The projection of a heat-conducting structure 6 on the packaging substrate 1 overlaps with the projections of multiple concentrated hot spots R on the packaging substrate 1. These multiple concentrated hot spots R can be guided to the same heat-conducting structure 6 through the heat dissipation connection point 5. Figure 4c The heat-conducting structure 6 in the middle can be referred to Figure 4d , Figure 4e The heat-conducting structure 6 in the middle can be referred to Figure 4f As shown. For ease of explanation, in the following embodiments, one hot spot R will correspond to one heat-conducting structure 6 for illustrative purposes.

[0061] like Figure 5aA chip package structure 10 in a semiconductor in-package (SIP) configuration is shown. The package substrate 1 specifically includes a substrate 11 and a first solder resist layer 12 and a second solder resist layer 13 formed on two surfaces of the substrate 11. The surface of the first solder resist layer 12 facing away from the substrate 11 corresponds to the first surface a1 of the package substrate 1, and the surface of the second solder resist layer 13 facing away from the substrate 11 corresponds to the second surface a2 of the package substrate 1. An electronic device 2 is disposed on the surface of the first solder resist layer 12 and is encapsulated by a first package body 31. A chip 4 is embedded within the substrate 11, and an internal connection terminal 81 is disposed on the surface of the chip 4 facing the first package body 31. A first connection terminal 82 is disposed on the side of the second solder resist layer 13 facing away from the substrate 11 and protrudes from the second package body 32 to facilitate coupling with a circuit board for electrical signal connection. The electrical channel P formed within the substrate 11 for connecting the electronic device 2 and the chip 4 can be formed by vias 101 and inner layer circuits 102 disposed within the substrate 11, with the vias 101 and inner layer circuits 102 distributed within the substrate 11 as required. A first solder joint 103 (connected to the via 101) is provided on the surface of the substrate 11 where the first solder resist layer 12 is disposed, and the electronic device 2 is connected to the first solder joint 103. A second solder joint 104 (connected to the via 101) is provided on the surface of the substrate 11 where the second solder resist layer 13 is disposed, and the second solder joint 104 is connected to the electrical channel P, and the second solder joint 104 is connected to the external connection terminal 82. The other surfaces of the chip package structure 10, except for the side where the first connection terminal 82 is disposed (the side for mating with the circuit board), are coated with a protective film 7 by a sputtering process.

[0062] To dissipate heat from the hot spot R on chip 4, the heat dissipation connection point 5 is specifically located on the surface of the substrate 11 where the first solder resist layer 12 is disposed, and the first solder resist layer 12 has an opening exposing the heat dissipation connection point 5 (equivalent to the heat dissipation connection point 5 being located on the first surface a1 of the packaging substrate 1); the electrical channel P located between the heat dissipation connection point 5 and the hot spot R can act as a heat conduction channel Q, in Figure 5a In the example structure, the heat conduction channel Q is equivalent to being formed by the via 101 and the inner layer circuit 102, so that the heat of the hot spot R on the chip 4 is transferred to the surface of the first package 31 through the internal connection terminal 81, the via 101, the inner layer circuit 102, the heat dissipation connection point 5 and the heat conduction structure 6.

[0063] Will Figure 5a The structure shown is cut along the plane containing BB to obtain Figure 5b As shown in the structure, the hot spot R on chip 4 corresponds to the position of the heat conduction structure 6. The projections of the two on the packaging substrate 1 overlap, which allows the heat of the hot spot R to be dissipated in time, achieving a good heat dissipation effect.

[0064] like Figure 6aA stacked Fanout SIP chip packaging structure 10 is shown. The packaging substrate 1 includes a first rewiring layer 14, a molding layer 15, and a second rewiring layer 16 stacked together. The surface of the first rewiring layer 14 facing away from the second rewiring layer 16 corresponds to the first surface a1 of the packaging substrate 1, and the surface of the second rewiring layer 16 facing away from the first rewiring layer 14 corresponds to the second surface a2 of the packaging substrate 1. Electronic device 2 is coupled to the surface of the first redistribution layer 14 and is covered by the first package 31; the molding compound 15 is a ring structure with a hollow area in the center. Chip 4 is disposed in the hollow area of ​​the molding compound 15 to be disposed in the same layer as the molding compound 15. In the structural layer where the molding compound 15 and chip 4 are located, the molding compound 15 encapsulates chip 4 between the first redistribution layer 14 and the second redistribution layer 16, which is equivalent to chip 4 being coupled between the first redistribution layer 14 and the second redistribution layer 16, and covering chip 4 along the circumferential direction of chip 4; it should be understood that chip 4 can be regarded as a sheet structure with a small thickness (the thickness direction can be regarded as the radial direction of chip 4). Chip 4 has two opposing surfaces perpendicular to or approximately perpendicular to the thickness direction. Here, "circumferential direction" refers to the side located between the two surfaces. Both the first wiring layer 14 and the second wiring layer 16 include a dielectric layer 9 and an inner layer circuit 102 formed within the dielectric layer 9. To enable electrical signal conduction between the first wiring layer 14 and the second wiring layer 16, a connecting post 151 for connecting the first wiring layer 14 and the second wiring layer 16 is provided within the molding layer 15. The connecting post 151 can specifically be a copper pillar connector; the connecting post 151 can also be replaced with other types of connectors with structures such as connecting lines or metal vias, as long as electrical signal conduction between the first wiring layer 14 and the second wiring layer 16 can be achieved. A dielectric layer 9 is provided between the chip 4 and the second wiring layer 16. In the fabrication process, the chip 4 needs to be fixed onto the second wiring layer 16 first. Here, the dielectric layer 9 is used to fix the chip 4 onto the second wiring layer 16. Specifically, the dielectric layer 9 can be double-sided adhesive. After the chip 4 is fabricated and molded, the first wiring layer 14 is directly grown on the surface of the chip 4 facing away from the second wiring layer 16. The chip 4 has an internal connection terminal 81 on its surface facing the first package 31. A first connection terminal 82 is disposed in the second wiring layer 16, and is partially embedded within the second wiring layer 16 and protrudes from the side of the second wiring layer 16 opposite to the first wiring layer 14, to facilitate coupling with the circuit board for electrical signal connection. The electrical channel P formed within the package substrate 1 for connecting the electronic device 2 and the chip 4 can be formed by an inner layer circuit 102 disposed within the first wiring layer 14. Depending on requirements, vias 101 can also be provided at appropriate locations to achieve electrical conduction.On the surface of the first wiring layer 14 facing away from the second wiring layer 16, a first solder point 103 connected to the electrical channel P is provided (the first solder point 103 is connected to the inner layer circuit 102 here), and the electronic device 2 is connected to the first solder point 103; within the second wiring layer 16, a second solder point 104 connected to the electrical channel P is provided (the second solder point 104 is connected to the via 101 here), and the second solder point 104 is connected to the first connection terminal 82. The chip package structure 10, except for the side with the first connection terminal 82 (the side used for mating with the circuit board), has a protective coating 7 formed by sputtering. For heat dissipation of the hot spot R on the chip 4, a heat dissipation connection point 5 is specifically located on the surface of the first wiring layer 14 facing away from the second wiring layer 16 (equivalent to the heat dissipation connection point 5 being located on the first surface a1 of the package substrate 1); the electrical channel P located between the heat dissipation connection point 5 and the hot spot R can act as a heat conduction channel Q. Figure 6a In the example structure, the heat conduction channel Q is equivalent to being formed by the inner layer circuit 102, so that the heat of the hot spot R on the chip 4 is transferred to the surface of the first package 31 through the internal connection terminal 81, the inner layer circuit 102, the heat dissipation connection point 5 and the heat conduction structure 6.

[0065] Will Figure 6a The structure shown is cut along the plane containing CC to obtain... Figure 6b As shown in the structure, the hot spot R on chip 4 corresponds to the position of the heat-conducting structure 6, and their projections on the packaging substrate 1 overlap, allowing the heat from the hot spot R to be dissipated in a timely manner, achieving a good heat dissipation effect. It should be understood that, combined with... Figure 4a , Figure 5a and Figure 6a The structure of the chip packaging structure 10 shown can be flexibly configured according to different packaging structures. Furthermore, the fabrication of the thermal conductive structure 6 can be closely integrated with the entire fabrication process of the chip packaging structure 10 during the fabrication of the chip packaging structure 10.

[0066] It should be noted that the aforementioned molding layer 15 serves to encapsulate the chip 4, and its material is a common molding material, such as epoxy resin. Furthermore, the molding layer 15 can be made of the same material as the first package 31, or it can be different.

[0067] This application also provides a method for fabricating a chip packaging structure, used to fabricate the chip packaging structure 10 in the above embodiments. For example... Figure 7 As shown, the preparation method includes the following steps: Step S1: Provide a packaging substrate 1 with a chip 4 coupled thereto, the chip 4 having a hot spot R; the packaging substrate 1 has a first surface a1 and a second surface a2 opposite to each other, and the packaging substrate 1 has a heat conduction channel P communicating with the hot spot R.

[0068] Referring to the appendix in the above embodiments Figure 4a , Figure 5a and Figure 6a It can be seen that the "packaging substrate 1 with chip 4 coupled" here may have multiple forms, resulting in different possible positions of chip 4 on the packaging substrate 1. Figure 4a , Figure 5a and Figure 6a The structure of chip 4 on the packaging substrate 1 has already been clearly shown, so it will not be repeated here. In addition, common structures such as electronic device 2, via 101, inner layer circuit 102, first solder point 103, second solder point 104, and internal connection terminal 81 can be prepared according to conventional techniques in this field, so they are not described in detail here.

[0069] It should be noted that when chip 4 is located inside the packaging substrate 1 (e.g. Figure 4a or Figure 6a (Structure of chip 4), chip 4 is coupled to the packaging substrate 1 before step S1; while when chip 4 is located on the second surface a2 of the packaging substrate 1, chip 4 can be coupled to the packaging substrate 1 after the thermal conductive structure 6 is set.

[0070] Step S2: A heat dissipation connection point 5 connected to the heat conduction channel P is provided on the first surface a1 of the packaging substrate 1; the heat dissipation connection point 5 can be specifically exemplified by the structure of a heat dissipation pad; Step S3: A first package body 31 with a heat conduction structure 6 is formed on the first surface a1 of the packaging substrate 1, the heat conduction structure 6 extending from the heat dissipation connection point 5 to the surface of the first package body 31; at this point, the positional structure of the packaging substrate 1, the heat conduction structure 6, and the heat dissipation connection point 5 can be referred to Figure 8 As shown.

[0071] Specifically, in order to form Figure 8 The structure shown can be implemented in different ways, including step S3. One specific implementation is as follows: Figure 9 As shown, step S3 may include the following steps: Step S311: A heat-conducting structure 6 is generated on the heat dissipation connection point 5 by means of welding, growth, etc., to obtain the following... Figure 10 The structure shown; Step S312: A first package 31 is formed on the first surface a1 of the packaging substrate 1, and the end of the thermally conductive structure 6 away from the heat dissipation connection point 5 is located on the surface of the first package 31, resulting in... Figure 8 The structure shown.

[0072] Another specific implementation, such as Figure 11 As shown, step S3 may include the following steps: Step S321: Forming a first package 31 on the first surface a1 of the packaging substrate 1, thereby obtaining... Figure 12aThe structure shown; Step S322: An inward opening is made on the surface of the first package 31 to form a pre-set hole 311 communicating with the heat dissipation connection point 5, resulting in Figure 12b The structure shown; Step S323: Generate a heat-conducting structure 6 within the pre-placed hole 51, to obtain Figure 8 The structure shown.

[0073] Then, step S4 is performed: a first connection terminal 82 is formed on the second surface a2 of the packaging substrate 1. After step S4, the surface of the entire structure having the first package 31 needs to be ground to reduce the height of the entire structure to the designed height; in order to protect the structure, a protective coating 7 can also be formed on the surface of the first package 31, and the protective coating 7 can cover the entire structure except for the surface of the second surface a2 of the packaging substrate 1.

[0074] Based on the chip packaging structure 10 provided in the above embodiments, this application also provides a packaging system 100. Figure 4a , Figure 5a and Figure 6a The three structures shown in this application embodiment can be used to encapsulate the packaging system 100. Figures 13a to 13c Provide an example.

[0075] Specifically, Figure 3a A double-sided surface mount SIP packaging system 100 is shown, which includes Figure 4a The illustrated chip package structure 10 and circuit board 20 are connected, with the circuit board 20 coupled to the chip package structure 10 via a first connection terminal 82. The first connection terminal 82 may specifically be a solder ball, and it can be connected to the circuit board 20 to enable electrical signal conduction between the chip package structure 10 and the circuit board 20.

[0076] and Figure 13b This illustrates a SiP (Semiconductor In-Package) packaging system 100 embedded in a semiconductor substrate, which includes... Figure 5a The illustrated chip package structure 10 and circuit board 20 are shown, with the circuit board 20 also coupled to the chip package structure 10 via a first connection terminal 82. The first connection terminal 82 may specifically be a solder ball, and it can be connected to the circuit board 20 to enable electrical signal conduction between the chip package structure 10 and the circuit board 20.

[0077] Similarly, Figure 13c A stacked Fanout SIP-based packaging system 100 is shown, comprising: Figure 6aThe illustrated chip package structure 10 and circuit board 20 are shown, with the circuit board 20 also coupled to the chip package structure 10 via a first connection terminal 82. The first connection terminal 82 may specifically be a solder ball, and it can be connected to the circuit board 20 to enable electrical signal conduction between the chip package structure 10 and the circuit board 20.

[0078] In the above embodiment, the circuit board 20 can export the signal from the chip 4 and connect it to external devices, thereby helping the system to achieve its functions. The circuit board 20 can be a PCB, FPC, or FPCB; the appropriate circuit board 20 can be selected according to the application scenario.

[0079] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: Packaging substrate, chip, electronic device, and first package; The chip is coupled to the packaging substrate, and the chip has a hot spot; The packaging substrate has a first surface and a second surface opposite to each other. The first surface is provided with a heat dissipation connection point, and a heat conduction channel is formed in the packaging substrate to connect the heat dissipation connection point and the hot spot. The second surface is provided with a first connection terminal for connecting external devices; The first package is disposed on the first surface, and a thermally conductive structure is formed in the first package. One end of the thermally conductive structure is connected to the heat dissipation connection point, and the other end extends along a direction perpendicular to the packaging substrate to the surface of the first package away from the packaging substrate. The electronic device is disposed on the first surface and spaced apart from the heat dissipation connection point. The first package covers the electronic device. An electrical channel connecting the electronic device and the chip is formed in the package substrate. The electronic device is a passive device. Along a direction perpendicular to the packaging substrate, the orthographic projection of the electronic device on the packaging substrate does not overlap with the orthographic projection of the thermal conductive structure on the packaging substrate; The thermal resistance of the thermally conductive structure is lower than that of the first package.

2. The chip packaging structure as described in claim 1, characterized in that, The heat dissipation connection point is a heat dissipation pad.

3. The chip packaging structure as described in claim 1, characterized in that, The packaging substrate includes a substrate, a first solder resist layer is formed on the side of the substrate facing the first package, and a second solder resist layer is formed on the other side of the substrate away from the first package.

4. The chip packaging structure as described in claim 3, characterized in that, Also includes: A second package is coupled to the second surface, and the first connection terminal protrudes from the second package; The chip is coupled to the second surface, which is the side of the second solder mask layer that faces away from the first package, and the second package is used to cover the chip.

5. The chip packaging structure as described in claim 3, characterized in that, The chip is embedded in the substrate.

6. The chip packaging structure as described in claim 1, characterized in that, The packaging substrate includes a first rewiring layer, a molding layer, and a second rewiring layer stacked together, and the molding layer is provided with a connector for connecting the first rewiring layer and the second rewiring layer; The chip is coupled between the first redistribution layer and the second redistribution layer and is circumferentially covered by the molding compound. The second redistribution layer has a first pad for connecting the first connection terminal and a via for connecting the first pad and the connector.

7. The chip packaging structure as described in claim 6, characterized in that, Also includes: A dielectric layer is disposed between the chip and the second redistribution layer to fix the chip to the second redistribution layer.

8. The chip packaging structure as described in claim 1, characterized in that, The chip has a second connection terminal on the side facing the first package for connecting to the package substrate.

9. The chip packaging structure as described in any one of claims 1-8, characterized in that, Also includes: A protective coating formed on the surface of the first package.

10. A packaging system, characterized in that, The device includes a circuit board and a chip package structure as described in any one of claims 1-9, wherein the circuit board is coupled to the chip package structure via the external connection terminal.

11. A method for fabricating a chip packaging structure, characterized in that, include: A packaging substrate with a chip coupled thereto, the chip having a hot spot is provided; The packaging substrate has a first surface and a second surface opposite to each other, and the packaging substrate has a thermally conductive channel communicating with the hot spot and an electrical channel communicating with the chip. A heat dissipation connection point and an electronic device are disposed on the first surface of the packaging substrate. The heat conduction channel is connected to the heat dissipation connection point. The electronic device is a passive device and is spaced apart from the heat dissipation connection point. The electronic device is connected to the electrical channel. A first package with a thermally conductive structure is formed on the first surface of the packaging substrate. The first package encapsulates the electronic device. One end of the thermally conductive structure is connected to the heat dissipation connection point, and the other end extends along a direction perpendicular to the packaging substrate to the surface of the first package away from the packaging substrate. The thermal resistance of the thermally conductive structure is lower than that of the first package. Along a direction perpendicular to the packaging substrate, the orthographic projection of the electronic device on the packaging substrate does not overlap with the orthographic projection of the thermal conductive structure on the packaging substrate; A first connection terminal is formed on the second surface of the packaging substrate.

12. The preparation method according to claim 11, characterized in that, A first package having a thermally conductive structure is formed on a first surface of the packaging substrate. The first package encapsulates the electronic device. The thermally conductive structure extends from the heat dissipation connection point to the surface of the first package facing away from the packaging substrate, including: A heat-conducting structure is generated at the heat dissipation connection point; A first package is formed on the first surface of the packaging substrate, and one end of the thermally conductive structure away from the heat dissipation connection point is located on the surface of the first package.

13. The preparation method according to claim 11, characterized in that, A first package having a thermally conductive structure is formed on a first surface of the packaging substrate. The first package encapsulates the electronic device. The thermally conductive structure extends from the heat dissipation connection point to the surface of the first package facing away from the packaging substrate, including: A first package is formed on the first surface of the packaging substrate; An inwardly formed hole is made on the surface of the first package to form a pre-set hole communicating with the heat dissipation connection point; A heat-conducting structure is generated within the pre-set hole.

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