Data reading method, memory and device

Abstract

This application provides a data reading method, a memory, and a device. The method includes: determining a first reading voltage based on the reading voltage used for M data reads of a storage region, the storage region including at least one memory cell; the first i-1 data reads of the storage region including the M data reads, where M is less than i, and both M and i are positive integers; and performing the i-th data read of the storage region based on the first reading voltage. This avoids using a fixed reading voltage for each data read, which could lead to data read failures, and improves the accuracy of data reading.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data reading method, memory, and device. Background Technology

[0002] Phase-change memory (PCM) is a type of memory that stores data by utilizing the difference in conductivity exhibited by a special material when it transitions between crystalline and amorphous states. This material is called a phase-change material. Due to the characteristics of phase-change materials, the read voltage will drift over time after data is written. In this case, reading data from a PCM using a relatively stable read voltage results in lower accuracy of the read data, leading to a higher failure rate for data read operations. Summary of the Invention

[0003] This application provides a data reading method, a memory, and a device to achieve accurate reading of data stored in a PCM.

[0004] In a first aspect, embodiments of this application provide a data reading method, the method comprising: determining a first reading voltage based on the reading voltage used for M data readings of a storage interval, the storage interval comprising at least one storage unit, the M data readings being part or all of the first i-1 data readings of the storage interval, M being less than i, and M and i being both positive integers; and performing the i-th data reading of the storage interval based on the first reading voltage.

[0005] Secondly, embodiments of this application provide a memory, including: a processing module, configured to determine a first reading voltage based on the reading voltage used for M data reads of the memory region, the memory region including at least one memory cell, the M data reads being part or all of the first i-1 data reads of the memory region, M being less than i, and M and i being both positive integers; and a storage module, configured to perform the i-th data read of the memory region based on the first reading voltage.

[0006] Thirdly, embodiments of this application provide an electronic device, including: a memory, the memory including a module for performing the method of the first aspect.

[0007] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the method provided in the first aspect.

[0008] Fifthly, embodiments of this application provide a computer program product including computer instructions that, when executed by a processor, implement the method provided in the first aspect.

[0009] In this embodiment, the reading voltage for the i-th data read is determined based on the reading voltage used in the M data reads prior to the i-th data read in the storage interval. This enables prediction of the reading voltage for the i-th data read, avoiding the use of a fixed reading voltage for each data read, which could lead to data read failure and improves the accuracy of data read. Attached Figure Description

[0010] Figure 1 A schematic diagram of a memory frame provided for an embodiment of this application;

[0011] Figure 2 This is a schematic diagram of an application scenario provided by an embodiment of this application;

[0012] Figure 3 A flowchart illustrating a data reading method provided in an embodiment of this application;

[0013] Figure 4 This is a flowchart illustrating another data reading method provided in an embodiment of this application. Detailed Implementation

[0014] Figure 1 This is a schematic diagram of the framework of a memory 100 provided in an embodiment of this application. Figure 1 As shown, the memory 100 may include a processing module 110, a storage module 120, and an input / output module 130. The processing module 110, the storage module 120, and the input / output module 130 may be interconnected.

[0015] The storage module 120 may include an electrical control unit 121, multiple storage cells (122-1 to 122-n), and a read unit 123. The multiple storage cells (122-1 to 122-n) may form a storage array. A storage cell (such as any one of 122-1 to 122-n), also called a memory unit, can be an electronic circuit for storing information. It can be used to store one or more bits of binary information and has various logical states associated with the stored bits. The logical states can be represented by binary values ​​(such as "0" and "1") or combinations of these values.

[0016] like Figure 1 As shown, the storage cell (e.g., 122-1) may include an upper electrode 1221, a phase change material 1222, a resistor 1223, and a lower electrode 1224. A write pulse signal is provided to the storage cell (e.g., 122-1) through the upper electrode 1221 and the lower electrode 1224. The resistor 1223 experiences a temperature change under the influence of the write pulse signal, thereby altering the temperature of the phase change material in contact with one end of it.

[0017] The aforementioned write pulse signals can include a reset (RESET) pulse and a set (SET) pulse. Under the action of the RESET pulse, the temperature of resistor 1223 increases, causing the temperature of the phase change material to rise to its melting point. During the fall time of the RESET pulse, the temperature of resistor 1223 decreases, quenching and forming an amorphous state. When the phase change material is in the amorphous state, the state of the phase change material can be called the RESET state, and the logic state of the corresponding bit in the storage cell is "0". Under the action of the SET pulse, the temperature of resistor 1223 increases, causing the temperature of the phase change material to rise to a temperature higher than the crystallization temperature but lower than the melting point temperature, causing the phase change material to form a crystalline state. At this time, the state of the phase change material can be called the SET state, and the logic state of the corresponding bit in the storage cell is "1".

[0018] Based on this, after applying a read voltage to the storage cell (such as 122-1), the read unit 123 can determine the logic state on the corresponding bit by detecting the resistance value of the phase change material in the storage cell (or the voltage across the phase change material), thereby realizing the reading of data from the storage cell.

[0019] It should be noted that the storage region mentioned below may include at least one of the above-described storage cells, and the same read voltage may be applied to the storage cells within each storage region. For example, the memory may be a package of one or more dies, each die containing one or more planes, each plane containing a set of physical blocks, each physical block containing a set of contiguous or non-contiguous memory pages, the physical block being the smallest erasable unit of the memory, and the memory page being the smallest writable unit of the memory. Each memory page may contain a set of memory cells. Continuing with the above examples, a storage region may be one or more dies, one or more planes, one or more physical blocks, one or more memory pages in the memory, or a row of memory cells, a column of memory cells, etc., within a memory page; this application does not limit this. A storage cell may also be a row of cells.

[0020] It should also be understood that multiple storage cells (122-1 to 122-n) can all be storage cells with the same structure, or at least partially have the same structure, or all have different structures. This application does not limit this. Generally, storage cells within the same storage range have the same structure. For example, storage cells (122-1 to 122-m) in storage range 12 are all storage cells with the same structure, for example, they all have the same structure as storage cell 122-1.

[0021] See Figure 1The electronic control unit 121 can be implemented as an electronic circuit and electrically connected to a plurality of storage cells (122-1 to 122-n) for providing voltage to each storage cell to drive reading data from one or more storage cells or writing data to one or more storage cells.

[0022] See Figure 1 The input / output module 130 can be used to receive data read instructions or data write instructions from external devices, so as to read data from the storage unit according to the data read instructions and write data to the storage unit according to the data write instructions; the input / output module 130 can also send the read data to external devices.

[0023] See Figure 1 After receiving a data read instruction, the processing module 110 can control the components in the memory to read data, for example, by sending a data read control instruction to the electronic control unit 121 so that the electronic control unit 121 provides voltage to drive the reading of data in the storage area; the processing module 110 can also control the components in the memory to write data after receiving a data write instruction, for example, by sending a data write control instruction to the electronic control unit 121 so that the electronic control unit 121 provides a write pulse signal to write data into the storage area.

[0024] Because the resistance of phase change materials (PCMs) is temperature-dependent, its resistance varies with temperature. After data is written under the influence of a write pulse signal, the temperature of the PCM changes over time. For example, the PCM temperature may rise under the influence of the write pulse signal, causing it to form a crystalline or amorphous state, and then gradually decrease. Consequently, the resistance of the PCM decreases as the temperature drops; this change is called resistance drift. The decrease in resistance also leads to a decrease in the voltage across the PCM, hence the term voltage drift. In this situation, when a fixed read voltage is applied to the memory cell, the voltage drift of the PCM can cause the read information to be flipped (e.g., reading logic state "0" as logic state "1", or logic state "1" as logic state "0"), resulting in lower accuracy of the read data.

[0025] To improve the accuracy of data reading, this application provides a reading voltage control scheme. Based on the reading voltage used in the M data readings prior to the i-th data reading in the storage interval, the reading voltage for the i-th data reading is determined, thereby predicting the reading voltage for the i-th data reading. This avoids using a fixed reading voltage for each data reading, which could lead to data reading failure and improves the accuracy of data reading.

[0026] In order to implement the reading voltage control scheme of this application, Figure 1The processing module 110 can be used to determine the first read voltage for driving each memory interval and output the corresponding first read voltage to the connected memory interval in order to achieve accurate reading of data in the memory interval.

[0027] The processing module 110 can be implemented as a processing chip in the memory 100. By running the stored program, it executes the data reading method in this embodiment to read data from the memory 100.

[0028] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the processing module 110 to execute the data reading method in the above method embodiment to read data from the memory 100.

[0029] It should be understood that the computer program code may be stored in the aforementioned memory 100, or in other memory, or in a storage unit in memory 100 that does not contain phase change material.

[0030] Of course, this application does not limit the processing module for determining the first read voltage to be deployed in the memory. For example, the processing module may be deployed independently of the memory 100, or the first read voltage may be determined by a processor outside the memory 100.

[0031] Figure 2 This is a schematic diagram illustrating an application scenario provided by an embodiment of this application. For example... Figure 2 As shown, the electronic device 10 includes the aforementioned memory 100. Optionally, the electronic device 10 may also include a processor 200.

[0032] The processor 200 and the memory 100 can communicate with each other through an internal connection path to transmit control and / or data signals. For example, the processor 200 can send a data read instruction or a data write instruction to the memory 100; or, for example, the processor 200 can receive a data read result or a data write result sent by the memory 100.

[0033] The processor 200 can also be deployed with Figure 1 The processing module 110 in the memory 100 is used to determine the first read voltage of each memory region in the memory 100. The processor 200 can execute the data reading method of the embodiments of this application by running the stored program to read data from the memory 100.

[0034] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the processor 200 to execute the data reading method in the above method embodiment to read data from the memory 100.

[0035] It should be understood that the computer program code can be stored in memory 100, or other memory, or in a storage cell within memory 100 that does not contain phase change material. This application does not limit the memory used to store the computer program code; it can include, but is not limited to, volatile memory or non-volatile memory, or both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0036] It should be understood that the aforementioned processor can be one or more chips. For example, the processor can be a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0037] The electronic device 10 can be implemented as any terminal device, such as a regular PC, mobile phone, tablet computer, smart wearable device, computer with wireless transceiver function, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc.

[0038] The electronic device 10 can also be implemented as a regular server, a server cluster, or a cloud server or server cluster.

[0039] The division of modules or units in this application is only an example and not a limiting illustration. In actual implementation, there may be other division methods, such as multiple units or modules being combined or integrated into another system.

[0040] It should be noted that the memory in the embodiments of this application (such as...) Figure 1 or Figure 2 The memory 100 in the memory may include memory cells having phase change materials (such as...) Figure 1The memory in 122-1) can be any memory with voltage drift characteristics, and this application does not limit it.

[0041] The data reading method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] For ease of understanding, the embodiments of this application use memory (such as...) Figure 1 and Figure 2 The processing module and storage module in (100) are used as examples of the execution subject to illustrate the method provided in this application embodiment. The execution subject of the data reading method provided in this application embodiment can also be an electronic device (such as...). Figure 2 Electronic devices 10 in the middle.

[0043] Figure 3 This is a flowchart illustrating a data reading method provided in an embodiment of this application. Figure 3 As shown, the method 300 includes:

[0044] S310, determine the first reading voltage based on the reading voltage used for each of the M data reads of the storage area, the storage area includes at least one storage cell, the M data reads are part or all of the first i-1 data reads of the storage area, M is less than i, and M and i are both positive integers;

[0045] S320, based on the first read voltage, performs the i-th data read from the storage region.

[0046] It should be noted that the processing module can respond to the received data read instruction and execute the process of determining the first read voltage in S310 above; or the processing module can execute the process of determining the first read voltage in S310 above after the (i-1)th data read, and the storage module can respond to the received data read instruction and execute the i-th data read above.

[0047] The data read instruction can be generated by the processor 200. For example, when a user interacts with the electronic device, it needs to read data from the memory. The processor 200 in the electronic device 10 can generate a data read instruction, which can include the access address of the memory range. The processor 200 sends the data read instruction to the memory, and the processing module in the memory performs the i-th data read from the corresponding memory range according to the data read instruction.

[0048] As mentioned above, the process of determining the first read voltage can also be implemented by a processor in an electronic device. The processor can generate a data read instruction, which includes the first read voltage. The processor sends the data read instruction to the memory to realize the i-th data read in the memory region.

[0049] It should be understood that in this embodiment, the number of data reads from the storage area needs to be accumulated and recorded to record the reading voltage used for each data read. Before S310 is executed, the number of reads can be initialized. For example, the number of reads can be initialized after data is written to the storage area, or the read data can be initialized in response to user operation, or the read data can be initialized periodically. This application does not limit this. Depending on the stage of read data initialization, the data read in the storage area during the i-th data read process can be the same or different. For example, if the number of reads is initialized each time data is written, the data in the storage area is the same during the i-th data read process. Or, if multiple different data are written after the number of reads is initialized, the data in the storage area is different during the i-th data read process.

[0050] In S310 above, the processing module can predict the reading voltage (such as the first reading voltage) used in the i-th data read based on the reading voltage used in the M data reads in the previous i-1 data reads. Generally, the M data reads can be the M most recent data reads, for example, the M data reads can be the data reads from iM to i-1, which can improve the accuracy of the prediction of the first reading voltage. Of course, this application does not limit this, that is, the M data reads can be any M data reads in the previous i-1 data reads. For example, in order to save storage space, the reading voltage can be recorded intermittently, such as recording the reading voltage once every 2 data reads. Optionally, M equals 7. Optionally, the voltage used in the M data reads can be recorded in a data table. When there is a new data read operation, the reading voltage used in the new read operation can be updated in the data table. The data table can only store the reading voltage used in the most recent M data reads.

[0051] In a first example, the processing module can determine the first reading voltage based on the reading voltage used in the Mth data read (i.e., the read voltage most recent to the i-th data read among the M data reads). For example, the reading voltage used in the Mth data read can be used as the first reading voltage, or the sum of the reading voltages used in the M data reads and a preset voltage offset can be used as the first reading voltage.

[0052] In the second example, the processing module can determine the first reading voltage based on the reading voltage used most frequently among the reading voltages used in the M data reads. For example, the reading voltage used most frequently can be used as the first reading voltage, or the sum of the reading voltage used most frequently and a preset voltage offset can be used as the first reading voltage.

[0053] In the third example, the processing module can calculate and determine the first reading voltage based on the reading voltage used in the M data reads. For example, it can calculate the mean and variance of the reading voltage used in the M data reads and use the calculation result as the first reading voltage, or use the sum of the calculation result and the preset voltage offset as the first reading voltage.

[0054] The aforementioned preset voltage offset is related to the voltage drift parameter of the phase change material in the storage unit. If the voltage drift parameter indicates that the voltage drift of the phase change material changes over time is large, then the preset voltage offset is large; if the voltage drift parameter indicates that the voltage drift of the phase change material changes over time is small, then the preset voltage offset is small.

[0055] The first example described above can save computing resources and has high processing efficiency. This first example is particularly suitable for scenarios with frequent data reads. When data reads from the storage region are frequent, the shorter the interval between the i-th data read and the M-th data read, the smaller the voltage drift. In this case, using the same or similar (with a preset voltage offset) read voltage as the M-th data read for the i-th data read increases the probability of successfully reading the data.

[0056] The second example above is applicable to scenarios where the timing of data reading is regular. For example, the time between data reading and data writing (including rewriting due to memory refresh) is basically within the same time interval. The first data voltage and the reading voltage used most frequently in the M data readings have a higher probability of successfully reading data.

[0057] The third example above is suitable for scenarios where the timing of data reading is irregular or complex. The mean or variance calculated through M data readings will more easily improve the accuracy of the i-th data reading, or in other words, increase the success rate of data reading.

[0058] It should be noted that the cumulative resistance drift of the PCM medium may cause information reversal, thus requiring a refresh operation. A refresh operation refers to the process of rewriting the memory cell, re-saving the data that is about to expire, thereby maintaining its storage state. PCM refresh operations can be performed periodically.

[0059] In the above S320, the processing module can send the first read voltage to the storage module, or the processing module can carry the first read voltage in the control signal for data reading and send the control signal to the storage module, so that the storage module can use the first read voltage to perform the i-th data reading to read the data stored in the storage area. For example, after the electrical control unit in the storage module receives the first read voltage or the control signal carrying the first read voltage, it outputs the first read voltage to each storage unit in the storage area. After each storage unit applies the first read voltage, the reading unit detects the resistance value of the phase change material (or the voltage value across the phase change material) to obtain the reading result, and then outputs the reading result through the input / output module.

[0060] This application's embodiments predict the first read voltage for the i-th data read based on the read voltage used in the M data reads during the first i data reads of the storage region. The predicted first read voltage can better avoid the impact of voltage drift on the accuracy of data reading during the i-th data read of the storage region. From one perspective, it can achieve accurate data reading results during the i-th data read; from another perspective, in the i-th data read, data is successfully read using the first read voltage, avoiding the need to adjust the read voltage and improving the efficiency of data reading.

[0061] Considering the time relationship between the read voltage and the data rewritten during the memory refresh operation, the refresh cycle of the memory region (i.e., the memory) can be divided into time intervals to obtain N time intervals. Based on the voltage drift parameters of each time interval and the memory region, the candidate read voltage corresponding to that time interval is determined. Since the N time intervals cover the memory refresh cycle, the first read voltage suitable for the voltage drift during the i-th data read can be determined from the N candidate read voltages corresponding to the N time intervals, thus improving the processing efficiency of determining the first read voltage.

[0062] For example, assuming the memory's refresh cycle is 48 hours (h), the refresh cycle can be divided into three time intervals: the first time interval (0, 1ms), the second time interval (1ms, 100ms), and the third time interval (100ms, 48h). Based on experimental data or historical usage records of the memory, and using statistical methods, the read voltage used for each time interval in a successful data read process can be selected as the candidate read voltage for that time interval. One of these three candidate read voltages will accurately read the data in the memory interval during the i-th data read.

[0063] The following is combined Figure 4An exemplary illustration is provided on how to determine the first read voltage based on N time intervals.

[0064] Figure 4 This is a flowchart illustrating another data reading method provided in an embodiment of this application. Figure 4 As shown, the method 400 includes:

[0065] S410, determine the first read voltage;

[0066] S420, based on the first read voltage, perform the i-th data read from the storage area;

[0067] S430, Verify the result of the i-th data read;

[0068] If the result of the i-th data read passes verification, execute S440 as follows; if the result of the i-th data read fails verification, execute S450 as follows.

[0069] S440, end the i-th data reading process;

[0070] S450: Select one candidate read voltage from N candidate read voltages and use this candidate read voltage as the first read voltage. Repeat steps S420 to S450 until the result of the i-th data read passes verification, ending the i-th data read process. It should be understood that the first read voltage used in each execution of the i-th data read of the storage region is different; that is, the candidate read voltage determined after each data read result verification failure is a different candidate read voltage from the N candidate read voltages.

[0071] In the above S410, the first read voltage can be determined through the following possible implementations:

[0072] Implementation Method 1: The processing module can determine the first read voltage based on the read voltage used for M data reads from the storage area. Figure 3 Similar to S310 in the example above, the processing module can determine the first read voltage based on any one of the first to third examples described above. In this first embodiment, the first read voltage is not limited to belonging to the N candidate read voltages.

[0073] Implementation Method 2: The processing module can determine the first read voltage from N candidate read voltages based on the read voltage used for M data reads from the storage area.

[0074] In the second implementation described above, the reading voltage used in the M data reads can be included among the N alternative reading voltages. In this case, the processing module can determine the reading voltage used in the Mth data read out of the M data reads as the first reading voltage; or the processing module can determine the reading voltage used most frequently out of the M data reads as the first reading voltage.

[0075] In the second implementation described above, at least some of the read voltages used in the M data reads are not included in the aforementioned N candidate read voltages. In this case, the processing module can determine a voltage prediction value based on the read voltages used in the M data reads of the storage area, and determine a first read voltage from the N candidate read voltages based on the voltage prediction value.

[0076] For example, the processing module can determine the reading voltage used in the Mth data read out of M data reads as the voltage prediction value; or, the processing module can determine the reading voltage used most frequently in the M data reads as the voltage prediction value; or, the processing module can calculate the voltage prediction value based on the reading voltage used in the M data reads, for example, by calculating the mean or variance of the reading voltage used in the M data reads, and determine the calculated mean or variance as the voltage prediction value.

[0077] Continuing with the example above, the processing module can determine the first read voltage from among N candidate read voltages that has the smallest difference from the predicted voltage value, based on the determined voltage prediction value.

[0078] Implementation Method 3: The first read voltage can be a preset default read voltage. In this case, the processor does not need to predict the first read voltage used for the i-th data read. This implementation method 3 can be applied to scenarios with a low number of historical reads, such as when reading data from the first to the M-th data read of a memory region, the default read voltage can be used for data reading.

[0079] The default read voltage can be the initial default read voltage with the highest probability determined based on the data read / write characteristics of a specific application scenario and experimental or testing methods. Optionally, the default read voltage can belong to N alternative read voltages.

[0080] The above S420 and Figure 3 The S320 in this article is the same as or similar to the S320 in this article, and will not be elaborated here.

[0081] In S430 above, the Error Correcting Code (ECC) module in the memory can verify the result of the i-th data read to determine whether the result of the i-th data read is accurate. If the result of the i-th data read has no error, the verification passes; if the result of the i-th data read has an error, the verification fails.

[0082] When the verification of the result of the i-th data reading by S430 fails, the processing module can use some or all of the N candidate reading voltages as the first reading voltage, and perform the i-th data reading in sequence until the result of the i-th data reading passes the verification, and then end the i-th data reading process.

[0083] If the first read voltage determined in S410 does not belong to the N candidate read voltages, for example, in the case where the default read voltage does not belong to the N candidate read voltages in the above implementation method one or the above implementation method three, in S450, the processing module can sequentially perform the i-th data read according to the N candidate read voltages until the result of the i-th data read passes the verification.

[0084] The processing module can sequentially read data based on N candidate reading voltages in ascending order of the difference between the candidate reading voltage and the first reading voltage determined in S430.

[0085] The first read voltage determined in S410 above belongs to N candidate read voltages. For example, in the case where the default read voltage belongs to N candidate read voltages in the above implementation method 2 or Shangshu Province implementation method 3, in S450, the processing module can sequentially perform the i-th data read according to the N-1 candidate read voltages other than the first read voltage determined in S410 among the N candidate read voltages, until the result of the i-th data read passes the verification.

[0086] The processing module can sequentially read data based on N-1 alternative reading voltages other than the first reading voltage determined in S410, in ascending order of the difference between the alternative reading voltages and the first reading voltage determined in S430.

[0087] In some embodiments, after the result verification of the i-th data read passes, the memory can save the read voltage used in the i-th data read. For example, the processing module can send a data write control command to the electronic control unit, which can write the read voltage used in the i-th data read into the static random access memory (SRAM) and the read voltage used in the i-th data read into the data table of the dynamic random access memory (DRAM) according to the control command, so that the data table is updated to save the read voltage used in the most recent M data reads, including the i-th data read.

[0088] The method provided in this application provides N alternative voltages for the finally determined first read voltage. When the i-th data read fails (i.e., the result verification of the i-th data read fails) based on the predicted first read data, an alternative read voltage is selected from the N alternative read voltages, and the i-th data read is performed again. Each alternative read voltage can be applied to a time interval within the refresh cycle, and the N time intervals can cover the refresh cycle. Therefore, an alternative read voltage that satisfies the voltage drift amount of the i-th data read can definitely be determined from the alternative read voltages, reducing the number of read voltage adjustments and improving data read efficiency.

[0089] It should be noted that the modules or components described in the above embodiments can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), etc. Furthermore, when one of the above modules is implemented through processing element scheduler code, the processing element can be a general-purpose processor, such as a CPU or other processor capable of calling program code, such as a controller. Additionally, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0090] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0091] The term "multiple" in this document refers to two or more. The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the preceding and following related objects; in formulas, " / " indicates a "division" relationship. Additionally, it should be understood that in the description of this application, words such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0092] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0093] It is understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

Claims

1. A data reading method, characterized in that, The method includes: The first reading voltage is determined based on the reading voltage used for each of the M data reads of the storage area. The storage area includes at least one storage unit. The M data reads are part or all of the first i-1 data reads of the storage area. M is less than i, and both M and i are positive integers. Based on the first read voltage, the storage region is read for the i-th time; The refresh cycle of the storage region includes N time intervals, where N is an integer greater than 1. Determining the first read voltage based on the read voltage used for M data reads of the storage region includes: Based on the read voltage used for M data reads from the storage region, the first read voltage is determined from N candidate read voltages; wherein, The N candidate read voltages correspond one-to-one with the N time intervals, and the candidate read voltages are determined based on the voltage drift of the storage interval in the corresponding time interval.

2. The method according to claim 1, characterized in that, The N alternative reading voltages include the reading voltages used for each of the M data readings; The step of determining the first read voltage from the N candidate read voltages based on the read voltages used for M data reads of the storage region includes: The reading voltage used in the Mth data reading out of the M data readings is determined as the first reading voltage; or... The reading voltage that is used most frequently in the M data reads is determined as the first reading voltage.

3. The method according to claim 1, characterized in that, The N alternative read voltages include at most a subset of the read voltages used in the M data reads; The step of determining the first read voltage from the N candidate read voltages based on the read voltages used for M data reads of the storage region includes: The voltage prediction value is determined based on the reading voltage used for M data reads from the storage area; The first read voltage is determined from the N candidate read voltages based on the voltage prediction value.

4. The method according to claim 3, characterized in that, The step of determining the voltage prediction value based on the read voltage used for each of the M data reads from the storage region includes: The voltage used for the Mth data read in each of the M data reads is determined as the predicted voltage value; or... The voltage most frequently used in the M data reads is determined as the predicted voltage value; or... The average of the reading voltages used in the M data readings is determined as the predicted voltage value.

5. The method according to claim 3 or 4, characterized in that, The step of determining the first read voltage from the N candidate read voltages based on the predicted voltage value includes: The candidate reading voltage with the smallest difference from the predicted voltage value among the N candidate reading voltages is taken as the first reading voltage.

6. The method according to any one of claims 1 to 4, characterized in that, Also includes: The result of the i-th data read is verified; The result of the i-th data read passes the verification, and the i-th data read process ends. If the verification of the result of the i-th data read fails, the N-1 alternative reading voltages (excluding the first reading voltage) from the N alternative reading voltages will be used to sequentially read the data from the storage area for the i-th time, and the result of the i-th data read will be verified until the result of the i-th data read passes the verification, at which point the i-th data read process ends.

7. The method according to claim 6, characterized in that, Also includes: After the result of the i-th data read passes verification, the reading voltage used in the i-th data read is saved.

8. The method according to any one of claims 2 to 4, characterized in that, The method further includes: Based on the voltage drift parameters of the N time intervals and the storage interval, the N candidate read voltages are determined respectively. The voltage drift parameters are used to indicate the amount of voltage drift caused by the change of the resistance of the storage interval over time.

9. A memory, characterized in that, include: The processing module is used to determine a first reading voltage based on the reading voltage used for each of the M data reads of the storage area. The storage area includes at least one storage unit. The M data reads are part or all of the first i-1 data reads of the storage area, where M is less than i and both M and i are positive integers. The storage module is used to perform the i-th data read from the storage area based on the first read voltage; The refresh cycle of the storage region includes N time intervals, where N is an integer greater than 1. The processing module is specifically used to determine the first read voltage from N candidate read voltages based on the read voltages used for M data reads of the storage region; wherein... The N candidate read voltages correspond one-to-one with the N time intervals, and the candidate read voltages are determined based on the voltage drift of the storage interval in the corresponding time interval.

10. An electronic device, characterized in that, include: A memory, the memory comprising a module for performing the method according to any one of claims 1 to 8.

11. The electronic device according to claim 10, characterized in that, The memory includes a processing module and a storage module; The storage module stores computer instructions; The processing module executes the computer instructions stored in the storage module, causing the processing module to perform the method as described in any one of claims 1 to 8.

12. The electronic device according to claim 11, characterized in that, It also includes a processor, which is used to instruct the memory to read or write data.

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