Display device with light blocking pattern

Abstract

Provided is a display device having a light-blocking pattern, including: a light-blocking pattern on a pixel region of a device substrate; an upper buffer layer on the light-blocking pattern, extending on a bending region of the device substrate; a switching thin film transistor on the upper buffer layer of the pixel region, including a first semiconductor pattern separated from the light-blocking pattern; a separation insulating layer on the first semiconductor pattern, extending on the upper buffer layer of the bending region; a driving thin film transistor on the separation insulating layer of the pixel region, including a second semiconductor pattern overlapping a part of the light-blocking pattern; a bending opening on the bending region of the device substrate, including a first bending hole exposing a part of the upper buffer layer and a second bending hole in the first bending hole; and an intermediate electrode on the separation insulating layer of the pixel region, connected to the light-blocking pattern via an intermediate contact hole, the intermediate contact hole including a first intermediate hole and a second intermediate hole, a vertical depth of the first intermediate hole being the same as a vertical depth of the first bending hole.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0111006, filed on August 23, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a display device wherein a light-blocking pattern is provided in each pixel area. Background Technology

[0004] Typically, a display device provides an image to a user. For example, a display device may include multiple pixel areas. A light-emitting device may be disposed in each pixel area. The light-emitting device may emit light that displays a specific color. For example, the light-emitting device may include a light-emitting layer between a first electrode and a second electrode.

[0005] A driving circuit electrically connected to the light-emitting device can be disposed in each pixel region. The driving circuit can apply a driving current corresponding to the data signal to the light-emitting device according to the gate signal. For example, the driving circuit may include a switching thin-film transistor and a driving thin-film transistor.

[0006] Driving a thin-film transistor (TFT) generates a drive current corresponding to a data signal. The drive current applied to the light-emitting device can be affected by external light incident on the semiconductor pattern of the TFT. For example, a light-blocking pattern can be provided in each pixel area to block external light from propagating toward the semiconductor pattern of the TFT.

[0007] A specific voltage can be applied to the light-blocking pattern. However, in display devices, additional masks can be used to form contact holes that connect the light-blocking pattern to one of the signal wirings. Therefore, in display devices, process efficiency can be degraded. Summary of the Invention

[0008] Therefore, the present invention aims to provide a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0009] One object of the present invention is to provide a display device that can effectively prevent changes in the characteristics of the driving thin-film transistors due to external light without degrading process efficiency.

[0010] Another object of the present invention is to provide a display device that can connect the light-blocking pattern of each pixel area to one of the signal wirings without using an additional mask.

[0011] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows, some of which will become apparent to those skilled in the art upon review of the following description or will be apparent by practice of the invention. These objects and other advantages of the invention can be realized and obtained through the structures specifically pointed out in the specification, claims, and drawings.

[0012] To achieve these objectives and other advantages, according to the intent of the present invention, as embodied and broadly described herein, a display device is provided, comprising: a light-blocking pattern on a pixel region of a device substrate; an upper buffer layer on the light-blocking pattern, the upper buffer layer extending over a curved region of the device substrate; a switching thin-film transistor on the upper buffer layer in the pixel region, the switching thin-film transistor including a first semiconductor pattern separated from the light-blocking pattern; a separating insulating layer on the first semiconductor pattern, the separating insulating layer extending over the upper buffer layer in the curved region; and a driving thin-film transistor on the separating insulating layer in the pixel region, the driving thin-film transistor including a first semiconductor pattern separated from the light-blocking pattern. A second semiconductor pattern partially overlapping the pattern; a bent opening in a bent region of the device substrate, the bent opening including a first bent hole exposing a portion of the upper buffer layer and a second bent hole exposing a portion of the device substrate in the first bent hole; and an intermediate electrode on a separating insulating layer of the pixel region, the intermediate electrode being connected to the light-blocking pattern via an intermediate contact hole, wherein the intermediate contact hole includes a first intermediate hole partially exposing the upper buffer layer of the pixel region and a second intermediate hole partially exposing a portion of the light-blocking pattern overlapping with the first intermediate hole, wherein the vertical depth of the first intermediate hole is the same as the vertical depth of the first bent hole.

[0013] The first semiconductor pattern may comprise silicon. The second semiconductor pattern may comprise an oxide semiconductor.

[0014] The vertical depth of the second intermediate hole can be less than the vertical depth of the second curved hole.

[0015] The bending region of the device substrate may include a substrate recessed region that overlaps with the second bending hole.

[0016] The bottom surface of the first intermediate hole can be positioned closer to the device substrate than the upper surface of the upper buffer layer. The upper buffer layer of the bending region may include an upper recessed region overlapping the first bending hole.

[0017] The vertical depth of the upper recessed area can be equal to the distance between the bottom surface of the first intermediate hole and the upper surface of the upper buffer layer.

[0018] The source of the switching thin-film transistor can be connected to the source region of the first semiconductor pattern via a source contact hole. The drain of the switching thin-film transistor can be connected to the drain region of the first semiconductor pattern via a drain contact hole. The source contact hole and the drain contact hole can penetrate the first semiconductor pattern.

[0019] The vertical depth of the source contact hole can be equal to the vertical depth of the first intermediate hole. The vertical depth of the drain contact hole can be equal to the vertical depth of the source contact hole.

[0020] A lower buffer layer may be disposed between the device substrate and the upper buffer layer. The lower buffer layer may extend between the device substrate and the light-blocking pattern.

[0021] The light-blocking pattern may include a blocking recessed area that overlaps with the second intermediate hole.

[0022] In another embodiment, a display device is provided, comprising: a device substrate including a pixel region and a curved region; a buffer insulating layer on the device substrate, the buffer insulating layer including a stacked structure of a lower buffer layer and an upper buffer layer; a light-blocking pattern between the lower buffer layer and the upper buffer layer in the pixel region; a first switching thin-film transistor on the upper buffer layer in the pixel region, the first switching thin-film transistor including a first semiconductor pattern disposed outside the light-blocking pattern; a separating insulating layer covering the first semiconductor pattern, the separating insulating layer extending on the upper buffer layer in the curved region; a driving thin-film transistor on the separating insulating layer in the pixel region, the driving thin-film transistor including a second semiconductor pattern overlapping a portion of the light-blocking pattern; a curved opening disposed on the curved region of the device substrate, the curved opening including a first curved hole exposing a portion of the lower buffer layer and a second curved hole exposing a portion of the device substrate in the first curved hole; and an intermediate electrode on the separating insulating layer in the pixel region, the intermediate electrode being connected to the light-blocking pattern via an intermediate contact hole, wherein the vertical depth of the first curved hole is greater than or equal to the vertical depth of the intermediate contact hole.

[0023] A second switching thin-film transistor may be disposed on the insulating layer separating the pixel region. The second switching thin-film transistor may include a third semiconductor pattern made of the same material as the second semiconductor pattern. The third semiconductor pattern may be separated from the intermediate electrode and the second semiconductor pattern.

[0024] The lower buffer layer of the curved area may include a recessed area overlapping the first curved hole.

[0025] The source of the first switching thin-film transistor can be connected to the source region of the first semiconductor pattern via a source contact hole. The drain of the first switching thin-film transistor can be connected to the drain region of the first semiconductor pattern via a drain contact hole. The bottom surface of the source contact hole and the bottom surface of the drain contact hole can be configured to be closer to the device substrate than the top surface of the lower buffer layer.

[0026] An upper electrode of a capacitor may be disposed between the light-blocking pattern and the second semiconductor pattern.

[0027] The upper electrode of the capacitor may include a material different from the gate of the first switching thin-film transistor.

[0028] A substrate hole may be provided in the hole region of the device substrate. A separation region may be provided between the pixel region and the hole region. A partition may be provided in the separation region. The partition may include at least one undercut portion. The vertical distance of the partition may be greater than the vertical depth of the curved opening. Attached Figure Description

[0029] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0030] Figure 1 This is a schematic view illustrating a display device according to an embodiment of the present invention;

[0031] Figure 2 It is along Figure 1 The view intercepted by lines I-I' and II-II';

[0032] Figure 3A yes Figure 2 A magnified view of region P1;

[0033] Figure 3B yes Figure 2 A magnified view of region P2;

[0034] Figure 3C yes Figure 2 A magnified view of the P3 region;

[0035] Figures 4 to 18 These are views showing sequentially a method for forming a display device according to an embodiment of the present invention;

[0036] Figures 19 to 23 27, 29 and 30 are views illustrating a display device according to another embodiment of the present invention;

[0037] Figure 24 yes Figure 23 A magnified view of region P4;

[0038] Figure 25 and 26 This is a view showing a method for forming a display device according to another embodiment of the present invention;

[0039] Figure 28A yes Figure 27 A magnified view of area P5;

[0040] Figure 28B yes Figure 27 A magnified view of region P6;

[0041] Figure 28C yes Figure 27 A magnified view of region P7. Detailed Implementation

[0042] The details of the embodiments of the present invention regarding the above-mentioned objectives, technical construction, and operational effects will be clearly understood from the following detailed description given with reference to the accompanying drawings, which illustrate some embodiments of the present invention. Embodiments of the present invention are provided herein to satisfactorily convey the technical spirit of the invention to those skilled in the art; therefore, the present invention can be implemented in other forms and is not limited to the embodiments described below.

[0043] Furthermore, the same reference numerals may refer to the same or very similar elements throughout the specification, and in the accompanying drawings, for convenience, the lengths and thicknesses of layers and regions may be enlarged. It will be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element in contact with the second element, a third element may also be inserted between the first and second elements.

[0044] Here, terms such as "first" and "second" may be used to distinguish one element from other elements. However, without departing from the spirit of the invention, those skilled in the art may name the first and second elements arbitrarily for convenience.

[0045] The terminology used in this specification is for describing specific embodiments only and is not intended to limit the scope of the invention. Furthermore, it will be further understood in this specification that the terms "comprising" and "including" indicate the presence of the described features, integers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with that in the relevant technical context and shall not be interpreted in an idealized or overly formalistic manner unless expressly so defined herein.

[0047] (Implementation Method)

[0048] Figure 1 This is a schematic view illustrating a display device according to an embodiment of the present invention. Figure 2 It is along Figure 1 The view captured by lines I-I' and II-II'. Figure 3A yes Figure 2 A magnified view of region P1. Figure 3B yes Figure 2 A magnified view of region P2. Figure 3C yes Figure 2 A magnified view of region P3.

[0049] Reference Figure 1 , 2 According to embodiments 3A to 3C, a display device according to an embodiment of the present invention may include a device substrate 100. The device substrate 100 may comprise a flexible material. The device substrate 100 may have a multilayer structure. For example, the device substrate 100 may have a stacked structure of a first substrate layer 101, a substrate insulating layer 102, and a second substrate layer 103. The second substrate layer 103 may comprise the same material as the first substrate layer 101. For example, the first substrate layer 101 and the second substrate layer 103 may comprise a polymer material, such as polyimide (PI). The substrate insulating layer 102 may comprise an insulating material. For example, the substrate insulating layer 102 may comprise an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). Therefore, in a display device according to an embodiment of the present invention, damage to the device substrate 100 due to bending stress can be prevented.

[0050] The device substrate 100 may include a display area AA and a non-display area NA. The display area AA generates an image to be provided to a user. For example, multiple pixel areas PA may be disposed in the display area AA. The non-display area NA may provide various signals for generating an image to each pixel area PA of the display area AA. For example, the display device according to an embodiment of the present invention may be a GIP (gate in panel) type display device, wherein at least one gate driver GIP1 and GIP2 are mounted in the non-display area NA of the device substrate 100. The gate drivers GIP1 and GIP2 may sequentially apply gate signals to each pixel area PA of the display area AA via gate lines GL.

[0051] A pad portion PAD electrically connected to a data driver can be disposed in the non-display area NA of the device substrate 100. Data signals can be applied to each pixel area PA of the display area AA via the pad portion PAD. For example, each pixel area PA of the display area AA can be connected to the pad portion PAD via one of the data lines and one of the data link lines DLL. The data link line DLL can be disposed between the display area AA and the pad portion PAD, and the data line electrically connected to the data link line DLL can be disposed in the display area AA. A clock signal, a reset clock signal, and a start signal can be applied to gate drivers GIP1 and GIP2 via the pad portion PAD. For example, gate drivers GIP1 and GIP2 can be connected to the pad portion PAD via a gate link line (GLL).

[0052] The device substrate 100 can be partially bent. For example, a bending region BA can be provided in the non-display area NA of the device substrate 100. The bending region BA can be provided between the display area AA and the pad portion PAD. For example, in the display device according to an embodiment of the present invention, the bending region BA of the device substrate 100 can be bent, and the pad portion PAD can be provided on the lower surface of the device substrate 100.

[0053] A driving circuit may be disposed on each pixel region PA of the device substrate 100. The driving circuit may be electrically connected to one of the gate lines GL and one of the data lines. The driving circuit may generate a driving current corresponding to the data signal according to the gate signal. For example, the driving circuit may include a switching thin-film transistor 200 and a driving thin-film transistor 300.

[0054] The switching thin-film transistor 200 may include a first semiconductor pattern 210, a first gate insulating layer 220, a first gate 230, a first source 240, and a first drain 250.

[0055] The first semiconductor pattern 210 may be positioned close to the device substrate 100. The first semiconductor pattern 210 may comprise a semiconductor material. For example, the first semiconductor pattern 210 may comprise low-temperature polycrystalline silicon (LTPS). The first semiconductor pattern 210 may include a first source region, a first channel region, and a first drain region. The first channel region may be disposed between the first source region and the first drain region. The first source region and the first drain region may have a lower resistance than the first channel region. For example, the first source region and the first drain region may contain conductive impurities.

[0056] A first gate insulating layer 220 may be disposed on the first semiconductor pattern 210. The first gate insulating layer 220 may extend beyond the first semiconductor pattern 210. For example, one side of the first semiconductor pattern 210 may be covered by the first gate insulating layer 220. The first gate insulating layer 220 may comprise an insulating material. For example, the first gate insulating layer 220 may comprise an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN).

[0057] A first gate 230 may be disposed on a first gate insulating layer 220. For example, the first gate 230 may overlap with a first channel region of a first semiconductor pattern 210. The first gate 230 may comprise a conductive material. For example, the first gate 230 may comprise a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The first gate 230 may be insulated from the first semiconductor pattern 210 through the first gate insulating layer 220. For example, the first channel region of the first semiconductor pattern 210 may have a conductivity corresponding to the voltage applied to the first gate 230.

[0058] A first source electrode 240 may be disposed on a first gate insulating layer 220. The first source electrode 240 may contain a conductive material. For example, the first source electrode 240 may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The first source electrode 240 may be insulated from the first gate electrode 230. The first source electrode 240 may be disposed on a different layer than the first gate electrode 230. For example, a first interlayer insulating layer 120 may be disposed on the first gate electrode 230, and the first source electrode 240 may be disposed on the first interlayer insulating layer 120. The first interlayer insulating layer 120 may contain an insulating material. For example, the first interlayer insulating layer 120 may contain inorganic insulating materials such as silicon oxide (SiO) and silicon nitride (SiN). The first interlayer insulating layer 120 may extend beyond the first gate electrode 230. For example, one side of the first gate electrode 230 may be covered by the first interlayer insulating layer 120. The first source electrode 240 may contain a different material than the first gate electrode 230.

[0059] The first source 240 may be electrically connected to the first source region of the first semiconductor pattern 210. For example, the first gate insulating layer 220 and the first interlayer insulating layer 120 may include a first source contact hole SC1 that partially exposes the first source region of the first semiconductor pattern 210. The first source 240 may be in direct contact with the first source region of the first semiconductor pattern 210 via the first source contact hole SC1. The first source contact hole SC1 may completely penetrate the first semiconductor pattern 210. For example, the bottom surface Sb of the first source contact hole SC1 facing the device substrate 100 may be configured to be closer to the device substrate 100 than the bottom surface of the first semiconductor pattern 210 facing the device substrate 100. The first source region of the first semiconductor pattern 210 may be in contact with one side of the first source 240.

[0060] The first drain 250 may be disposed on the first gate insulating layer 220. The first drain 250 may contain a conductive material. For example, the first drain 250 may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The first drain 250 may be insulated from the first gate 230. The first drain 250 may be disposed on a different layer than the first gate 230. For example, the first drain 250 may be disposed on the first interlayer insulating layer 120. The first drain 250 may be disposed on the same layer as the first source 240. For example, the first drain 250 may contain the same material as the first source 240. The first drain 250 may contain a different material than the first gate 230.

[0061] The first drain 250 may be electrically connected to the first drain region of the first semiconductor pattern 210. For example, the first gate insulating layer 220 and the first interlayer insulating layer 120 may include a first drain contact hole that partially exposes the first drain region of the first semiconductor pattern 210. The first drain 250 may be in direct contact with the first drain region of the first semiconductor pattern 210 via the first drain contact hole. The vertical depth of the first drain contact hole may be equal to the vertical depth h1 of the first source contact hole SC1. For example, the first drain contact hole may completely penetrate the first semiconductor pattern 210. For example, the bottom surface of the first drain contact hole facing the device substrate 100 may be configured to be closer to the device substrate 100 than the lower surface of the first semiconductor pattern 210. The first drain region of the first semiconductor pattern 210 may be in contact with one side of the first drain 250.

[0062] The driving thin-film transistor 300 may have the same structure as the switching thin-film transistor 200. For example, the driving thin-film transistor 300 may include a second semiconductor pattern 310, a second gate insulating layer 320, a second gate 330, a second source 340, and a second drain 350.

[0063] The second semiconductor pattern 310 may comprise a semiconductor material. The second semiconductor pattern 310 may comprise a material different from the first semiconductor pattern 210. For example, the second semiconductor pattern 310 may comprise an oxide semiconductor such as IGZO. The second semiconductor pattern 310 may be disposed on a layer different from the first semiconductor pattern 210. For example, a separating insulating layer 130 may be disposed on the first interlayer insulating layer 120, and the second semiconductor pattern 310 may be disposed on the separating insulating layer 130. The separating insulating layer 130 may comprise an insulating material. For example, the separating insulating layer 130 may comprise an inorganic insulating material such as silicon oxide (SiO). The separating insulating layer 130 may be thicker than the first interlayer insulating layer 120. Therefore, in the display device according to an embodiment of the present invention, damage to the first semiconductor pattern 210 due to the process of forming the second semiconductor pattern 310 can be prevented.

[0064] The second semiconductor pattern 310 may have the same structure as the first semiconductor pattern 210. For example, the second semiconductor pattern 310 may include a second source region, a second channel region, and a second drain region. The second channel region may be disposed between the second source region and the second drain region. The second source region and the second drain region may have a lower resistance than the second channel region. For example, the second source region and the second drain region may include conductive regions of an oxide semiconductor.

[0065] A second gate insulating layer 320 may be disposed on the second semiconductor pattern 310. The second gate insulating layer 320 may partially cover the second semiconductor pattern 310. For example, the second gate insulating layer 320 may be disposed on the second channel region of the second semiconductor pattern 310. The second source region and the second drain region of the second semiconductor pattern 310 may be disposed outside the second gate insulating layer 320. The second gate insulating layer 320 may contain an insulating material. For example, the second gate insulating layer 320 may contain an inorganic insulating material such as silicon oxide (SiO).

[0066] The second gate 330 may be disposed on the second gate insulating layer 320. For example, the second gate 330 may overlap with the second channel region of the second semiconductor pattern 310. The second gate 330 may contain a conductive material. For example, the second gate 330 may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The second gate 330 may be insulated from the second semiconductor pattern 310 through the second gate insulating layer 320. For example, the second channel region of the second semiconductor pattern 310 may have a conductivity corresponding to the voltage applied to the second gate 330.

[0067] The second source 340 may contain a conductive material. For example, the second source 340 may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The second source 340 may contain a different material than the second gate 330. The second source 340 may be disposed on a different layer than the second gate 330. For example, a second interlayer insulating layer 140 may be disposed on the second gate 330, and the second source 340 may be disposed on the second interlayer insulating layer 140. The second interlayer insulating layer 140 may contain an insulating material. For example, the second interlayer insulating layer 140 may contain inorganic insulating materials such as silicon oxide (SiO) and silicon nitride (SiN). The second interlayer insulating layer 140 may extend beyond the second semiconductor pattern 310 and the second gate 330. For example, one side of the second semiconductor pattern 310 and one side of the second gate 330 may be covered by the second interlayer insulating layer 140. The second source 340 may be insulated from the second gate 330.

[0068] The second source 340 may contain the same material as the first source 240 and the first drain 250. The first source 240 and the first drain 250 may be disposed on the same layer as the second source 340. For example, the first source 240 and the first drain 250 may be disposed on the second interlayer insulating layer 140. The first source contact hole SC1 and the first drain contact hole may penetrate the separating insulating layer 130 and the second interlayer insulating layer 140.

[0069] The second source 340 may be electrically connected to the second source region of the second semiconductor pattern 310. For example, the second interlayer insulating layer 140 may include a second source contact hole that partially exposes the second source region of the second semiconductor pattern 310. The second source 340 may be in direct contact with the second source region of the second semiconductor pattern 310 via the second source contact hole. The vertical depth of the second source contact hole may be the same as the thickness of the second interlayer insulating layer 140. For example, the second source region of the second semiconductor pattern 310 may be in contact with the bottom surface of the second source 340.

[0070] The second drain 350 may comprise a conductive material. For example, the second drain 350 may comprise a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The second drain 350 may be insulated from the second gate 330. For example, the second drain 350 may be disposed on a different layer than the second gate 330. The second drain 350 may be disposed on the same layer as the second source 340. For example, the second drain 350 may be disposed on the second interlayer insulating layer 140. The second drain 350 may comprise a different material than the second gate 330. For example, the second drain 350 may comprise the same material as the second source 340.

[0071] The second drain 350 may be electrically connected to the second drain region of the second semiconductor pattern 310. For example, the second interlayer insulating layer 140 may include a second drain contact hole that partially exposes the second drain region of the second semiconductor pattern 310. The second drain 350 may be in direct contact with the second drain region of the second semiconductor pattern 310 through the second drain contact hole. The vertical depth of the second drain contact hole may be the same as the vertical depth of the second source contact hole. For example, the vertical depth of the second drain contact hole may be equal to the thickness of the second interlayer insulating layer 140. The second drain region of the second semiconductor pattern 310 may be in contact with the bottom surface of the second drain 350.

[0072] Each driving circuit's switching thin-film transistor 200 can transmit a data signal to the corresponding driving thin-film transistor 300 according to a gate signal. For example, in each pixel region PA, the first gate 230 of the switching thin-film transistor 200 can be electrically connected to one of the gate lines GL, and the first source 240 of the switching thin-film transistor 200 can be electrically connected to one of the data lines. The gate line GL and the data line can be formed by a process of forming the switching thin-film transistor 200 in each pixel region PA. For example, the gate line GL can be formed on the same layer as the first gate 230 of each driving circuit, and the data line can be formed on the same layer as the first source 240 and the first drain 250 of each driving circuit. The gate line GL can be disposed between the first interlayer insulating layer 120 and the first gate insulating layer 220 of each pixel region PA. For example, the gate line GL can contain the same material as the first gate 230 of each driving circuit. The data line can be disposed on the second interlayer insulating layer 140. For example, the data line can contain the same material as the first source 240 and the first drain 250.

[0073] Each driving thin-film transistor 300 of the driving circuit can generate a driving current corresponding to the data signal. For example, in each pixel region PA, the second gate 330 of the driving thin-film transistor 300 can be electrically connected to the first drain 250 of the switching thin-film transistor 200, and the second source 340 of the driving thin-film transistor 300 can be electrically connected to one of the power supply voltage supply lines. The power supply voltage supply lines can be formed by a process of forming the driving thin-film transistor 300 in each pixel region PA. For example, the power supply voltage supply lines can be disposed on the same layer as the second source 340 and the second drain 350 of each driving circuit. The power supply voltage supply lines can be disposed on the second interlayer insulating layer 140. For example, the power supply voltage supply lines can be disposed on the same layer as the data lines. The power supply voltage supply lines can be separated from the data lines. The power supply voltage supply lines can contain the same material as the second source 340 and the second drain 350 of each driving circuit. For example, the power supply voltage supply lines can contain the same material as the data lines.

[0074] A buffer insulating layer 110 may be disposed between the driving circuitry of each pixel region PA and the device substrate 100. The buffer insulating layer 110 prevents contamination caused by the device substrate 100 during the process of forming the switching thin-film transistors 200 and driving thin-film transistors 300 of each driving circuit. For example, the buffer insulating layer 110 may extend along the upper surface of the device substrate 100 toward the switching thin-film transistors 200 and driving thin-film transistors 300 of each driving circuit. The buffer insulating layer 110 may comprise an insulating material. For example, the buffer insulating layer 110 may comprise an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The buffer insulating layer 110 may have a multilayer structure. For example, the buffer insulating layer 110 may have a stacked structure of a lower buffer layer 111 and an upper buffer layer 112. The lower buffer layer 111 may be disposed between the device substrate 100 and the upper buffer layer 112. For example, the lower surface of the first semiconductor pattern 210 may be in direct contact with the upper buffer layer 112 in each pixel region PA. The upper buffer layer 112 may contain a different material than the lower buffer layer 111. The separating insulating layer 130 may extend over the upper buffer layer 112 in the bending region BA.

[0075] A light-blocking pattern 410 may be disposed in each pixel region PA. The light-blocking pattern 410 may contain a material capable of blocking light. The light-blocking pattern 410 may contain a conductive material. For example, the light-blocking pattern 410 may contain metals such as aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The light-blocking pattern 410 may be disposed between the second semiconductor pattern 310 of the driving thin-film transistor 300 and the device substrate 100. For example, a portion of the second semiconductor pattern 310 of the driving thin-film transistor 300 may overlap with the light-blocking pattern 410. Therefore, in the display device according to an embodiment of the present invention, external light propagating in the direction toward the second semiconductor pattern 310 of the driving thin-film transistor 300 can be blocked by the light-blocking pattern 410. Thus, in the display device according to an embodiment of the present invention, characteristic changes of the driving thin-film transistor 300 due to external light can be prevented.

[0076] The light-blocking pattern 410 can be positioned close to the device substrate 100. The first gate 230 of the switching thin-film transistor 200 can be insulated from the light-blocking pattern 410. The light-blocking pattern 410 can be disposed on a different layer from the first gate 230 of the switching thin-film transistor 200. For example, the light-blocking pattern 410 can be disposed between the device substrate 100 and the buffer insulating layer 110. The light-blocking pattern 410 can be in direct contact with the upper surface of the device substrate 100. The light-blocking pattern 410 can contain a different material than the first gate 230. Therefore, in the display device according to the embodiment of the present invention, the material of the light-blocking pattern 410 can be selected without considering the operating characteristics of the switching thin-film transistor 200. That is, in the display device according to the embodiment of the present invention, the function of the light-blocking pattern 410 can be maximized without causing degradation of the characteristics of the switching thin-film transistor 200. Therefore, in the display device according to the embodiment of the present invention, characteristic changes of the switching thin-film transistor 200 due to external light can be effectively prevented.

[0077] The light-blocking pattern 410 of each pixel region PA can be separated from the light-blocking patterns 410 of adjacent pixel regions PA. For example, the light-blocking pattern 410 of each pixel region PA can have an island shape. The light-blocking pattern 410 of each pixel region PA can be separated from the light-blocking patterns 410 of adjacent pixel regions PA. Thus, in the display device according to the embodiment of the present invention, signal delay caused by parasitic capacitance between the light-blocking pattern 410 and the gate line GL and / or data line can be prevented.

[0078] An intermediate electrode 600 electrically connected to the light-blocking pattern 410 can be disposed in each pixel area PA. The intermediate electrode 600 may contain a conductive material. For example, the intermediate electrode 600 may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The intermediate electrode 600 may be connected to signal wiring such as gate line GL, data line DL (see... Figure 29 One of the two is the intermediate electrode 600 and the power supply voltage line. For example, the intermediate electrode 600 may be electrically connected to the power supply voltage line, and the power supply voltage may be applied to the light-blocking pattern 410 through the intermediate electrode 600. Thus, in the display device according to an embodiment of the present invention, the light-blocking pattern 410 can effectively block external light.

[0079] The intermediate electrode 600 can be disposed on the same layer as the corresponding signal wiring. For example, the intermediate electrode 600 can be disposed on the second interlayer insulating layer 140. The intermediate electrode 600 can be disposed on the same layer as the first source 240, the first drain 250, the second source 340, and the second drain 350. For example, the intermediate electrode 600 can contain the same material as the first source 240, the first drain 250, the second source 340, and the second drain 350. The intermediate electrode 600 can be formed simultaneously with the first source 240, the first drain 250, the second source 340, and the second drain 350. Thus, in the display device according to an embodiment of the present invention, the process for forming the intermediate electrode 600 can be simplified.

[0080] The intermediate electrode 600 can be electrically connected to the light-blocking pattern 410 through an intermediate contact hole BC. For example, the intermediate contact hole BC can penetrate the buffer insulating layer 110, the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140. The vertical depth of the intermediate contact hole can be greater than the vertical depth h1 of the first source contact hole SC1. For example, the intermediate contact hole BC can include a first intermediate hole BC1 and a second intermediate hole BC2 disposed in the first intermediate hole BC1.

[0081] The first intermediate hole BC1 may partially expose the upper buffer layer 112. For example, the first intermediate hole BC1 may penetrate the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140. The vertical depth h2 of the first intermediate hole BC1 may be equal to the vertical depth h1 of the first source contact hole SC1. For example, the bottom surface Cb of the first intermediate hole BC1 facing the device substrate 100 on the light-blocking pattern 410 may be set closer to the device substrate 100 than the upper surface of the upper buffer layer 112 facing the device substrate 100. The first intermediate hole BC1 may be formed simultaneously with the first source contact hole SC1. For example, the first distance d1 between the bottom surface Sb of the first source contact hole SC1 and the lower surface of the first semiconductor pattern 210 may be equal to the second distance d2 between the bottom surface Cb of the first intermediate hole BC1 and the upper surface of the upper buffer layer 112 on the light-blocking pattern 410.

[0082] The second intermediate aperture BC2 can partially expose a portion of the light-blocking pattern 410 that overlaps with the first intermediate aperture BC1. For example, the second intermediate aperture BC2 can penetrate a portion of the upper buffer layer 112 and the lower buffer layer 111. The vertical depth h3 of the second intermediate aperture BC2 can be less than the vertical depth h2 of the first intermediate aperture BC1.

[0083] The upper electrode 420 of the capacitor may be disposed between the second semiconductor pattern 310 and the light-blocking pattern 410 in each pixel region PA. The upper electrode 420 of the capacitor may overlap with a portion of the light-blocking pattern 410. For example, the light-blocking pattern 410 and the upper electrode 420 of the capacitor may constitute the storage capacitor 400 of the driving circuit. That is, in the display device according to the embodiment of the present invention, the light-blocking pattern 410 may be used as the lower electrode of the storage capacitor 400. Thus, in the display device according to the embodiment of the present invention, process efficiency can be improved.

[0084] The upper electrode 420 of the capacitor may comprise a conductive material. For example, the upper electrode 420 may comprise a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The upper electrode 420 may be disposed on a different layer from the first gate 230 of the switching thin-film transistor 200. For example, the upper electrode 420 may be disposed between the first interlayer insulating layer 120 and the separating insulating layer 130. The upper electrode 420 may comprise a different material than the first gate 230. Thus, in the display device according to an embodiment of the present invention, the storage capacitor 400 can be configured without considering the operating characteristics of the switching thin-film transistor 200. Therefore, in the display device according to an embodiment of the present invention, the operating characteristics of each driving circuit can be improved.

[0085] The first planarization layer 150 and the second planarization layer 160 may be stacked sequentially on the driving circuit of each pixel region PA. For example, the first planarization layer 150 may be disposed between the second interlayer insulating layer 140 and the second planarization layer 160. The first source 240, the first drain 250, the second source 340, the second drain 350, and the intermediate electrode 600 of each pixel region PA may be covered by the first planarization layer 150. The first planarization layer 150 and the second planarization layer 160 may eliminate thickness differences caused by the driving circuit of each pixel region PA. For example, the upper surface of the second planarization layer 160 opposite to the device substrate 100 may be a flat surface. The first planarization layer 150 and the second planarization layer 160 may contain an insulating material. The first planarization layer 150 and the second planarization layer 160 may contain a material different from the second interlayer insulating layer 140. For example, the first planarization layer 150 and the second planarization layer 160 may contain an organic insulating material. The second planarization layer 160 may contain a material different from the first planarization layer 150.

[0086] The light-emitting device 500 may be disposed on the second planarization layer 160 of each pixel region PA. The light-emitting device 500 may emit light displaying a specific color. For example, the light-emitting device 500 may include a first electrode 510, a light-emitting layer 520 and a second electrode 530 stacked in sequence.

[0087] The first electrode 510 may comprise a conductive material. The first electrode 510 may comprise a material with high reflectivity. For example, the first electrode 510 may comprise metals such as aluminum (Al) and silver (Ag). The first electrode 510 may have a multilayer structure. For example, the first electrode 510 may have a structure in which a reflective electrode made of metal is inserted between transparent electrodes made of transparent conductive materials such as ITO and IZO.

[0088] The light-emitting layer 520 can generate light with a brightness corresponding to the voltage difference between the first electrode 510 and the second electrode 530. For example, the light-emitting layer 520 may include a light-emitting material layer (EML) having a light-emitting material. The light-emitting material may include organic materials, inorganic materials, or mixed materials. For example, the display device according to an embodiment of the present invention may be an organic light-emitting display device comprising an organic light-emitting material. The light-emitting layer 520 may have a multilayer structure. For example, the light-emitting layer 520 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Thus, in the display device according to an embodiment of the present invention, the luminous efficiency of the light-emitting layer 520 in each pixel region PA can be improved.

[0089] The second electrode 530 may comprise a conductive material. The second electrode 530 may comprise a material different from the first electrode 510. The second electrode 530 may be a transparent electrode having a higher transmittance than the first electrode 510. Thus, in the display device according to an embodiment of the present invention, light generated by the light-emitting layer 520 of each pixel region PA can be emitted to the outside via the second electrode 530 of the corresponding pixel region PA.

[0090] The light-emitting device 500 of each pixel region PA can be electrically connected to the driving circuit of the corresponding pixel region PA. For example, the first planarization layer 150 and the second planarization layer 160 may include electrode contact holes that partially expose the second drain 350 of each pixel region PA. The first electrode 510 of each pixel region PA can be electrically connected to the second drain 350 of the driving thin-film transistor 300 in the corresponding pixel region PA through one of the electrode contact holes. Thus, in the display device according to an embodiment of the present invention, the driving current generated by the driving circuit of each pixel region PA can be applied to the light-emitting device 500 of the corresponding pixel region PA.

[0091] In each pixel region PA, a first connection electrode 710 connecting the second drain 350 of the driving thin-film transistor 300 and the first electrode 510 of the light-emitting device 500 can be disposed between the first planarization layer 150 and the second planarization layer 160 of the corresponding pixel region PA. For example, the first connection electrode 710 of each pixel region PA can be connected to the second drain 350 of the corresponding pixel region PA by penetrating the first planarization layer 150, and the first electrode 510 of each pixel region PA can be connected to the first connection electrode 710 of the corresponding pixel region PA by penetrating the second planarization layer 160. Thus, in the display device according to an embodiment of the present invention, the light-emitting device 500 of each pixel region PA can be stably connected to the driving thin-film transistor 300 of the corresponding pixel region PA. The first connection electrode 710 may contain a conductive material. For example, the first connection electrode 710 may contain a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0092] A second connection electrode 720 connected to the intermediate electrode 600 of each pixel region PA can be disposed between the first planarization layer 150 and the second planarization layer 160 of the corresponding pixel region PA. The second connection electrode 720 may contain a conductive material. For example, the second connection metal may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The second connection electrode 720 may contain the same material as the first connection electrode 710. For example, the second connection electrode 720 may be formed simultaneously with the first connection electrode 710. The intermediate electrode 600 of each pixel region PA can be connected to one of the signal wirings through the second connection electrode 720 of the corresponding pixel region PA. Thus, in the display device according to an embodiment of the present invention, the intermediate electrode 600 in each pixel region PA can be connected to one of the signal wirings by bypassing the connection line connected between the switching thin-film transistor 200, the driving thin-film transistor 300, and the storage capacitor 400. Therefore, in the display device according to an embodiment of the present invention, the configuration freedom of the driving circuit in each pixel region PA can be improved.

[0093] The first electrode 510 of each pixel region PA can be separated from the first electrode 510 of adjacent pixel regions PA. For example, a bank insulating layer 170 can be provided on the second planarization layer 160 between adjacent first electrodes 510. The bank insulating layer 170 can contain an insulating material. For example, the bank insulating layer 170 can contain an organic insulating material. The bank insulating layer 170 can contain a material different from the second planarization layer 160. The first electrode 510 of each pixel region PA can be insulated from the first electrode 510 of adjacent pixel regions PA through the bank insulating layer 170. For example, the bank insulating layer 170 can cover the edge of each first electrode 510. The light-emitting layer 520 and the second electrode 530 of each pixel region PA can be stacked sequentially on the portion of the corresponding first electrode 510 exposed by the bank insulating layer 170. The bank insulating layer 170 can be in direct contact with the second planarization layer 160 between adjacent first electrodes 510. Thus, in the display device according to an embodiment of the present invention, the light-emitting device 500 of each pixel region PA can be independently controlled.

[0094] Each pixel region PA's light-emitting device 500 can emit light of a different color than that of the light-emitting devices 500 in adjacent pixel regions PA. For example, the light-emitting layer 520 of each pixel region PA can be separated from the light-emitting layers 520 of adjacent pixel regions PA. The light-emitting layer 520 of each pixel region PA may include an end located on the dam insulating layer 170 of the corresponding pixel region PA. The light-emitting layer 520 of each pixel region PA can be formed by a different process than that of the light-emitting layers 520 of adjacent pixel regions PA. For example, the light-emitting layer 520 of each pixel region PA can be formed using a fine metal mask (FMM). A spacer 180 can be disposed on the dam insulating layer 170. The spacer 180 may contain an insulating material. The fine metal mask used in the process of forming the light-emitting layer 520 of each pixel region PA can be supported by the spacer 180. For example, the light-emitting layer 520 of each pixel region PA can be separated from the spacer 180. Therefore, in the display device according to the embodiment of the present invention, damage to the light-emitting layer 520 and the insulating layer 170 of adjacent pixel areas PA can be prevented during the process of forming the light-emitting layer 520 in each pixel area PA.

[0095] The voltage applied to the second electrode 530 of each pixel region PA can be the same as the voltage applied to the second electrode 530 of the adjacent pixel region PA. For example, the second electrode 530 of each pixel region PA can be electrically connected to the second electrode 530 of the adjacent pixel region PA. The second electrode 530 of each pixel region PA can contain the same material as the second electrode 530 of the adjacent pixel region PA. For example, the second electrode 530 of each pixel region PA can be in direct contact with the second electrode 530 of the adjacent pixel region PA. The second electrode 530 of each pixel region PA can be formed simultaneously with the second electrode 530 of the adjacent pixel region PA. For example, the second electrode 530 of each pixel region PA can extend on the insulating layer 170 and the spacer 180. Thus, the display device according to the embodiment of the present invention can control the brightness of the light emitted from the light-emitting device 500 of each pixel region PA by means of a data signal.

[0096] like Figure 2 and 3C As shown, a buffer insulating layer 110, a first gate insulating layer 220, a first interlayer insulating layer 120, a separator insulating layer 130, a second interlayer insulating layer 140, a first planarization layer 150, and a second planarization layer 160 may be disposed on the non-display area NA of the device substrate 100. For example, the buffer insulating layer 110, the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, the second interlayer insulating layer 140, the first planarization layer 150, and the second planarization layer 160 may extend on the bent region BA of the device substrate 100. A bent open hole OP may be disposed on the bent region BA of the device substrate 100, wherein the buffer insulating layer 110, the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140 are removed. The first planarization layer 150 and the second planarization layer 160 may extend in the bent open hole OP. For example, the bent open hole OP may be filled by the first planarization layer 150. Therefore, in the display device according to an embodiment of the present invention, the bending stress caused by bending through the bending region BA of the device substrate 100 can be reduced. The bending opening OP can partially expose the bending region BA of the device substrate 100. For example, the bending opening OP may include a first bending hole OP1 and a second bending hole OP2 in the first bending hole OP1.

[0097] The first curved hole OP1 may partially expose the upper buffer layer 112 of the curved region BA. For example, the vertical depth h4 of the first curved hole OP1 may be the same as the vertical depth h2 of the first intermediate hole BC1. As an example, the vertical depth of the first curved hole OP1 may be greater than or equal to the vertical depth of the intermediate contact hole BC. The upper buffer layer 112 of the curved region BA may include an upper recessed region 112r overlapping the first curved hole OP1. The vertical depth d3 of the upper recessed region 112r may be equal to the second distance d2 between the bottom surface Cb of the first intermediate hole BC1 and the upper surface of the upper buffer layer 112. For example, the first curved hole OP1 may be formed simultaneously with the first intermediate hole BC1.

[0098] The second curved hole OP2 can partially expose a portion of the device substrate 100 overlapping with the first curved hole OP. The second curved hole OP2 can penetrate a portion of the upper buffer layer 112 and the lower buffer layer 111. The vertical depth of the second curved hole OP2 can be less than the vertical depth of the first curved hole OP1. The vertical depth h5 of the second curved hole OP2 can be different from the vertical depth h3 of the second intermediate hole BC2. For example, the vertical depth h5 of the second curved hole OP2 can be greater than the vertical depth h3 of the second intermediate hole BC2. The substrate recess region 100r overlapping with the second curved hole OP2 can be provided in the curved region BA of the device substrate 100.

[0099] The following will refer to Figure 2 , 3A Methods for forming a display device according to embodiments of the present invention are described in sections 3C, 4 to 15.

[0100] Figures 4 to 18 These are views showing, in sequence, a method for forming a display device according to an embodiment of the present invention.

[0101] First, the method for forming a display device according to an embodiment of the present invention may include the steps of preparing a device substrate 100 and forming a light-blocking pattern 410 on the pixel region PA of the device substrate 100, such as... Figure 4 As shown.

[0102] The device substrate 100 may be formed of a flexible material. The device substrate 100 may have a multilayer structure. For example, the steps of fabricating the device substrate 100 may include bonding a first substrate layer 101, a substrate insulating layer 102, and a second substrate layer 103. The second substrate layer 103 may be formed of the same material as the first substrate layer 101. For example, the first substrate layer 101 and the second substrate layer 103 may be formed of a polymer material such as polyimide (PI). The substrate insulating layer 102 may comprise an insulating material. For example, the substrate insulating layer 102 may be formed of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN).

[0103] The light-blocking pattern 410 may comprise a conductive material. For example, the light-blocking pattern 410 may be formed from a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The steps of forming the light-blocking pattern 410 may include an etching process using a mask. For example, the steps of forming the light-blocking pattern 410 may include forming a conductive material layer on the device substrate 100 and patterning the conductive material using a mask.

[0104] A method for forming a display device according to an embodiment of the present invention may include: the step of forming a buffer insulating layer 110 on a device substrate 100 in which a light-blocking pattern 410 is formed; and the step of forming a first semiconductor pattern 210 on the buffer insulating layer 110 of a pixel region PA, such as... Figure 5 As shown.

[0105] The buffer insulating layer 110 may be formed of an insulating material. For example, the buffer insulating layer 110 may be formed of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The buffer insulating layer 110 may be formed on the pixel region PA and the curved region BA located outside the pixel region PA of the device substrate 100. The buffer insulating layer 110 may have a multilayer structure. For example, the step of forming the buffer insulating layer 110 may include: forming a lower buffer layer 111 on the curved region BA and the pixel region PA of the device substrate 100 in which a light-blocking pattern 410 is formed; and forming an upper buffer layer 112 on the lower buffer layer 111 of the pixel region PA and the curved region BA. The light-blocking pattern 410 may be covered by the lower buffer layer 111. The upper buffer layer 112 may be formed of a material different from the lower buffer layer 111.

[0106] The first semiconductor pattern 210 may be formed of a semiconductor material. For example, the first semiconductor pattern 210 may be formed of low-temperature polycrystalline silicon (LTPS). The formation process of the first semiconductor pattern 210 may include a deposition process and a crystallization process. The steps of forming the first semiconductor pattern 210 may include an etching process using a mask. For example, the steps of forming the first semiconductor pattern 210 may include: forming an amorphous silicon layer on the upper buffer layer 112; forming a low-temperature polycrystalline silicon layer by crystallizing the amorphous silicon layer at a low temperature; and patterning the low-temperature polycrystalline silicon layer using a mask. The first semiconductor pattern 210 may be separated from the light-blocking pattern 410. For example, the first semiconductor pattern 210 may be formed outside the light-blocking pattern 410.

[0107] A method for forming a display device according to an embodiment of the present invention may include the steps of: forming a first gate insulating layer 220 on a device substrate 100 in which a first semiconductor pattern 210 is formed; and forming a first gate 230 on the first gate insulating layer 220 of a pixel region PA, such as... Figure 6As shown.

[0108] The first gate insulating layer 220 may be formed of an insulating material. For example, the first gate insulating layer 220 may be formed of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The first gate insulating layer 220 may be formed on the pixel region PA and the curved region BA of the device substrate 100. For example, the first gate insulating layer 220 may cover the buffer insulating layer 110 and the first semiconductor pattern 210 of the curved region BA.

[0109] The first gate 230 may comprise a conductive material. For example, the first gate 230 may be formed of a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The first gate 230 may be formed of a material different from the light-blocking pattern 410. The steps of forming the first gate 230 may include an etching process using a mask. For example, the steps of forming the first gate 230 may include: forming a conductive material layer on the first gate insulating layer 220; and patterning the conductive material layer using a mask.

[0110] A first gate 230 may be formed on a first channel region of the first semiconductor pattern 210. The first channel region of the first semiconductor pattern 210 may be disposed between a first source region and a first drain region of the first semiconductor pattern 210. The first source region and the first drain region of the first semiconductor pattern 210 may have a lower resistance than the first channel region of the first semiconductor pattern 210. For example, the first source region, the first channel region, and the first drain region of the first semiconductor pattern 210 may be formed by a doping process using conductive impurities.

[0111] The first source region, first channel region, and first drain region of the first semiconductor pattern 210 can be formed using a first gate 230. For example, the steps of forming the first source region, first drain region, and first channel region of the first semiconductor pattern 210 may include using the first gate 230 formed on the central portion of the first semiconductor pattern 210 as a conductive impurity to dope the two ends of the first semiconductor pattern 210. Therefore, the method for forming a display device according to an embodiment of the present invention can form the first source region, first channel region, and first drain region in the first semiconductor pattern 210 without requiring an additional mask for the doping process using conductive impurities. Thus, process efficiency can be improved in the method for forming a display device according to an embodiment of the present invention.

[0112] A method for forming a display device according to an embodiment of the present invention may include the steps of forming a first interlayer insulating layer 120 on a device substrate 100 in which a first gate 230 is formed; and the step of forming an upper electrode 420 of a capacitor on the first interlayer insulating layer 120 of a pixel region PA, such as... Figure 7 As shown.

[0113] The first interlayer insulating layer 120 may comprise an insulating material. For example, the first interlayer insulating layer 120 may be formed of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The first interlayer insulating layer 120 may be formed on the pixel region PA and the curved region BA of the device substrate 100. For example, the first gate insulating layer 220 and the first gate 230 of the curved region BA may be covered by the first interlayer insulating layer 120.

[0114] The upper electrode 420 of the capacitor may be formed of a conductive material. For example, the upper electrode 420 may be formed of a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The upper electrode 420 may be formed of a material different from the first gate 230. The steps of forming the upper electrode 420 may include an etching process using a mask. For example, the steps of forming the upper electrode 420 may include forming a conductive material layer on the first interlayer insulating layer 120 and patterning the conductive material layer using a mask.

[0115] The upper electrode 420 of the capacitor may be formed on the light-blocking pattern 410. For example, the upper electrode 420 of the capacitor may overlap with a portion of the light-blocking pattern 410. The light-blocking pattern 410 and the upper electrode 420 of the capacitor may constitute the storage capacitor 400. For example, the light-blocking pattern 410 may be used as the lower electrode of the storage capacitor 400.

[0116] A method for forming a display device according to an embodiment of the present invention may include: the step of forming a separating insulating layer 130 on a device substrate 100 in which an upper electrode 420 of a capacitor is formed; and the step of forming a second semiconductor pattern 310 on the separating insulating layer 130 of a pixel region PA, such as... Figure 8 As shown.

[0117] The separating insulating layer 130 may be formed of an insulating material. For example, the separating insulating layer 130 may be formed of an inorganic insulating material such as silicon oxide (SiO). The separating insulating layer 130 may be formed to be thicker than the first interlayer insulating layer 120. The separating insulating layer 130 may be formed on the curved region BA and the pixel region PA of the device substrate 100. For example, the first interlayer insulating layer 120 of the curved region BA and the upper electrode 420 of the capacitor may be covered by the separating insulating layer 130.

[0118] The second semiconductor pattern 310 may be formed of a semiconductor material. The second semiconductor pattern 310 may be formed of a material different from the first semiconductor pattern 210. For example, the second semiconductor pattern 310 may be formed of an oxide semiconductor such as IGZO. The steps of forming the second semiconductor pattern 310 may include an etching process using a mask. For example, the steps of forming the second semiconductor pattern 310 may include: forming an oxide semiconductor material layer on the separating insulating layer 130; and patterning the oxide semiconductor material layer using a mask.

[0119] The second semiconductor pattern 310 may be formed on the upper electrode 420 of the capacitor. For example, the second semiconductor pattern 310 may overlap with a portion of the light-blocking pattern 410. Thus, in the method of forming a display device according to an embodiment of the present invention, light propagating through the device substrate 100 toward the second semiconductor pattern 310 may be blocked by the light-blocking pattern 410.

[0120] A method for forming a display device according to an embodiment of the present invention may include the steps of forming a second gate insulating layer 320 on a portion of a second semiconductor pattern 310; and the step of forming a second gate 330 on the second gate insulating layer 320, such as... Figure 9 As shown.

[0121] The second gate insulating layer 320 may be formed of an insulating material. For example, the second gate insulating layer 320 may be formed of an inorganic insulating material such as silicon oxide (SiO). The second gate insulating layer 320 may expose a portion of the second semiconductor pattern 310. For example, the second source region and the second drain region of the second semiconductor pattern 310 may be disposed outside the second gate insulating layer 320. The second semiconductor pattern 310 may include a second channel region located between the second source region and the second drain region. The second source region and the second drain region of the second semiconductor pattern 310 may have a lower resistance than the second channel region of the second semiconductor pattern 310. For example, the second source region and the second drain region of the second semiconductor pattern 310 may include conductive regions of an oxide semiconductor. For example, the second channel region of the second semiconductor pattern 310 may be an unconductive region of an oxide semiconductor. The second gate insulating layer 320 may overlap with the second channel region of the second semiconductor pattern 310.

[0122] The second gate 330 may be formed to overlap with the second gate insulating layer 320. For example, the second gate 320 may overlap with the second channel region of the second semiconductor pattern 310. The second gate 330 may be formed of a conductive material. For example, the second gate 330 may be formed of a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0123] The second gate insulating layer 320 and the second gate 330 can be formed using a single mask process. For example, the steps of forming the second gate insulating layer 320 and the second gate 330 may include: forming an insulating material layer on a device substrate 100 in which the second semiconductor pattern 310 is formed; forming a conductive material layer on the insulating material layer; patterning the conductive material layer using an etching process with a mask to form the second gate 330; and patterning the insulating material layer using the second gate 330 as a mask to form the second gate insulating layer 320. One side of the second gate insulating layer 320 may be vertically aligned with one side of the second gate 330. For example, one side of the second gate 330 may be continuous with one side of the second gate insulating layer 320.

[0124] The second source region, the second channel region, and the second drain region of the second semiconductor pattern 310 can be formed by a process for forming the second gate insulating layer 320. For example, the step of forming the second source region, the second channel region, and the second drain region in the second semiconductor pattern 310 may include the step of making a portion of the second semiconductor pattern 310 exposed by the second gate insulating layer 320 conductive using an etchant used in the patterning process of the second gate insulating layer 320.

[0125] A method for forming a display device according to an embodiment of the present invention may include the steps of forming a second interlayer insulating layer 140 on a device substrate 100 in which a second gate 330 is formed; and the steps of forming a first source contact hole SC1, a first drain contact hole DC1, a first intermediate hole BC1, and a first bent hole OP1 on the device substrate 100 in which the second interlayer insulating layer 140 is formed. Figure 10 As shown.

[0126] The second interlayer insulating layer 140 may be formed of an insulating material. For example, the second interlayer insulating layer 140 may be formed of an inorganic insulating material such as silicon oxide (SiO). The second interlayer insulating layer 140 may be formed on the curved region BA and the pixel region PA of the device substrate 100. For example, the second interlayer insulating layer 140 may cover the separating insulating layer 130 of the curved region BA and the second semiconductor pattern 310, the second gate insulating layer 320 and the second gate 330 of the pixel region PA.

[0127] A first source contact SC1 and a first drain contact DC1 may be formed in the pixel region PA. The first source contact SC1 may partially expose the first source region of the first semiconductor pattern 210, and the first drain contact DC1 may partially expose the first drain region of the first semiconductor pattern 210. For example, each of the first source contact SC1 and the first drain contact DC1 may penetrate the first gate insulating layer 220, the first interlayer insulating layer 120, the separating insulating layer 130, and the second interlayer insulating layer 140 of the pixel region PA.

[0128] A first intermediate hole BC1 may be formed in the pixel region PA. The first intermediate hole BC1 may overlap with a portion of the light-blocking pattern 410. For example, the first intermediate hole BC1 may penetrate the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140 disposed on the light-blocking pattern 410. The first intermediate hole BC1 may be formed outside the upper electrode 420 of the capacitor.

[0129] A first bend hole OP1 may be formed on a bend region BA of the device substrate 100. For example, the first bend hole OP1 may penetrate the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140 of the bend region BA. The first bend hole OP1 may partially expose the upper buffer layer 112 of the bend region BA. For example, the vertical depth of the first bend hole OP1 may be greater than the sum of the thicknesses of the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140 on the bend region BA. For example, the upper portion of the upper buffer layer 112 in the bend region BA may be removed by the process of forming the first bend hole OP1. An upper recessed region 112r overlapping the first bend hole OP1 may be formed at the upper buffer layer 112 of the bend region BA.

[0130] The first source contact hole SC1, the first drain contact hole DC1, and the first intermediate hole BC1 can be formed simultaneously with the first curved hole OP1. For example, the vertical depth of the first source contact hole SC1, the vertical depth of the first drain contact hole DC1, and the vertical depth of the first intermediate hole BC1 can all be the same as the vertical depth of the first curved hole OP1. The first source contact hole SC1 and the first drain contact hole DC1 can penetrate the first semiconductor pattern 210. For example, the bottom surface of the first source contact hole SC1 and the bottom surface of the first drain contact hole DC1 can be set to be closer to the device substrate 100 than the lower surface of the first semiconductor pattern 210 (or compared to the upper surface of the lower buffer layer 111). The bottom surface of the first intermediate hole BC1 can be set to be closer to the device substrate 100 than the upper surface of the upper buffer layer 112 on the light-blocking pattern 410.

[0131] A method for forming a display device according to an embodiment of the present invention may include the steps of forming a second source contact hole SC2, a second drain contact hole DC2, a second intermediate hole BC2, and a second bent hole OP2 on a device substrate 100 in which a first source contact hole SC1, a first drain contact hole DC1, a first intermediate hole BC1, and a first bent hole OP1 are formed, such as... Figure 11 As shown.

[0132] A second source contact SC2 and a second drain contact DC2 may be formed in the pixel region PA. The second source contact SC2 may partially expose the second source region of the second semiconductor pattern 310, and the second drain contact DC2 may partially expose the second drain region of the second semiconductor pattern 310. For example, each of the second source contact SC2 and the second drain contact DC2 may penetrate the second interlayer insulating layer 140 of the pixel region PA.

[0133] A second intermediate hole BC2 may be formed within a first intermediate hole BC1. For example, the first intermediate hole BC1 and the second intermediate hole BC2 may constitute an intermediate contact hole BC that partially exposes the light-blocking pattern 410. The second intermediate hole BC2 may partially expose the portion of the light-blocking pattern 410 that overlaps with the first intermediate hole BC1. For example, the second intermediate hole BC2 may completely penetrate the upper buffer layer 112 and the lower buffer layer 111 in the first intermediate hole BC1. The vertical depth of the second intermediate hole BC2 may be less than the vertical depth of the first intermediate hole BC1. The second intermediate hole BC2 may be separated from the upper electrode 420 of the capacitor. For example, the intermediate contact hole BC may expose a portion of the light-blocking pattern 410 outside the upper electrode 420 of the capacitor.

[0134] A second curved hole OP2 may be formed within a first curved hole OP1. For example, the first curved hole OP1 and the second curved hole OP2 may constitute a curved opening OP that partially exposes the curved region BA of the device substrate 100. The second curved hole OP2 may partially expose the portion of the device substrate 100 that overlaps with the first curved hole OP1. The second curved hole OP2 may penetrate the upper buffer layer 112 and the lower buffer layer 111 of the curved region BA. The vertical depth of the second curved hole OP2 may be less than the vertical depth of the first curved hole OP1. The vertical depth of the second curved hole OP2 may be greater than the sum of the thicknesses of the upper buffer layer 112 and the lower buffer layer 111 in the first curved hole OP1. For example, the step of forming the second curved hole OP2 may include forming a trench in the portion of the device substrate 100 that overlaps with the second curved hole OP2. A substrate recess 100r that overlaps with the second curved hole OP2 may be formed in the curved region BA of the device substrate 100.

[0135] A method for forming a display device according to an embodiment of the present invention may include the steps of forming a first source 240, a first drain 250, a second source 340, a second drain 350, and an intermediate electrode 600 on a device substrate 100 in which a first source contact hole SC1, a first drain contact hole DC1, a second source contact hole SC2, a second drain contact hole DC2, an intermediate contact hole BC, and a bent opening OP are formed, such as... Figure 12 As shown.

[0136] The first source 240 can be connected to the first source region of the first semiconductor pattern 210 through the first source contact hole SC1, and the first drain 250 can be connected to the first drain region of the first semiconductor pattern 210 through the first drain contact hole DC1. The first semiconductor pattern 210, the first gate insulating layer 220, the first gate 230, the first source 240, and the first drain 250 can constitute a switching thin-film transistor 200. The second source 340 can be connected to the second source region of the second semiconductor pattern 310 through the second source contact hole SC2, and the second drain region 350 can be connected to the second drain region of the second semiconductor pattern 310 through the second drain contact hole DC2. The second semiconductor pattern 310, the second gate insulating layer 320, the second gate 330, the second source 340, and the second drain 350 can constitute a driving thin-film transistor 300. The intermediate electrode 600 can be connected to the light-blocking pattern 410 through the intermediate contact hole BC.

[0137] The first source 240, first drain 250, second source 340, second drain 350, and intermediate electrode 600 may comprise conductive materials. For example, the first source 240, first drain 250, second source 340, second drain 350, and intermediate electrode 600 may be formed of metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The first source 240, first drain 250, second source 340, second drain 350, and intermediate electrode 600 may be formed simultaneously. For example, the steps of forming the first source 240, first drain 250, second source 340, second drain 350, and intermediate electrode 600 may include: forming a conductive material layer for filling the first source contact hole SC1, first drain contact hole DC1, second source contact hole SC2, second drain contact hole DC2, and intermediate contact hole BC; and patterning the conductive material layer using a mask. Therefore, in the method for forming a display device according to an embodiment of the present invention, it is not necessary to use an additional mask to form the intermediate contact hole BC and the intermediate electrode 600. Thus, the method for forming a display device according to an embodiment of the present invention can connect the light-blocking pattern 410 to one of the signal wirings without degrading process efficiency.

[0138] A method for forming a display device according to an embodiment of the present invention may include: the step of forming a first planarization layer 150 on a device substrate 100 in which a first source electrode 240, a first drain electrode 250, a second source electrode 340, a second drain electrode 350, and an intermediate electrode 600 are formed; and the step of forming a first connection hole IC1 and a second connection hole IC2 in the first planarization layer 150, such as... Figure 13 As shown.

[0139] The first planarization layer 150 may be formed of an insulating material. The first planarization layer 150 may be formed of a material different from the second interlayer insulating layer 140. For example, the first planarization layer 150 may be formed of an organic insulating material. Thus, in the method of forming a display device according to an embodiment of the present invention, the thickness difference caused by the switching thin-film transistor 200, driving thin-film transistor 300, storage capacitor 400, and intermediate electrode 600 disposed on the pixel region PA of the device substrate 100 can be mitigated by the first planarization layer 150. The first planarization layer 150 may be formed on the pixel region PA and the curved region BA of the device substrate 100. For example, the curved opening OP disposed on the curved region BA of the device substrate 100 may be filled by the first planarization layer 150.

[0140] A first connection hole IC1 and a second connection hole IC2 may be formed on the pixel region PA of the device substrate 100. For example, the first connection hole IC1 may partially expose the second drain 350 of the driving thin-film transistor 300, and the second connection hole IC2 may expose a portion of the intermediate electrode 600. For example, the first connection hole IC1 and the second connection hole IC2 may completely penetrate the first planarization layer 150. The second connection hole IC2 may be formed simultaneously with the first connection hole IC1.

[0141] A method for forming a display device according to an embodiment of the present invention may include the step of forming a first connection electrode 710 and a second connection electrode 720 on a first planarization layer 150 in which a first connection hole IC1 and a second connection hole IC2 are formed, such as... Figure 14 As shown.

[0142] The first connection electrode 710 can be connected to the second drain 350 of the driving thin-film transistor 300 through the first connection hole IC1. The second connection electrode 720 can be connected to the intermediate electrode 600 through the second connection hole IC2. The first connection hole IC1 and the second connection hole IC2 can be formed of a conductive material. For example, the first connection hole IC1 and the second connection hole IC2 can be formed of metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The second connection electrode 720 can be formed simultaneously with the first connection electrode 710. For example, the steps of forming the first connection electrode 710 and the second connection electrode 720 may include: forming a conductive material layer on the first planarization layer 150 for filling the first connection hole IC1 and the second connection hole IC2; and patterning the conductive material layer using a mask.

[0143] A method for forming a display device according to an embodiment of the present invention may include: the step of forming a second planarization layer 160 on a device substrate 100 in which a first connecting electrode 710 and a second connecting electrode 720 are formed; and the step of forming an electrode contact hole EC in the second planarization layer 160 of the pixel region PA, such as Figure 15 As shown.

[0144] The second planarization layer 160 may be formed of an insulating material. For example, the second planarization layer 160 may be formed of an organic insulating material. The second planarization layer 160 may be formed of a different material than the first planarization layer 150. The first planarization layer 150 and the second planarization layer 160 can eliminate the thickness difference caused by the switching thin-film transistor 200, driving thin-film transistor 300, storage capacitor 400, intermediate electrode 600, first connection electrode 710 and second connection electrode 720 on the pixel region PA of the device substrate 100. For example, the upper surface of the second planarization layer 160 opposite to the device substrate 100 may be a flat surface in the pixel region PA of the device substrate 100. The second planarization layer 160 may be formed on the pixel region PA and the curved region BA of the device substrate 100. For example, the first planarization layer 150 and the second planarization layer 160 may be stacked sequentially on a portion of the device substrate 100 exposed through the curved opening OP.

[0145] The electrode contact hole EC can partially expose the first connection electrode 710. For example, the electrode contact hole EC can completely penetrate the second planarization layer 160.

[0146] A method for forming a display device according to an embodiment of the present invention may include the step of forming a first electrode 510 on a pixel region PA of a device substrate 100 in which electrode contact holes EC are formed, such as... Figure 16 As shown.

[0147] The first electrode 510 may comprise a conductive material. The first electrode 510 may be formed of a material with high reflectivity. The first electrode 510 may have a multilayer structure. For example, the steps of forming the first electrode 510 may include: forming a first transparent electrode layer on the device substrate 100 using a transparent conductive material such as ITO and IZO; forming a reflective electrode layer on the first transparent electrode layer using a metal; forming a second transparent electrode layer on the reflective electrode layer using a transparent conductive material such as ITO and IZO; and sequentially patterning the second transparent electrode layer, the reflective electrode layer, and the first transparent electrode layer using a mask.

[0148] A method for forming a display device according to an embodiment of the present invention may include the step of forming a retaining layer 170 on a pixel region PA of a device substrate 100, such as... Figure 17 As shown.

[0149] The dam insulating layer 170 may be formed of an insulating material. For example, the dam insulating layer 170 may be formed of an organic insulating material. The dam insulating layer 170 may expose a portion of the first electrode 510. For example, the dam insulating layer 170 may cover the edge of the first electrode 510. The dam insulating layer 170 may be in direct contact with the second planarization layer 160 outside the first electrode 510. For example, the step of forming the dam insulating layer 170 may include: forming an insulating material layer on the device substrate 100 in which the first electrode 510 is formed; and using a mask to remove a portion of the insulating material layer overlapping a portion of the first electrode 510. The dam insulating layer 170 may be formed of a material different from the second planarization layer 160.

[0150] A method for forming a display device according to an embodiment of the present invention may include the step of forming a light-emitting layer 520 on a portion of the first electrode 510 exposed by the insulating layer 170, such as... Figure 18 As shown.

[0151] The light-emitting layer 520 can be formed using a fine metal mask (FMM). For example, the steps of forming the light-emitting layer 520 may include: forming a spacer 180 on the embankment insulating layer 170; placing a fine metal mask (FMM) having an opening that overlaps with a portion of the first electrode 510 exposed by the embankment insulating layer 170 on the spacer 180; and depositing a light-emitting material through the opening of the fine metal mask (FMM).

[0152] A method for forming a display device according to an embodiment of the present invention may include the step of forming a second electrode 530 on a pixel region PA of a device substrate 100 in which a light-emitting layer 520 is formed, such as... Figure 2 and Figures 3A to 3C As shown.

[0153] The second electrode 530 may be formed of a conductive material. The second electrode 530 may be formed as a transparent electrode with a higher transmittance than the first electrode 510. For example, the second electrode 530 may be formed of a transparent conductive material such as ITO and IZO. The first electrode 510, the light-emitting layer 520, and the second electrode 530 may constitute a light-emitting device 500.

[0154] Therefore, a display device according to an embodiment of the present invention may include a light-blocking pattern 410 in each pixel region PA of the device substrate 100 to block light propagating in a direction toward the second semiconductor pattern 310 of the driving thin-film transistor 300 in the corresponding pixel region PA. An intermediate contact hole BC exposing a portion of the light-blocking pattern 410 may be formed using a process of forming a bent opening OP in a bent region BA of the device substrate 100. An intermediate electrode 600 connected to the light-blocking pattern 410 via the intermediate contact hole BC may be formed using a process of forming the second source 340 and the second drain 350 of the driving panel transistor 300. Thus, in a display device according to an embodiment of the present invention, the light-blocking pattern 410 can be connected to one of the signal wirings without the need for an additional masking process. Therefore, in a display device according to an embodiment of the present invention, characteristic changes of the driving thin-film transistor 300 due to external light can be effectively prevented without degrading process efficiency.

[0155] A display device according to an embodiment of the present invention is described as follows: the light-blocking pattern 410 in each pixel region PA is in the shape of an island. However, in a display device according to another embodiment of the present invention, the light-blocking pattern 410 may have a mesh shape extending along a first direction and a second direction perpendicular to the first direction. For example, in a display device according to another embodiment of the present invention, the light-blocking pattern 410 in each pixel region PA may be connected to the light-blocking patterns 410 of adjacent pixel regions PA in the first direction and the light-blocking patterns 410 of adjacent pixel regions PA in the second direction. Thus, in a display device according to another embodiment of the present invention, voltage can be stably applied to the light-blocking pattern of each pixel region PA. Furthermore, in a display device according to another embodiment of the present invention, the resistance of the signal wiring electrically connected to the light-blocking pattern 410 can be reduced by the light-blocking pattern 410. For example, in a display device according to another embodiment of the present invention, the light-blocking pattern 410 can be used to prevent voltage drop due to the resistance of the power supply line. Therefore, in a display device according to another embodiment of the present invention, brightness deviation of the light-emitting device 500 in each pixel region PA can be prevented.

[0156] A display device according to an embodiment of the present invention is described as follows: the driving circuit of each pixel region PA may include a single switching thin-film transistor 200. However, in a display device according to another embodiment of the present invention, multiple switching thin-film transistors 200 may be provided in each pixel region PA.

[0157] For example, in a display device according to another embodiment of the present invention, the driving circuit of each pixel region PA may include a first switching thin-film transistor 200, a driving thin-film transistor 300, and a second switching thin-film transistor 800, such as Figure 19As shown. The second switching thin-film transistor 800 may have the same structure as the first switching thin-film transistor 200. For example, the second switching thin-film transistor 800 may include a third semiconductor pattern 810, a third gate insulating layer 820, a third gate 830, a third source 840, and a third drain 850.

[0158] The third semiconductor pattern 810 may comprise a semiconductor material. The third semiconductor pattern 810 may comprise a different material than the first semiconductor pattern 210 of the first switching thin-film transistor 200. For example, the third semiconductor pattern 810 may comprise an oxide semiconductor such as IGZO. The third semiconductor pattern 810 may be disposed on a different layer than the first semiconductor pattern 210. For example, the third semiconductor pattern 810 may be disposed on the same layer as the second semiconductor pattern 310 of the driving thin-film transistor 300. The third semiconductor pattern 810 may comprise the same material as the second semiconductor pattern 310.

[0159] The third semiconductor pattern 810 may include a third source region, a third channel region, and a third drain region. The third channel region may be disposed between the third source region and the third drain region. The third source region and the third drain region may have a lower resistance than the third channel region. For example, the third source region and the third drain region may include conductive regions of an oxide semiconductor. The third channel region may be a non-conductive region of an oxide semiconductor.

[0160] The third gate insulating layer 820 may be disposed on the third channel region of the third semiconductor pattern 810. The third source region and the third drain region of the third semiconductor pattern 810 may be disposed outside the third gate insulating layer 820. The third gate 830 may be disposed on the third gate insulating layer 820. For example, the third gate 830 may overlap with the third channel region of the third semiconductor pattern 810.

[0161] The third gate insulating layer 820 may comprise an insulating material. For example, the third gate insulating layer 820 may comprise an inorganic insulating material such as silicon oxide (SiO). The third gate insulating layer 820 may comprise the same material as the second gate insulating layer 320 of the driving thin-film transistor 300. The third gate 830 may comprise a conductive material. For example, the third gate 830 may comprise a metal such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The third gate 830 may comprise the same material as the second gate 330 of the driving thin-film transistor 300. The third gate 830 may be insulated from the third semiconductor pattern 810 through the third gate insulating layer 820. For example, the third channel region of the third semiconductor pattern 810 may have a conductivity corresponding to the voltage applied to the third gate 830.

[0162] The third source 840 and the third drain 850 may contain conductive materials. For example, the third source 840 and the third drain 850 may contain metals such as aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). The third source 840 and the third drain 850 may contain materials different from those of the third gate 830. The third source 840 and the third drain 850 may be insulated from the third gate 830. The third source 840 and the third drain 850 may be disposed on different layers from the third gate 830. For example, a second interlayer insulating layer 140 may extend between the third gate 830 and the third source 840, and between the third gate 830 and the third drain 850. The third source 840 and the third drain 850 may contain the same materials as the second source 340 and the second drain 350 of the driving thin-film transistor 300.

[0163] The second switching thin-film transistor 800 can be separated from the first switching thin-film transistor 200 and the driving thin-film transistor 300. For example, in a display device according to another embodiment of the present invention, an internal compensation circuit including the second switching thin-film transistor 800 can be provided in each pixel region PA. Thus, in a display device according to another embodiment of the present invention, the configuration freedom of each pixel region PA can be improved.

[0164] A display device according to an embodiment of the present invention is described as follows: the upper electrode 420 of the capacitor comprises a material different from that of the first gate 230. However, in a display device according to another embodiment of the present invention, the upper electrode 420 of the capacitor may be formed of the same material as the first gate 230. For example, the upper electrode 420 of the capacitor may be formed simultaneously with the first gate 230. The upper electrode 420 of the capacitor may be disposed on the same layer as the first gate 230. For example, the upper electrode 420 of the capacitor may be disposed between the first gate insulating layer 220 and the first interlayer insulating layer 120. Thus, in a display device according to another embodiment of the present invention, the process of forming the storage capacitor 400 can be simplified. Therefore, in a display device according to another embodiment of the present invention, process efficiency can be improved.

[0165] The display device according to an embodiment of the present invention is described as follows: the light-blocking pattern 410 of each pixel region PA is an electrode of the storage capacitor 400 of the corresponding pixel region PA. However, in a display device according to another embodiment of the present invention, the storage capacitor 400 of each pixel region PA may not include the light-blocking pattern 410 of the corresponding pixel region PA.

[0166] For example, in a display device according to another embodiment of the present invention, the storage capacitor 400 in each pixel region PA may have a stacked structure of a lower electrode 425 and an upper electrode 435 separated from the light-blocking pattern 410 of the corresponding pixel region PA, such as Figure 20As shown. The lower electrode 425 and upper electrode 435 of the capacitor can be disposed on layers different from the light-blocking pattern 410. For example, the lower electrode 425 can be disposed between the first gate insulating layer 220 and the first interlayer insulating layer 120, and the upper electrode 435 can be disposed between the first interlayer insulating layer 120 and the separating insulating layer 130. The lower electrode 425 can contain the same material as the first gate 230. The upper electrode 435 can contain a different material than the lower electrode 425. Thus, in a display device according to another embodiment of the present invention, the light-blocking pattern 410 can effectively block external light.

[0167] A display device according to an embodiment of the present invention is described as follows: the storage capacitor 400 of each pixel region PA has a stacked structure of a light-blocking pattern 410 and an upper electrode 420 of the capacitor. However, in a display device according to another embodiment of the present invention, the storage capacitor of each pixel region PA may have a stacked structure of three or more capacitor electrodes.

[0168] For example, in a display device according to another embodiment of the present invention, the storage capacitor 400 of each pixel region PA may further include a capacitor intermediate electrode 415 located between the light-blocking pattern 410 and the upper electrode 420 of the capacitor, such as Figure 21 As shown. The capacitor intermediate electrode 415 can be formed using the process for forming the switching thin-film transistor 200. For example, the capacitor intermediate electrode 415 can be disposed on the same layer as the first gate 230 of the switching thin-film transistor 200. The capacitor intermediate electrode 415 can contain the same material as the first gate 230. Thus, in a display device according to another embodiment of the present invention, the area occupied by the storage capacitor 400 of each pixel region PA can be reduced without degrading process efficiency. Therefore, in a display device according to another embodiment of the present invention, the resolution can be improved.

[0169] A display device according to an embodiment of the present invention is described as follows: a first planarization layer 150 and a second planarization layer 160 are stacked between the driving circuit and the light-emitting device 500 in each pixel region PA. However, in a display device according to another embodiment of the present invention, the second planarization layer 160 may be omitted, as... Figure 22 As shown. Therefore, in a display device according to another embodiment of the present invention, the light-emitting device 500 of each pixel region PA can be disposed on the first planarization layer 150. The first electrode 510 in each pixel region PA can directly contact the second drain 350 of the driving thin-film transistor 300 by penetrating the first planarization layer 150. Therefore, in a display device according to another embodiment of the present invention, the configuration freedom of each pixel region PA can be improved.

[0170] A display device according to an embodiment of the present invention is described as follows: a light-blocking pattern 410 of each pixel region PA is disposed between a device substrate 100 and a buffer insulating layer 110. However, in a display device according to another embodiment of the present invention, the lower surface of the light-blocking pattern 410 in each pixel region PA may be separated from the device substrate 100. For example, in a display device according to another embodiment of the present invention, the light-blocking pattern 410 of each pixel region PA may be disposed between a lower buffer layer 111 and an upper buffer layer 112, such as... Figure 23 and 24 As shown. That is, the lower buffer layer 111 may extend between the device substrate 100 and the light-blocking pattern 410. The lower end portion 600e of the intermediate electrode 600 may be positioned closer to the device substrate 100 than the upper surface of the light-blocking pattern 410. For example, the light-blocking pattern 410 may include a blocking recess 410r overlapping with the second intermediate hole BC2.

[0171] Figure 25 and 26 This is a view showing, in sequence, a method for forming a display device according to another embodiment of the present invention. (Refer to...) Figures 23 to 26 A method for forming a display device according to another embodiment of the present invention is described. First, the method for forming a display device according to another embodiment of the present invention may include: forming a lower buffer layer 111 on a pixel region PA and a curved region BA of a device substrate 100; forming a light-blocking pattern 410 on the lower buffer layer 111 of the pixel region PA; forming an upper buffer layer 112 on the pixel region PA and the curved region BA of the device substrate 100 in which the light-blocking pattern 410 is formed; and forming a first semiconductor pattern 210, a first gate insulating layer 220, a first gate 230, a first interlayer insulating layer 120, a capacitor upper electrode 420, a separating insulating layer 130, a second semiconductor pattern 310, a second gate insulating layer 320, a second gate 330, a first source contact hole SC1, a first drain contact hole DC1, a first intermediate hole BC1, and a first curved hole OP1 on the upper buffer layer 112, as follows: Figure 25 As shown.

[0172] A method for forming a display device according to another embodiment of the present invention may include the step of forming a second source contact hole SC2, a second drain contact hole DC2, a second intermediate hole BC2, and a second bent hole OP2 on a device substrate 100 in which a first source contact hole SC1, a first drain contact hole DC1, a first intermediate hole BC1, and a first bent hole OP1 are formed, such as... Figure 26 As shown.

[0173] The second intermediate hole BC2 can be formed simultaneously with the second curved hole OP2. The bottom surface of the second intermediate hole BC2 can be positioned closer to the device substrate 100 than the upper surface of the light-blocking pattern 410. For example, the step of forming the second intermediate hole BC2 may include forming a trench in the portion of the light-blocking pattern 410 that overlaps with the second intermediate hole BC2. The blocking recess 410 may be formed in the portion of the light-blocking pattern 410 that overlaps with the second intermediate hole BC2.

[0174] According to another embodiment of the present invention, a method for forming a display device may include the steps of forming a first source electrode 240, a first drain electrode 250, a second source electrode 340, a second drain electrode 350, an intermediate electrode 600, a first planarization layer 150, a first connecting electrode 710, a second connecting electrode 720, a second planarization layer 160, a light-emitting device 500, a dam insulating layer 170, and a spacer 180 on a device substrate 100 in which a blocking recess region 410r is formed. Figure 23 and 24 As shown.

[0175] Therefore, in a display device according to another embodiment of the present invention, the light-blocking pattern 410 of each pixel region PA can be formed in the buffer insulating layer 110. Thus, in a display device according to another embodiment of the present invention, damage to the device substrate 100 caused by the process of forming the light-blocking pattern 410 can be prevented. Therefore, in a display device according to another embodiment of the present invention, the positional freedom of the light-blocking pattern 410 can be improved.

[0176] A display device according to an embodiment of the present invention is described as follows: the intermediate contact hole BC includes a first intermediate hole BC1 and a second intermediate hole BC2. However, in a display device according to another embodiment of the present invention, the intermediate contact hole BC can be formed by a single process. For example, in a display device according to another embodiment of the present invention, each of the first source contact hole SC1, the first drain contact hole, and the first bent hole OP1 can expose a portion of the lower buffer layer 111, such as... Figure 27 and 28A As shown in Figure 28C, the first source contact hole SC1, the first drain contact hole, the intermediate contact hole BC, and the first bent hole OP1 can penetrate the upper buffer layer 112, the first gate insulating layer 220, the first interlayer insulating layer 120, the separator insulating layer 130, and the second interlayer insulating layer 140. The bottom surface Sb of the first source contact hole SC1 can be set to be closer to the device substrate 100 than the upper surface of the lower buffer layer 111. For example, the vertical depth h6 of the first source contact hole SC1 can be greater than the vertical depth h7 of the intermediate contact hole BC.

[0177] The vertical depth h8 of the first bent hole OP1 can be equal to the vertical depth h6 of the first source contact hole SC1. For example, the first source contact hole SC1, the first drain contact hole, the intermediate contact hole BC, and the first bent hole OP1 can be formed simultaneously. The lower buffer layer 111 of the bent region BA may include a lower recessed region 111r overlapping the first bent hole OP1. The second bent hole OP2 formed in the first bent hole OP1 can penetrate the lower buffer layer 111. For example, the vertical depth h9 of the second bent hole OP2 can be less than the thickness of the buffer insulating layer 110. A trench can be formed in the portion of the device substrate 100 that overlaps with the second bent hole OP2.

[0178] In a display device according to another embodiment of the present invention, the intermediate contact hole BC exposing a portion of the light-blocking pattern 410 can be formed simultaneously with the first source contact hole SC1, the first drain contact hole, and the first bent hole OP1. Therefore, in the display device according to another embodiment of the present invention, the positional freedom of the light-blocking pattern 410 can be improved without causing over-etching of the light-blocking pattern 410 through the process of forming the intermediate contact hole BC. Thus, in the display device according to another embodiment of the present invention, changes in the characteristics of the driving thin-film transistor 300 due to external light can be effectively prevented without degrading process efficiency.

[0179] A display device according to another embodiment of the present invention may include a substrate hole CH disposed between pixel areas PA of display area AA, such as Figure 29 and 30 As shown. The substrate hole CH can penetrate a portion of the device substrate 100. At least one separating partition 900 can be disposed around the substrate hole CH. For example, the device substrate 100 may include a hole periphery region HA formed by a hole region CA in which the substrate hole CH is disposed and a separating region SA in which the separating partition 900 is disposed. The separating region SA can be disposed between the pixel region PA and the hole region CA. For example, the hole region CA can be surrounded by the separating region SA.

[0180] The separator 900 may include at least one undercut portion UC. The organic layer formed by subsequent processes may be partially interrupted by the undercut portion UC of the separator 900. The vertical distance of the separator 900 may be greater than the vertical depth of the curved opening OP. Thus, the display device according to another embodiment of the present invention can prevent external moisture introduced through the substrate hole CH from penetrating into the pixel area PA via the organic layer.

[0181] The separator 900 may have a stacked structure of a main body 910 and a cover 920. The main body 910 of the separator 900 may be formed using a process that forms a driving circuit in each pixel region PA. For example, the main body 910 of the separator 900 may include a first insulating pattern 911, a second insulating pattern 912, a third insulating pattern 913, a fourth insulating pattern 914, a fifth insulating pattern 915, and a sixth insulating pattern 916 sequentially stacked on the device substrate 100. The first insulating pattern 911 may contain the same material as the lower buffer layer 111. The second insulating pattern 912 may contain the same material as the upper buffer layer 112. The third insulating pattern 913 may contain the same material as the first gate insulating layer 220. The fourth insulating pattern 914 may contain the same material as the first interlayer insulating layer 120. The fifth insulating pattern 915 may contain the same material as the separator insulating layer 130. The sixth insulating pattern 916 may contain the same material as the second interlayer insulating layer 140. The patterning process of the first insulating pattern 911, the second insulating pattern 912, the third insulating pattern 913, the fourth insulating pattern 914, the fifth insulating pattern 915, and the sixth insulating pattern 916 can be performed simultaneously with the process of forming the bent opening OP. For example, a substrate recess 100r can be formed in a portion of the device substrate 100 surrounding the separator 900. Separator recesses 912r can be formed at both ends of the second insulating pattern 912. The cover portion 920 can be formed using at least one layer formed on the second interlayer insulating layer 140. For example, the cover portion 920 may contain the same material as the second planarization layer 160.

[0182] The undercut portion UC can be formed by selective etching of insulating patterns 911, 912, 913, 914, 915, and 916. For example, in a display device according to another embodiment of the present invention, the lower buffer layer 111, the first insulating pattern 911, the upper buffer layer 112, the second insulating pattern 912, the first gate insulating layer 220, the third insulating pattern 913, the separator insulating layer 130, and the fifth insulating pattern 915 can be formed of silicon oxide (SiO), and the first interlayer insulating layer 120, the fourth insulating pattern 914, the second interlayer insulating layer 140, and the sixth insulating pattern 916 can be formed of silicon nitride (SiN). The undercut portion UC of the separator 900 can be formed by over-etching the fourth insulating pattern 914 and the sixth insulating pattern 916 formed of silicon nitride (SiN). Thus, in a display device according to another embodiment of the present invention, the separator 900 and the intermediate contact hole can be formed using a process for forming a curved opening OP. Therefore, in a display device according to another embodiment of the present invention, changes in the characteristics of the driving thin-film transistors due to external light and degradation of the light-emitting layer in each pixel region PA due to external moisture introduced through the substrate hole CH can be prevented without degrading process efficiency.

[0183] As a result, the display device according to an embodiment of the present invention may include a central contact hole located on a pixel region of a device substrate and a bent opening located on a bent region of the device substrate, wherein a central electrode can be connected to a light-blocking pattern through the central contact hole, wherein the bent opening can partially expose the bent region of the device substrate, and wherein the central contact hole can be formed using a process for forming bent openings. Therefore, in the display device according to an embodiment of the present invention, an additional mask for forming the central contact hole is not required. Thus, in the display device according to an embodiment of the present invention, changes in the characteristics of the driving thin-film transistor can be effectively prevented without degrading process efficiency.

Claims

1. A display device, comprising: Light-blocking patterns on the pixel area of ​​the device substrate; An upper buffer layer is provided on the light-blocking pattern, the upper buffer layer extending over the curved area of ​​the device substrate; A switching thin-film transistor on the upper buffer layer of the pixel region, the switching thin-film transistor comprising a first semiconductor pattern separated from the light-blocking pattern; A separating insulating layer on the first semiconductor pattern, the separating insulating layer extending on the upper buffer layer of the bending region; A driving thin-film transistor on the separating insulating layer of the pixel region, the driving thin-film transistor including a second semiconductor pattern overlapping a portion of the light-blocking pattern; An interlayer insulating layer is provided on the second semiconductor pattern, the interlayer insulating layer extending over the separating insulating layer in the bending region, the source and drain of the driving thin-film transistor being connected to the second semiconductor pattern through contact holes in the interlayer insulating layer, and the lower surfaces of the source and drain of the driving thin-film transistor contacting the interlayer insulating layer. A bent opening on the bent area of ​​the device substrate, the bent opening including a first bent opening exposing a portion of the upper buffer layer and a second bent opening exposing a portion of the device substrate in the first bent opening; An intermediate electrode is located on the interlayer insulating layer in the pixel region, and the intermediate electrode is connected to the light-blocking pattern via an intermediate contact hole; as well as A planarization layer is applied to the intermediate electrode and the source and drain electrodes of the driving thin-film transistor, the planarization layer filling the curved opening in the curved region. The intermediate contact hole includes a first intermediate hole that partially exposes the upper buffer layer of the pixel area and a second intermediate hole that partially exposes a portion of the light-blocking pattern overlapping with the first intermediate hole. The vertical depth of the first intermediate hole is the same as the vertical depth of the first curved hole.

2. The display device according to claim 1, wherein the first semiconductor pattern comprises silicon and the second semiconductor pattern comprises oxide semiconductor.

3. The display device according to claim 1, wherein the vertical depth of the second intermediate hole is less than the vertical depth of the second curved hole.

4. The display device according to claim 3, wherein the bending region of the device substrate includes a substrate recess region overlapping with the second bending hole.

5. The display device according to claim 1, wherein the bottom surface of the first intermediate hole is configured to be closer to the device substrate than the upper surface of the upper buffer layer. The upper buffer layer of the curved area includes an upper recessed area that overlaps with the first curved hole.

6. The display device according to claim 5, wherein the vertical depth of the upper recessed area is equal to the distance between the bottom surface of the first intermediate hole and the upper surface of the upper buffer layer.

7. The display device according to claim 1, wherein the source of the switching thin-film transistor is connected to the source region of the first semiconductor pattern via a source contact hole. The drain of the aforementioned switching thin-film transistor is connected to the drain region of the first semiconductor pattern via a drain contact hole. The source contact hole and the drain contact hole penetrate the first semiconductor pattern.

8. The display device according to claim 7, wherein the vertical depth of the source contact hole is equal to the vertical depth of the first intermediate hole. The vertical depth of the drain contact hole is equal to the vertical depth of the source contact hole.

9. The display device according to claim 1, further comprising a lower buffer layer located between the device substrate and the upper buffer layer. The lower buffer layer extends between the device substrate and the light-blocking pattern.

10. The display device according to claim 9, wherein the light-blocking pattern includes a blocking recess area overlapping with the second intermediate hole.

11. A display device, comprising: Device substrate including pixel area and bending area; A buffer insulating layer on the device substrate, the buffer insulating layer comprising a stacked structure of a lower buffer layer and an upper buffer layer; The light-blocking pattern between the upper and lower buffer layers in the pixel area; A first switching thin-film transistor on the upper buffer layer of the pixel region, the first switching thin-film transistor comprising a first semiconductor pattern disposed outside the light-blocking pattern; A separating insulating layer covering the first semiconductor pattern, the separating insulating layer extending over the upper buffer layer of the bending region; A driving thin-film transistor on the separating insulating layer of the pixel region, the driving thin-film transistor including a second semiconductor pattern overlapping a portion of the light-blocking pattern; An interlayer insulating layer is provided on the second semiconductor pattern, the interlayer insulating layer extending over the separating insulating layer in the bending region, the source and drain of the driving thin-film transistor being connected to the second semiconductor pattern through contact holes in the interlayer insulating layer, and the lower surfaces of the source and drain of the driving thin-film transistor contacting the interlayer insulating layer. A curved opening is provided on the curved area of ​​the device substrate, the curved opening including a first curved hole exposing a portion of the lower buffer layer and a second curved hole exposing a portion of the device substrate in the first curved hole; An intermediate electrode is located on the interlayer insulating layer in the pixel region, and the intermediate electrode is connected to the light-blocking pattern via an intermediate contact hole; as well as A planarization layer is applied to the intermediate electrode and the source and drain electrodes of the driving thin-film transistor, the planarization layer filling the curved opening in the curved region. The vertical depth of the first curved hole is greater than or equal to the vertical depth of the intermediate contact hole.

12. The display device of claim 11, further comprising a second switching thin-film transistor on the separating insulating layer of the pixel region. The second switching thin-film transistor includes a third semiconductor pattern made of the same material as the second semiconductor pattern. The third semiconductor pattern is separated from the intermediate electrode and the second semiconductor pattern.

13. The display device of claim 11, wherein the lower buffer layer of the curved region includes a recessed region overlapping the first curved hole.

14. The display device of claim 13, wherein the source of the first switching thin-film transistor is connected to the source region of the first semiconductor pattern via a source contact hole, wherein The drain of the first switching thin-film transistor is connected to the drain region of the first semiconductor pattern via a drain contact hole. The bottom surface of the source contact hole and the bottom surface of the drain contact hole are positioned closer to the device substrate than the top surface of the lower buffer layer.

15. The display device of claim 11, further comprising an upper electrode of a capacitor between the light-blocking pattern and the second semiconductor pattern.

16. The display device of claim 15, wherein the upper electrode of the capacitor comprises a material different from the gate of the first switching thin-film transistor.

17. The display device according to claim 11, wherein the device substrate further includes a hole region and a partition region, wherein a substrate hole is disposed in the hole region, and a partition portion is disposed in the partition region. The separating region is located between the pixel region and the hole region. The partition includes at least one undercut portion. The vertical distance of the partition is greater than the vertical depth of the curved opening.

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