Array substrate, display panel and display device

Abstract

This application discloses an array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area at least partially surrounding the display area, the non-display area including a terminal area; the array substrate includes: a reset signal line located in the display area; a signal terminal located in the terminal area; and a connecting line located on the side of the display area near the terminal area, the connecting line connecting the signal terminal and the reset signal line. The array substrate, display panel, and display device provided according to the embodiments of this application are advantageous for achieving narrow left and right bezels.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous advancement of display panel technology, display panels are gradually evolving towards thinner and lighter designs, higher screen-to-body ratios, and ultra-narrower bezels. A display panel typically includes a display area and a non-display area surrounding the display area; the non-display area is used for arranging signal lines. In related technologies, the arrangement of signal lines within the non-display area is not conducive to achieving narrow bezels. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display device, which are beneficial for achieving narrow left and right bezels.

[0004] In a first aspect, embodiments of this application provide an array substrate having a display area and a non-display area at least partially surrounding the display area, the non-display area including a terminal area; the array substrate includes: a reset signal line located in the display area; a signal terminal located in the terminal area; and a connecting line located on the side of the display area near the terminal area, the connecting line connecting between the signal terminal and the reset signal line.

[0005] Secondly, embodiments of this application provide a display panel, including an array substrate as described in the first aspect embodiment.

[0006] Thirdly, embodiments of this application provide a display device, including a display panel as described in the second aspect embodiment.

[0007] According to the array substrate, display panel and display device provided in the embodiments of this application, taking the terminal area located on one side of the display area in the column direction as an example, since the connecting line is located in the non-display area and on the side of the display area close to the terminal area, the connecting line does not need to be set in the non-display area on both sides in the row direction. In other words, the connecting line is not set in the non-display area on the left and right sides. This is beneficial to achieve narrow bezels on the left and right sides. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This illustration shows a structural schematic diagram of an array substrate provided in an embodiment of this application;

[0010] Figure 2 This illustration shows a schematic diagram of a pixel circuit in an array substrate provided in an embodiment of this application;

[0011] Figure 3 This illustration shows another structural schematic diagram of the pixel circuit in the array substrate provided in an embodiment of this application;

[0012] Figure 4 This illustration shows another structural schematic diagram of the array substrate provided in an embodiment of this application;

[0013] Figure 5 This illustration shows another structural schematic diagram of the array substrate provided in an embodiment of this application;

[0014] Figure 6 This illustration shows another structural schematic diagram of the array substrate provided in an embodiment of this application;

[0015] Figure 7 This illustration shows another structural schematic diagram of the array substrate provided in an embodiment of this application;

[0016] Figure 8 This illustration shows a schematic diagram of a film structure of an array substrate provided in an embodiment of this application;

[0017] Figure 9 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0018] Figure 10 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0019] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0020] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0021] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0022] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] In the embodiments of this application, the term "connection" can refer to two components being directly connected, or it can refer to two components being connected via one or more other components.

[0024] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0025] This application provides an array substrate, a display panel, and a display device. The array substrate, display panel, and display device provided in this application will be described in detail below with reference to the accompanying drawings.

[0026] like Figure 1As shown, the array substrate 100 provided in this embodiment may include a display area AA and a non-display area NA that at least partially surrounds the display area AA. The non-display area NA may include a terminal area BA, which may be located on one side of the display area AA. For example, the terminal area BA may be located on one side of the display area AA in the second direction Y, where the first direction X and the second direction Y intersect. Taking the first direction X as the row direction and the second direction Y as the column direction as an example, the terminal area BA may be located on one side of the display area AA in the second direction Y.

[0027] The array substrate 100 may include signal lines 10, signal terminals 20, and connecting lines 30.

[0028] Signal line 10 is located in display area AA. Multiple pixel circuits can be arranged within display area AA. Figure 1 (Not shown in the image), signal line 10 can be used to transmit signals to the pixel circuit.

[0029] Signal terminal 20 is located in terminal area BA.

[0030] The connecting line 30 may be located in the non-display area NA and on the side of the display area AA closest to the terminal area BA. For example, the connecting line 30 may be located on one side of the display area AA in the second direction Y. It is understood that in this application, the non-display areas AA on both sides of the display area AA are no longer provided with the connecting line 30 in the first direction X; in other words, the non-display areas NA on the left and right sides are no longer provided with the connecting line 30.

[0031] The connecting line 30 connects the signal terminal 20 and the signal line 10. The signal output from the signal terminal 20 can be transmitted to the signal line 10 via the connecting line 30, and then to the pixel circuit via the signal line 10 to drive the pixel circuit to work.

[0032] According to the array substrate provided in the embodiments of this application, taking the terminal area BA located on one side of the display area AA in the column direction as an example, since the connecting line 30 is located in the non-display area NA and on the side of the display area AA close to the terminal area BA, the connecting line 30 does not need to be set in the non-display areas NA on both sides in the row direction. In other words, the connecting line 30 is not set in the non-display areas NA on the left and right sides. This is beneficial to achieve narrow bezels on the left and right sides.

[0033] In some alternative embodiments, signal line 10 may include a reset signal line for transmitting a reset signal Vref. To better understand the reset signal line, for example, the structure of the pixel circuit may be as follows: Figure 2 As shown, the pixel circuit may include transistors T1 to T7 and a storage capacitor Cst. The pixel circuit can be used to drive the light-emitting element D to emit light. The light-emitting element D may include an organic light-emitting diode. See [link to documentation] for the connection methods of each component. Figure 2 This will not be elaborated upon here. Among them, Figure 2In the diagram, S1, S2, and S3 represent scan lines, EM represents the light emission control signal line, Vdata represents the data signal, Vref represents the reset signal, PVDD represents the first power supply signal, and PVEE represents the second power supply signal.

[0034] The reset signal Vref can be transmitted to transistor T4 via the reset signal line. When transistor T4 is turned on, the reset signal Vref can be transmitted to the gate of transistor T1 to reset the gate of transistor T1. Alternatively, the reset signal Vref can also be transmitted to transistor T7 via the reset signal line. When transistor T7 is turned on, the reset signal Vref can be transmitted to the anode of light-emitting element D to reset the anode of light-emitting element D.

[0035] In some alternative embodiments, signal line 10 may include a bias signal line for transmitting a bias signal DVH. To better understand the bias signal line, for example, the structure of a pixel circuit may be as follows: Figure 3 As shown, the pixel circuit may include transistors T1 to T7 and a storage capacitor Cst. The pixel circuit is used to drive the light-emitting element D to emit light. The light-emitting element D may include an organic light-emitting diode. See [link to diagram] for the connection methods of each component. Figure 3 This will not be elaborated upon here. Among them, Figure 3 In the diagram, S1, S2, S3, and S4 represent scan lines, EM represents the light emission control signal line, Vdata represents the data signal, Vref1 represents the first reset signal, Vref2 represents the second reset signal, DVH represents the bias signal, PVDD represents the first power supply signal, and PVEE represents the second power supply signal.

[0036] The first reset signal Vref1 can be transmitted to transistor T4 via the first reset signal line. When transistor T4 is turned on, the first reset signal Vref1 can be transmitted to the gate of transistor T1 to reset the gate of transistor T1. The second reset signal Vref2 can be transmitted to transistor T7 via the second reset signal line. When transistor T7 is turned on, the first reset signal Vref2 can be transmitted to the anode of light-emitting element D to reset the anode of light-emitting element D. The first reset signal Vref1 and the second reset signal Vref2 can be different.

[0037] The bias signal DVH can be transmitted to transistor T8 via the bias signal line. When transistor T8 is turned on, the bias signal DVH can be transmitted to the source and / or drain of transistor T1 to adjust the bias state of transistor T1.

[0038] In this embodiment of the application, the first power signal PVDD can be a positive voltage signal, and the second power signal PVEE can be a negative voltage signal.

[0039] Figure 2and Figure 3 The pixel circuit structures shown are merely examples and are not intended to limit this application.

[0040] In some alternative embodiments, such as Figure 1 As shown, the signal line 10 may include a main line 11 extending along a first direction X and an auxiliary line 12 extending along a second direction Y.

[0041] Taking the pixel circuits arranged in multiple rows as an example, each row of pixel circuits can be provided with a main line 11, and multiple main lines 11 can be arranged in the second direction Y.

[0042] As an example, the number of auxiliary lines 12 may include at least one. When there is only one auxiliary line 12, the auxiliary line 12 can be connected to multiple main lines 11, and the auxiliary line 12 is connected to the connecting line 30, so that the signal transmitted by the connecting line 30 can be transmitted to each main line 11 via the auxiliary line 12.

[0043] As another example, the number of auxiliary lines 12 may include multiple main lines 11 and multiple auxiliary lines 12, which can be interconnected, and the extension directions of the main lines 11 and auxiliary lines 12 intersect. In this way, the multiple main lines 11 and multiple auxiliary lines 12 can form a grid, which is beneficial to reducing the overall voltage drop of the signal line 10.

[0044] In some alternative embodiments, such as Figure 1 As shown, the edge of the display area AA near the terminal area BA is the first edge a1. The first edge a1 extends along the first direction X, and the center of the first edge a1 is marked O1. The connecting line 30 includes at least one connecting node N0. The signal line 30 is connected to the connecting node N0 of the connecting line 30. In other words, the connecting line 30 is connected to the signal line 30 at the connecting node N0. Specifically, the connecting line 30 can be connected to the auxiliary line 12 at the connecting node N0. In the first direction X, the signal terminal 20 can be located near the edge of the terminal area BA. In the first direction X, at least one connecting node N0 is located on the side of the signal terminal 20 near the center O1 of the first edge a1. In other words, at least one connecting node N0 can be located near the center O1 of the first edge a1. This allows the signal output by the signal terminal 20 to be input to the display area AA from a position near the center, which is equivalent to transmitting the signal from the center of the display area AA to the left and right sides, which helps to improve the uniformity of the display.

[0045] In some alternative embodiments, such as Figure 4 As shown, the connecting line 30 may include a lead portion 31 and a connecting portion 32, with the extending direction of the lead portion 31 intersecting the extending direction of the connecting portion 32. For example, the lead portion 31 may extend along a second direction Y, and the connecting portion 32 may extend generally along a first direction X.

[0046] One end of the lead portion 31 is connected to the signal terminal 20, and the other end of the lead portion 31 is connected to the connection portion 32. The connection portion 32 may include multiple connection nodes N0, and the signal line 10 is connected to the multiple connection nodes N0. Specifically, the connection line 30 may be connected to multiple auxiliary lines 12 at the multiple connection nodes N0. Connecting the signal line at multiple connection nodes is equivalent to inputting signals in parallel to the display area, which can reduce voltage drop.

[0047] Multiple connection nodes N0 can be evenly distributed on the connection portion 32. In the first direction X, at least some of the connection nodes N0 can be located on the side of the signal terminal 20 near the center O1 of the first edge a1. In the first direction X, connection nodes N0 can also be provided on the side of the signal terminal 20 away from the center O1 of the first edge a1.

[0048] In some alternative embodiments, such as Figure 4 As shown, the connecting portion 32 can be parallel to the first edge a1. Taking the connecting line 30 set on the lower edge as an example, it can be understood that the connecting portion 32 has a certain length. If the extension direction of the connecting portion 32 intersects the extension direction of the first edge a1, then the width of the display area NA in the second direction Y needs to be wider to accommodate the connecting portion 32 with a certain length. Therefore, the connecting portion 32 being parallel to the first edge a1 can help to achieve a narrower lower edge.

[0049] In some alternative embodiments, such as Figure 5 As shown, signal line 10 may include a first signal line 10b and a second signal line 10c.

[0050] The signal terminal 20 may include a first signal terminal 21 and a second signal terminal 22 for providing different signals. The connecting line 30 may include a first connecting line 30b and a second connecting line 30c. The first connecting line 30b is connected between the first signal terminal 21 and the first signal line 10b, and the second connecting line 30c is connected between the second signal terminal 22 and the second signal line 10c.

[0051] In this embodiment, the first connecting line 30b and the second connecting line 30c are both located in the non-display area NA and on the side of the display area AA close to the terminal area BA. In this way, the first connecting line 30b and the second connecting line 30c do not need to be set in the non-display areas NA on both sides in the row direction. In other words, the first connecting line 30b and the second connecting line 30c are no longer set in the non-display areas NA on the left and right sides. This is more conducive to achieving narrow bezels on the left and right sides.

[0052] For example, in conjunction with reference Figure 3 The first signal line 10b can be used to transmit the first reset signal Vref1, and the second signal line 10c can be used to transmit the second reset signal Vref2.

[0053] Main line 11 may include a first main line 111 and a second main line 112, and auxiliary line 12 may include a first auxiliary line 121 and a second auxiliary line 122. Connection node N0 may include a first connection node N1 and a second connection node N2. First signal line 10b includes a first main line 111 and a first auxiliary line 121, and second signal line 10c includes a second main line 112 and a second auxiliary line 122. First connection line 30b includes a first connection node N1, and second connection line 30c includes a second connection node N2.

[0054] Multiple first main lines 111 extend along a first direction X, and are arranged along a second direction Y. A first auxiliary line 121 extends along the second direction Y, and the number of first auxiliary lines 121 can be at least one. When there is only one first auxiliary line 121, it can be connected to all of the first main lines 111, and connected to the first connection node N1 of the first connecting line 30b. Thus, the signal transmitted by the first connecting line 30b can be transmitted to each of the first main lines 111 via the first auxiliary line 121. Of course, there can also be multiple first auxiliary lines 121, so that the multiple first main lines 111 and multiple second auxiliary lines 121 can form a grid, which helps to reduce the overall voltage drop of the first signal line 10b.

[0055] Multiple second main lines 112 extend along the first direction X and are arranged along the second direction Y. A second auxiliary line 121 extends along the second direction Y, and the number of second auxiliary lines 121 can be at least one. When there is only one second auxiliary line 121, it can be connected to all of the second main lines 112, and it is connected to the second connection node N2 of the second connection line 30c. Thus, the signal transmitted by the second connection line 30c can be transmitted to each of the second main lines 112 via the second auxiliary line 121. Of course, there can also be multiple second auxiliary lines 121, so that the multiple second main lines 112 and the multiple second auxiliary lines 121 can form a grid, which helps to reduce the overall voltage drop of the second signal line 10c.

[0056] It should be noted that, in order to more clearly distinguish the first signal line 10b and the second signal line 10c, the first signal line 10b is indicated by a solid line and the second signal line 10c is indicated by a dashed line in the accompanying drawings of this application.

[0057] In some alternative embodiments, please continue to refer to Figure 5 Taking the edge of the display area AA near the terminal area BA as the first edge a1 as an example, the first edge a1 extends along the first direction X. In the first direction X, the first connecting line 30b and the first signal terminal 21 are located on one side of the center O1 of the first edge a1, and the second connecting line 30c and the second signal terminal 22 are located on the other side of the center O1 of the first edge a1.

[0058] For example, in the first direction X, the first connecting line 30b and the first signal terminal 21 are located to the left of the center O1 of the first edge a1, and the second connecting line 30c and the second signal terminal 22 are located to the right of the center O1 of the first edge a1. In the first direction X, the first signal terminal 21 is close to the left edge of the terminal area BA, and the second signal terminal 22 is close to the right edge of the terminal area BA.

[0059] In this embodiment of the application, by separating the first connecting line 30b and the second connecting line 30c to two different sides, mutual interference between the signals transmitted by the first connecting line 30b and the second connecting line 30c can be avoided, thereby improving signal stability.

[0060] In some alternative embodiments, such as Figure 6 As shown, the first connecting line 30b may include a first lead portion 311 and a first connecting portion 321. The extending direction of the first lead portion 311 intersects the extending direction of the first connecting portion 321. One end of the first lead portion 311 is connected to the first signal terminal 21, and the other end of the first lead portion 311 is connected to the first connecting portion 321.

[0061] The second connecting line 30c may include a second lead portion 312 and a second connecting portion 322. The extending direction of the second lead portion 312 intersects the extending direction of the second connecting portion 322. One end of the second lead portion 312 is connected to the second signal terminal 22, and the other end of the second lead portion 312 is connected to the second connecting portion 322.

[0062] like Figure 6 As shown, the straight line passing through the center O1 of the first edge a1 is marked as L. The first lead portion 311 and the second lead portion 312 can be symmetrical about the straight line L, and / or the first connecting portion 321 and the second connecting portion 322 can be symmetrical about the straight line L. It is understood that when the first lead portion 311 and the second lead portion 312 are symmetrically arranged, and the first connecting portion 321 and the second connecting portion 322 are symmetrically arranged, the distance between the first connecting portion 321 and the first edge a1 and the distance between the second connecting portion 322 and the first edge a1 are equal, which is more conducive to achieving a narrower bottom bezel.

[0063] The first connection portion 321 may include multiple first connection nodes N1, and the first signal line 10b is connected to the multiple first connection nodes N1. Specifically, the first connection line 30b may be connected to multiple first auxiliary lines 121 at the multiple first connection nodes N1. Connecting the first signal line at the multiple first connection nodes is equivalent to inputting signals in parallel to the display area, which can reduce voltage drop.

[0064] The second connection part 322 may include multiple second connection nodes N2, and the second signal line 10c is connected to the multiple second connection nodes N2. Specifically, the second connection line 30c may be connected to multiple second auxiliary lines 122 at the multiple second connection nodes N2. Similarly, connecting the second signal line at the multiple second connection nodes is equivalent to inputting a signal in parallel to the display area, which can reduce the voltage drop.

[0065] In some alternative embodiments, such as Figure 7 As shown, taking the edge of the display area AA near the terminal area BA as the first edge a1 as an example, the first edge a1 extends along the first direction X in general.

[0066] In the first direction X, at least one first signal terminal 21 is provided on each side of the center O1 of the first edge a1, and a first connecting portion 321 extends from each side of the center O1 of the first edge a1.

[0067] And / or, in the first direction X, at least one second signal terminal 22 is provided on each side of the center O1 of the first edge a1, and a second connecting portion 322 extends from each side of the center O1 of the first edge a1.

[0068] Since first signal terminals 21 are provided on both sides, the two first lead portions 311 connected to the first signal terminals 21 on both sides are equivalent to a parallel structure, which can reduce the voltage drop. Since first connection portions 321 extend from both sides of the center O1 of the first edge a1, first connection nodes N1 can be distributed on both sides of the center O1 of the first edge a1. This allows for the provision of more first connection nodes N1 to provide signals to the first signal line 10b of the display area at more locations, further reducing the voltage drop and improving display uniformity.

[0069] Similarly, since second signal terminals 22 are provided on both sides, the two second lead portions 312 connected to the second signal terminals 22 on both sides are equivalent to a parallel structure, which can reduce the voltage drop. Since second connection portions 322 extend from both sides of the center O1 of the first edge a1, second connection nodes N2 can be distributed on both sides of the center O1 of the first edge a1. This allows for the provision of more second connection nodes N2 to provide signals to the second signal line 10c of the display area at more locations, further reducing the voltage drop and improving display uniformity.

[0070] Please continue to refer to this. Figure 7 The first edge a1 may include a first corner edge a11, a second corner edge a12, and a straight edge a13, with the straight edge a13 located between the first corner edge a11 and the second corner edge a12.

[0071] The first connecting portion 321 may include a first straight portion 3211 and a first corner portion 3212. The first straight portion 3211 is adjacent to the straight side a13, and the first corner portion 3212 is adjacent to the first corner side a11.

[0072] The second connecting portion 322 may include a second straight portion 3221 and a second corner portion 3222, wherein the second straight portion 3221 is adjacent to the straight side a13 and the second corner portion 3222 is adjacent to the second corner side a12.

[0073] Setting a corner section for each corner can reduce the number of traces at the corner, which helps to reduce the border size at the corner.

[0074] For example, the first corner edge a11 and the second corner edge a12 can be arc-shaped edges.

[0075] like Figure 7 As shown, the straight edge a13, the first straight portion 3211, and the second straight portion 3221 can be parallel to each other. It is understood that the first straight portion 3211 and the second straight portion 3221 have a certain length. If the extension direction of the first straight portion 3211 and / or the second straight portion 3221 intersects the extension direction of the straight edge a13, then the display area NA needs to be wider in the second direction Y to accommodate the first straight portion 3211 and the second straight portion 3221 with a certain length. Therefore, the parallelism of the first straight portion 3211 and the second straight portion 3221 with the straight edge a13 helps to achieve a narrower bottom bezel.

[0076] The first corner portion 3212 can be parallel to the first corner edge a11. Similarly, the first corner portion 3212 has a certain length. If the extension direction of the first corner portion 3212 intersects the extension direction of the first corner edge a11, then the frame width at the first corner edge a11 needs to be wider to accommodate the first corner portion 3212 with a certain length. Therefore, the first corner portion 3212 being parallel to the first corner edge a11 can help to achieve a narrower frame at the first corner edge a11.

[0077] The second corner portion 3222 can be parallel to the second corner side a12. Similarly, since the second corner portion 3222 has a certain length, if the extension direction of the second corner portion 3222 intersects the extension direction of the second corner side a12, then the border width at the second corner side a12 needs to be wider to accommodate the second corner portion 3222 with a certain length. Therefore, the second corner portion 3222 being parallel to the second corner side a12 can help to achieve a narrower border at the second corner side a12.

[0078] For example, such as Figure 8As shown, the array substrate 100 may include a substrate 01 and a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, and a third metal layer M3 stacked on one side of the substrate 01, with an insulating layer disposed between adjacent metal layers. A semiconductor layer Poly may be disposed between the first metal layer M1 and the substrate 01.

[0079] As an example, the connector 30 can be designed with a single layer of trace. For instance, the connector 30 can be located on the second metal layer M2 or the third metal layer M3.

[0080] As another example, the connecting line 30 can adopt a double-layer routing design. For example, the connecting line 30 can be set in both the second metal layer M2 and the third metal layer M3, and the two layers of connecting lines 30 set in the second metal layer M2 and the third metal layer M3 can be connected to each other.

[0081] For example, the main line 11 in the display area may be located in the capacitor metal layer MC, and the auxiliary line 12 in the display area may be located in the second metal layer M2.

[0082] It is understood that the film layers in the above examples are merely examples and are not intended to limit this application.

[0083] Based on the same inventive concept, embodiments of this application also provide a display panel. Figure 9 This diagram illustrates the structure of a display panel according to one embodiment of the present application. Figure 9 As shown, the display panel 1000 provided in this application embodiment may include the array substrate described in any of the above embodiments. Figure 9 The display panel shown can be an organic light-emitting diode (OLED) display panel.

[0084] Those skilled in the art should understand that in other implementations of this application, the display panel may also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0085] The display panel provided in this application embodiment has the beneficial effects of the pixel driving circuit provided in this application embodiment. For details, please refer to the specific description of the pixel driving circuit in the above embodiments. This embodiment will not repeat the description here.

[0086] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 10 , Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 10 The provided display device 2000 includes the display panel 1000 provided in any of the above embodiments of this application. Figure 10This embodiment uses a mobile phone as an example to illustrate the display device 2000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0087] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized by, It has a display area and a non-display area at least partially surrounding the display area, the non-display area including a terminal area; The array substrate includes: The signal line is located in the display area. The signal line is a reset signal line or a bias signal line and is electrically connected to the pixel circuit. Signal terminals are located in the terminal area; A connecting line is located in the non-display area and on the side of the display area closer to the terminal area, and the connecting line connects the signal terminal and the signal line.

2. The array substrate of claim 1, wherein, The edge of the display area near the terminal area is the first edge. The connecting line includes at least one connecting node. The signal line is connected to the connecting node. In a first direction, at least one of the connecting nodes is located on the side of the signal terminal near the center of the first edge. The first direction is the extension direction of the first edge.

3. The array substrate according to claim 2, characterized in that, The connecting wire includes a lead portion and a connecting portion, wherein the extending direction of the lead portion intersects the extending direction of the connecting portion. One end of the lead portion is connected to the signal terminal, and the other end is connected to the connection portion. The connection portion includes multiple connection nodes, and the signal line is connected to multiple connection nodes.

4. The array substrate of claim 3, wherein, The connecting portion is parallel to the first edge.

5. The array substrate of claim 1, wherein, The signal line includes a first signal line and a second signal line, the signal terminal includes a first signal terminal and a second signal terminal that provide different signals, and the connecting line includes a first connecting line and a second connecting line. The first connecting line is connected between the first signal terminal and the first signal line, and the second connecting line is connected between the second signal terminal and the second signal line.

6. The array substrate of claim 5, wherein, The edge of the display area near the terminal area is the first edge. In a first direction, the first connecting line and the first signal terminal are located on one side of the center of the first edge, and the second connecting line and the second signal terminal are located on the other side of the center of the first edge. The first direction is the extension direction of the first edge.

7. The array substrate according to claim 6, characterized in that, The first connecting line includes a first lead portion and a first connecting portion. The extending direction of the first lead portion intersects the extending direction of the first connecting portion. One end of the first lead portion is connected to the first signal terminal, and the other end is connected to the first connecting portion. The second connecting line includes a second lead portion and a second connecting portion. The extending direction of the second lead portion intersects the extending direction of the second connecting portion. One end of the second lead portion is connected to the second signal terminal, and the other end is connected to the second connecting portion. The first lead portion and the second lead portion are symmetrical about a straight line passing through the center of the first edge, and / or the first connecting portion and the second connecting portion are symmetrical about a straight line passing through the center of the first edge.

8. The array substrate of claim 7, wherein, The edge of the display area near the terminal area is the first edge, and the extending direction of the first edge is the first direction; In the first direction, at least one first signal terminal is provided on each side of the center of the first edge, and the first connecting portion extends from both sides of the center of the first edge; And / or, in the first direction, at least one second signal terminal is provided on each side of the center of the first edge, and the second connecting portion extends from both sides of the center of the first edge.

9. The array substrate of claim 8, wherein, The first edge includes a straight edge, a first corner edge, and a second corner edge, wherein the straight edge is located between the first corner edge and the second corner edge; The first connecting portion includes a first straight portion and a first corner portion, wherein the first straight portion is adjacent to the straight side and the first corner portion is adjacent to the first corner side; The second connecting portion includes a second straight section and a second corner section, wherein the second straight section is adjacent to the straight side and the second corner section is adjacent to the second corner side.

10. The array substrate of claim 9, wherein, The straight edge, the first straight section, and the second straight section are parallel to each other; The first corner portion is parallel to the first corner side, and the second corner portion is parallel to the second corner side.

11. The array substrate of claim 1, wherein, The signal line includes a main line extending along a first direction and an auxiliary line extending along a second direction, the first direction and the second direction intersect, and multiple main lines and multiple auxiliary lines are interconnected.

12. A display panel, characterized by, Includes the array substrate as described in any one of claims 1 to 11.

13. A display device comprising: Includes the display panel as described in claim 12.

Images