Jfet injection type n-channel sic mosfet device and method of manufacturing the same

Abstract

The application discloses a JFET injection type N-channel SiC MOSFET device and a preparation method thereof. The method comprises the following steps: depositing a first dielectric layer on an epitaxial layer as an ion injection buffer layer; etching a second dielectric layer above a JFET area, performing ion injection on the JFET area after etching; depositing a third dielectric layer, etching the third dielectric layer in a large area and stopping on the second dielectric layer, etching the second dielectric layer, self-aligning to form a P-well injection pattern, and performing P-well injection; depositing a fourth dielectric layer, performing photoetching on the fourth dielectric layer to form an N-type heavily doped source area pattern, and self-aligning to form a channel; etching away the third dielectric layer and the fourth dielectric layer, performing photoetching to form a P-type heavily doped contact area, and performing ion injection; forming a gate dielectric layer through thermal oxidation, depositing polycrystalline silicon as a gate electrode through LPCVD to complete a front structure. The method avoids insufficient photoetching precision, has fewer photoetching steps, is easy to accurately control the channel length, can reduce the JFET resistance, and improves the device performance.

Description

Technical Field

[0001] This invention relates to the field of electronic components technology, and in particular to a JFET-injected N-channel SiC MOSFET device and its fabrication method. Background Technology

[0002] Due to the material advantages of wide-bandgap semiconductor SiC and its compatibility with Si processes, SiC diodes and MOSFETs have gradually become commercialized, and the demand for high breakdown voltage, low on-resistance, and high power has gradually increased.

[0003] For 1 kV planar gate SiC MOSFET devices, the main components of on-resistance are channel resistance, JFET region resistance, and drift region resistance. When the channel length is large, channel resistance becomes a significant factor influencing on-resistance, accounting for more than 50%. Therefore, to achieve high-power devices with low on-resistance, the channel length needs to be shortened. As the channel length decreases, the proportions of JFET region resistance and drift region resistance gradually increase, and when the JFET region width and channel length decrease to a certain extent, the JFET region resistance becomes comparable to the drift region resistance. The doping concentration and thickness of the drift region are limited by the breakdown voltage; therefore, the drift region resistance is determined solely by its material parameters. The factors determining the JFET region resistance include the JFET region width and the JFET region doping concentration. As part of the cell size, the JFET region width has little impact on the on-resistance when the device cell size is limited. Therefore, to reduce the JFET region resistance, the JFET region doping concentration can be increased. There are currently two methods: the first is to epitaxially grow a high-concentration N-type current spreading layer (CSL) on the N-type drift region; the other is to implant the JFET region through ion implantation.

[0004] Furthermore, as the channel length decreases, the dimension of the channel becomes difficult to control precisely due to limitations in photolithography accuracy. Self-aligned processes, however, avoid the use of photolithography to form the implantation pattern through deposition etching, enabling precise control of the channel size down to the sub-micron level. The region between adjacent P-wells within the cell is the JFET region; therefore, ion implantation in the P-wells and the JFET region can be achieved through self-alignment and is compatible with subsequent channel self-alignment processes. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to provide a JFET injection-type N-channel SiCMOSFET device that avoids insufficient photolithography precision, has fewer photolithography steps, is easy to accurately control the channel length, and can reduce JFET resistance and improve device performance.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a JFET injection-type N-channel SiCMOSFET device, characterized in that: it includes an epitaxial layer, a JFET injection region is formed in the middle of the upper part of the epitaxial layer, a P-well region is formed on each side of the JFET injection region, an N+ region is formed on the inner side of the upper surface of each P-well region, a P+ region is formed on the upper surface of the P-well region outside the N+ region, a gate dielectric layer is formed on the upper surface of the epitaxial layer, the left and right sides of the gate dielectric layer extend to the upper surface of the N+ region respectively, a gate is formed on the upper surface of the gate dielectric layer, an interlayer dielectric is formed on the outer side of the gate, the interlayer dielectric covers the gate and the left and right sides of the gate dielectric layer, and the interlayer dielectric contacts the upper surface of the N+ region on the left and right sides, a source is formed on the outer side of the interlayer dielectric, the left and right sides of the source are in contact with the P+ region and the N+ region outside the interlayer dielectric, and a drain is formed on the lower surface of the epitaxial layer.

[0007] A further technical solution is that the epitaxial layer includes an N+ substrate located on the lower side and an N- drift region located on the upper side.

[0008] This invention also discloses a method for fabricating a JFET-injected N-channel SiC MOSFET device, characterized by comprising the following steps: S1: Deposit a first dielectric layer on the epitaxial layer as an ion implantation buffer layer; deposit a second dielectric layer on the surface of the first dielectric layer; etch the second dielectric layer above the JFET region; and perform ion implantation in the JFET region after etching. S2: Deposit a third dielectric layer on the surface of the above device, then etch the third dielectric layer over a large area and terminate at the second dielectric layer, remove the remaining second dielectric layer by wet etching, form a P-well implantation pattern by self-alignment, and perform P-well ion implantation on both sides of the JFET region. S3: Deposit the fourth dielectric layer, perform photolithography on the fourth dielectric layer to form an N-type heavily doped source region pattern, and etch it to form a sidewall on the third dielectric layer above the JFET region. Perform N-type heavily doped source region ion implantation and self-align to form a channel. S4: The third and fourth dielectric layers are etched away, and a P-type heavily doped contact region is formed by photolithography. Ion implantation is then performed. After surface treatment, the gate dielectric layer is formed by thermal oxidation. Polysilicon is deposited by LPCVD to complete the front structure. S5: The electrode metal required for evaporation and sputtering completes the entire JFET injection-type N-channel SiC MOSFET structure.

[0009] A further technical solution is that step S1 specifically includes the following steps: Step S101: Epitaxially grow a substrate with a thickness of 5 μm to 15 μm and a doping concentration of 5 × 10⁻⁶ on an N+ type substrate.15 ~2×10 16 cm -3 The N-type drift region is deposited with a first dielectric layer of 30nm~100nm as an ion implantation buffer layer. Step S102: Deposit a second dielectric layer with a thickness of 0.4 μm to 2 μm on the upper surface of the first dielectric layer. Perform photolithography on the second dielectric layer above the JFET implantation region to form the JFET region pattern. After etching, perform N-type ion implantation in the JFET region. The width of the JFET region is 0.5 μm to 5 μm, and the N-type doping concentration is 5 × 10⁻⁶. 16 ~1×10 17 cm -3 The depth is 0.6~1.2μm.

[0010] A further technical solution is that step S2 specifically includes the following steps: Step S201: A third dielectric layer with a thickness of 0.3 μm to 2 μm is deposited on the upper surface of the device after the process in step S1; Step S202: Etch the third dielectric layer over a large area and terminate at the second dielectric layer, so that the third dielectric layer on the upper side of the JFET implantation region is retained. Then, use wet etching to remove the second dielectric layers on both sides of the third dielectric layer, self-align to form a P-well implantation pattern, and perform P-well ion implantation. The width of the P-well region is 4~7 μm, the P-type doping concentration is 1×10¹⁷~8×10¹⁷ cm⁻³, and the depth is 0.6~1.2 μm.

[0011] A further technical solution is that step S3 specifically includes the following steps: Step S301: Deposit a fourth dielectric layer with a thickness of 0.1 μm to 1 μm on the surface of the device after processing in step S2; Step S302: Perform photolithography on the fourth dielectric layer to form an N-type heavily doped source region pattern. Etch the layer and form sidewalls on both sides of the third dielectric layer above the JFET implantation region. Perform N-type heavily doped source region ion implantation and self-align to form a channel. The channel length is 0.1~1 μm, the N-type heavily doped source region depth is 0.1~0.6 μm, and the N-type doping concentration is 1×10⁻⁶. 19 ~1×10 21 cm -3 .

[0012] A further technical solution is that step S4 specifically includes the following steps: Step S401: Etch away the third and fourth dielectric layers, photolithographically form a P-type heavily doped contact region, and perform ion implantation to a depth of 0.1~0.6 μm with a doping concentration of 1×10⁻⁶. 19 ~1×1021 cm -3 ; Step S402: Etch away the remaining first dielectric layer, and thermally oxidize to grow a gate dielectric layer on the surface of the device; Step S403: Use LPCVD polysilicon process as gate electrode on the upper surface of the gate dielectric layer; Step S404: Deposit an interlayer dielectric on the outside of the gate to isolate the polysilicon gate from the source metal, and form the source metal on the outside of the interlayer dielectric.

[0013] A further technical solution is that step S5 specifically includes the following steps: The electrode metal required for evaporation and sputtering completes the entire JFET injection-type N-channel SiC MOSFET structure.

[0014] The beneficial effects of adopting the above technical solution are as follows: This invention solves the problem of insufficient photolithography precision by using a JFET injection-type N-channel SiC MOSFET device with dual self-alignment of P-well and channel. Furthermore, the dual self-alignment process reduces the number of photolithography steps in device fabrication and makes it easier to accurately control the channel length. At the same time, JFET injection reduces the JFET resistance, all of which improve device performance and enhance the device's trade-off characteristics. Attached Figure Description

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0016] Figure 1 This is a schematic diagram of the structure of the device described in an embodiment of the present invention; Figure 2 This is a flowchart of the method described in the embodiments of the present invention; Figures 3a-3i This is a structural diagram of the fabrication process of the device described in the embodiments of the present invention; Wherein: 1. Epitaxial layer; 1-1. N+ substrate; 1-2. N- drift region; 2. First dielectric layer; 3. Second dielectric layer; 4. Third dielectric layer; 5. Fourth dielectric layer; 6. Gate dielectric layer; 7. Gate electrode; 8. Interlayer dielectric; 9. Source electrode; 10. Drain electrode. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0019] Example 1 like Figure 1 As shown, the present invention discloses a JFET injection-type N-channel SiC MOSFET device, including an epitaxial layer, wherein the epitaxial layer 1 includes an N+ substrate 1-1 located on the lower side and an N- drift region 1-2 located on the upper side. A JFET injection region is formed in the upper middle of the N-drift region 1-2. A P-well region is formed on each side of the JFET injection region. An N+ region is formed on the inner side of the upper surface of each P-well region. A P+ region is formed on the upper surface of the P-well region outside the N+ region. A gate dielectric layer 6 is formed on the upper surface of the epitaxial layer. The left and right sides of the gate dielectric layer 6 extend to the upper surface of the N+ region, respectively. A gate 7 is formed on the upper surface of the gate dielectric layer 6. An interlayer dielectric 8 is formed on the outer side of the gate 7. The interlayer dielectric 8 covers the gate 7 and the left and right sides of the gate dielectric layer 6. The interlayer dielectric 8 is in contact with the upper surfaces of the N+ regions on the left and right sides. A source 9 is formed on the outer side of the interlayer dielectric 8. The left and right sides of the source 9 are in contact with the P+ region and the N+ region outside the interlayer dielectric 8. A drain 10 is formed on the lower surface of the N+ substrate 1-1.

[0020] The device described in this embodiment of the invention includes an N-type drift region, a JFET implantation region, and a planar gate front structure. The N-type drift region is formed epitaxially on an N-type 4H-SiC substrate. The JFET implantation region and the P-well are formed by ion implantation using a self-aligned process. The channel in the planar gate structure is also formed by a second self-aligned process, continuing the P-well self-alignment process. The remaining front structure is fabricated using the same conventional SiC MOSFET fabrication process, thus completing the entire JFET-implanted N-channel SiC MOSFET device. The device structure is as follows: Figure 1 As shown.

[0021] Example 2 Correspondingly, such as Figure 2 As shown in the figure, this invention also discloses a method for fabricating a JFET-injected N-channel SiC MOSFET device, which specifically includes the following steps: S1: A first dielectric layer 2 is deposited on the epitaxial layer 1 as an ion implantation buffer layer. The epitaxial layer includes an N+ substrate 1-1 located on the lower side and an N- drift region 1-2 located on the upper side. The first dielectric layer 2 is located on the upper surface of the N- drift region 1-2. S2: Deposit a second dielectric layer 3 on the surface of the first dielectric layer 2, etch the second dielectric layer 3 above the JFET region, and then perform ion implantation in the JFET region after etching; S3: Deposit a third dielectric layer 4 on the surface of the above device, then etch the third dielectric layer 4 over a large area and terminate at the second dielectric layer 3, remove the remaining second dielectric layer 3 by wet etching, form a P-well implantation pattern by self-alignment, and perform P-well ion implantation on both sides of the JFET region. S4: Deposit the fourth dielectric layer 5 again, perform photolithography on the fourth dielectric layer 5 to form an N-type heavily doped source region pattern, and etch it to form a sidewall on the third dielectric layer 4 above the JFET region. Perform N-type heavily doped source region ion implantation and self-align to form a channel. S5: Etch away the third dielectric layer 4 and the fourth dielectric layer 5, form a P-type heavily doped contact region by photolithography, and perform ion implantation; after surface treatment, thermal oxidation forms the gate dielectric layer 6, and polysilicon is deposited by LPCVD to complete the front structure; S6: The electrode metal required for evaporation and sputtering completes the entire JFET injection-type N-channel SiC MOSFET structure.

[0022] The method involves depositing a first dielectric layer on an N-type epitaxial layer as an ion implantation buffer layer, followed by a second dielectric layer as a JFET implantation mask. After JFET implantation, a third dielectric layer is deposited to fill the etched opening of the second dielectric layer. The third dielectric layer is then etched over a large area, terminating at the second dielectric layer. Wet etching is used to remove the second dielectric layer, and a P-well implantation pattern is formed through self-alignment. Next, a fourth dielectric layer is deposited, and an N-type heavily doped source region pattern is formed using photolithography. The fourth dielectric layer is etched, and sidewalls are formed on the third dielectric layer above the JFET region. A channel is then formed through self-alignment. After the self-alignment process, the relevant dielectric is removed, and subsequent processes are performed to complete the front-side device structure. This fabrication method allows for precise control of the device channel and ion implantation in the JFET region, reducing the JFET region resistance and meeting high-voltage, high-power requirements. This results in a relatively ideal trade-off between the device's conduction and switching characteristics while maintaining high voltage tolerance.

[0023] The above content will be explained in detail below with reference to specific processes. Step S1 specifically includes the following steps: Step S101: Epitaxially grow a substrate with a thickness of 5 μm to 15 μm and a doping concentration of 5 × 10⁻⁶ on an N+ type substrate 1-1. 15 ~2×10 16 cm -3 The N-type drift region 1-2, and a first dielectric layer 2 of 30nm~100nm is deposited on the N-type drift region 1-2 as an ion implantation buffer layer; Step S102: A second dielectric layer 3 with a thickness of 0.4 μm to 2 μm is deposited on the upper surface of the first dielectric layer 2. The second dielectric layer 3 above the JFET implantation region is photolithographically patterned to form the JFET region pattern. After etching, N-type ion implantation is performed on the JFET region. The width of the JFET region is 0.5 μm to 5 μm, and the N-type doping concentration is 5 × 10⁻⁶. 16 ~1×10 17 cm -3 Its depth is 0.6~1.2μm, and its structure is as follows: Figure 3a As shown.

[0024] Step S2 specifically includes the following steps: Step S201: A third dielectric layer 4 with a thickness of 0.3 μm to 2 μm is deposited on the upper surface of the device after the process in step S1, such as... Figure 3b As shown; Step S202: Etch the third dielectric layer 4 over a large area and terminate at the second dielectric layer 3, so that the third dielectric layer 4 above the JFET implantation region is retained, as shown. Figure 3c As shown, the second dielectric layers 3 on both sides of the third dielectric layer 4 are then removed using wet etching. A P-trap implantation pattern is formed through self-alignment, and P-trap ion implantation is performed. The structure is shown below. Figures 3d-3e As shown, the width of the P-well region is 4–7 μm, and the P-type doping concentration is 1 × 10¹⁷–8 × 10¹⁷ cm⁻¹. -3 The depth is 0.6~1.2μm.

[0025] Step S3 specifically includes the following steps: Step S301: A fourth dielectric layer 5 with a thickness of 0.1 μm to 1 μm is deposited on the surface of the device after the treatment in step S2, such as... Figure 3f As shown; Step S302: Perform photolithography on the fourth dielectric layer 5 to form an N-type heavily doped source region pattern, etch, and form sidewalls on the left and right sides of the third dielectric layer 4 above the JFET implantation region, as shown. Figure 3g As shown, N-type heavily doped source region ion implantation is performed, as follows: Figure 3h As shown, a self-aligned channel is formed with a channel length of 0.1–1 μm, an N-type heavily doped source region depth of 0.1–0.6 μm, and an N-type doping concentration of 1 × 10⁻⁶. 19 ~1×10 21 cm -3 .

[0026] Step S4 specifically includes the following steps: Step S401: Etch away the third dielectric layer 4 and the fourth dielectric layer 5, photolithographically form a P-type heavily doped contact region, and perform ion implantation to a depth of 0.1~0.6 μm with a doping concentration of 1×10⁻⁶.19 ~1×10 21 cm -3 ; Step S402: Etch away the remaining first dielectric layer 2, and thermally oxidize to grow the gate dielectric layer 6 on the surface of the device; Step S403: The gate 7 is fabricated on the upper surface of the gate dielectric layer 6 using LPCVD polysilicon process; Step S404: Deposit an interlayer dielectric 8 on the outside of the gate 7 to isolate the polysilicon gate from the source metal, and form a source metal 9 on the outside of the interlayer dielectric.

[0027] Step S5 specifically includes the following steps: The electrode metal required for evaporation and sputtering completes the entire JFET-type N-channel SiC MOSFET structure, such as... Figure 3i As shown.

[0028] This invention solves the problem of insufficient photolithography precision by employing a JFET-injected N-channel SiC MOSFET device with dual self-alignment of P-well and channel. Furthermore, the dual self-alignment process reduces the number of photolithography steps in device fabrication and facilitates precise control of the channel length. At the same time, JFET injection reduces JFET resistance, all of which improve device performance and enhance the device's trade-off characteristics.

Claims

1. A method for fabricating a JFET-injected N-channel SiC MOSFET device, characterized in that... Includes the following steps: S1: A first dielectric layer (2) is deposited on the epitaxial layer (1) as an ion implantation buffer layer; a second dielectric layer (3) is deposited on the surface of the first dielectric layer (2), the second dielectric layer (3) above the JFET region is etched, and ion implantation of the JFET region is performed after etching; S2: Deposit a third dielectric layer (4) on the surface of the above device, then etch the third dielectric layer (4) over a large area and terminate at the second dielectric layer (3), remove the remaining second dielectric layer (3) by wet etching, form a P-well implantation pattern by self-alignment, and perform P-well ion implantation on both sides of the JFET region. S3: Deposit the fourth dielectric layer (5) again, perform photolithography on the fourth dielectric layer (5) to form an N-type heavily doped source region pattern, and form a sidewall on the third dielectric layer (4) above the JFET region, perform N-type heavily doped source region ion implantation, and form a channel by self-alignment; S4: Etch away the third dielectric layer (4) and the fourth dielectric layer (5), form a P-type heavily doped contact region by photolithography, and perform ion implantation; after surface treatment, thermal oxidation forms a gate dielectric layer (6), and polysilicon is deposited by LPCVD to complete the front structure; S5: The electrode metal required for evaporation and sputtering completes the entire JFET injection-type N-channel SiC MOSFET structure; Step S1 specifically includes the following steps: Step S101: Epitaxially grow a substrate with a thickness of 5 μm to 15 μm and a doping concentration of 5 × 10⁻⁶ on an N+ type substrate (1-1). 15 ~2×10 16 cm -3 The N-type drift region (1-2) is deposited with a first dielectric layer (2) of 30nm~100nm as an ion implantation buffer layer. Step S102: A second dielectric layer (3) with a thickness of 0.4 μm to 2 μm is deposited on the upper surface of the first dielectric layer (2). The second dielectric layer (3) above the JFET implantation region is photolithographically patterned to form the JFET region pattern. After etching, N-type ion implantation is performed on the JFET region. The width of the JFET region is 0.5 μm to 5 μm, and the N-type doping concentration is 5 × 10⁻⁶. 16 ~1×10 17 cm -3 The depth is 0.6~1.2μm; Step S2 specifically includes the following steps: Step S201: Deposit a third dielectric layer (4) with a thickness of 0.3 μm to 2 μm on the upper surface of the device after processing in step S1. Step S202: Large-area etching of the third dielectric layer (4) terminates at the second dielectric layer (3), so that the third dielectric layer (4) above the JFET implantation region is retained. Then, wet etching is used to remove the second dielectric layers (3) on both sides of the third dielectric layer (4), and a P-well implantation pattern is formed by self-alignment. P-well ion implantation is performed. The width of the P-well region is 4~7 μm, and the P-type doping concentration is 1×10¹⁷~8×10¹⁷ cm⁻¹. -3 The depth is 0.6~1.2μm; Step S3 specifically includes the following steps: Step S301: Deposit a fourth dielectric layer (5) with a thickness of 0.1 μm to 1 μm on the surface of the device after processing in step S2. Step S302: Photolithography is performed on the fourth dielectric layer (5) to form an N-type heavily doped source region pattern. Etching is then performed, and sidewalls are formed on the left and right sides of the third dielectric layer (4) above the JFET implantation region. N-type heavily doped source region ion implantation is then performed, and a channel is formed through self-alignment. The channel length is 0.1~1 μm, the N-type heavily doped source region depth is 0.1~0.6 μm, and the N-type doping concentration is 1×10⁻⁶. 19 ~1×10 21 cm -3 ; Step S4 specifically includes the following steps: Step S401: Etch away the third dielectric layer (4) and the fourth dielectric layer (5), photolithographically form a P-type heavily doped contact region, and perform ion implantation to a depth of 0.1~0.6 μm with a doping concentration of 1×10⁻⁶. 19 ~1×10 21 cm -3 ; Step S402: Etch away the remaining first dielectric layer (2), and thermally oxidize to grow a gate dielectric layer (6) on the surface of the device. Step S403: The gate (7) is fabricated on the upper surface of the gate dielectric layer (6) using LPCVD polysilicon process. Step S404: Deposit an interlayer dielectric (8) on the outside of the gate (7) to isolate the polysilicon gate from the source metal, and form a source metal (9) on the outside of the interlayer dielectric.

2. The method for fabricating a JFET-injected N-channel SiC MOSFET device as described in claim 1, characterized in that, Step S5 specifically includes the following steps: The electrode metal required for evaporation and sputtering completes the entire JFET injection-type N-channel SiC MOSFET structure.

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