A method for manufacturing a hydrolysis-resistant LED chip

Abstract

The application discloses a kind of anti-hydrolysis LED chip production methods, it is related to light-emitting diode technical field, including the following steps: obtaining an epitaxial wafer, transparent conductive layer, electrode layer and passivation layer are formed in sequence on the epitaxial wafer;With O2 Auxiliary CF4 Gas is carried out to the surface of the passivation layer Modification etching, form hydrophobic passivation layer;The hydrophobic passivation layer is carried out photoetching, etching opening exposes electrode layer.The production method of the application avoids the influence of electrode layer caused by modification etching to avoid subsequent soldering of LED chip bad, also avoid the influence of passivation layer surface hydrophobic modification effect due to the introduction of photoresist after gelatinizing not clean;By using O2 Auxiliary CF4 Gas is carried out to the passivation layer Modification etching, reduce the consumption of CF4 Gas and enhance the hydrophobic effect.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and in particular to a method for manufacturing a hydrolysis-resistant LED chip. Background Technology

[0002] Outdoor LED displays are susceptible to moisture corrosion. Moisture can easily adhere to and penetrate the passivation layer (silicon dioxide film) of the LED chip, causing the LED chip to fail.

[0003] To address the aforementioned problems, Chinese Patent Application No. 202210328384.4 discloses a hydrophobic LED chip and its fabrication method. The method involves obtaining a substrate and forming an epitaxial layer on the substrate; sequentially forming a current blocking layer, a current spreading layer, a metal conductive layer, and a passivation layer on the surface of the epitaxial layer; photolithography, etching, and photoresist removal of the passivation layer to obtain an LED wafer; and bombarding the surface of the LED wafer with SiH4 or CF4 plasma to modify the surface of the LED wafer, forming a hydrophobic passivation layer to prevent moisture adsorption and penetration, thereby improving LED chip leakage current and enhancing reliability.

[0004] However, the patented technical solution involves surface modification after the passivation layer is etched to expose the metal conductive layer. This can cause SiH4 or CF4 plasma to bombard or adhere to the surface of the metal conductive layer, affecting subsequent bonding. Furthermore, the patented technical solution involves surface modification after photolithography, etching, and photoresist removal of the passivation layer. If the photoresist on the passivation layer surface is not completely removed, it can easily affect the hydrophobic modification effect of the passivation layer surface. In addition, the patented technical solution consumes a lot of CF4 and does not maximize the hydrophobic effect of CF4 modification treatment. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies. This invention provides a method for manufacturing a hydrolysis-resistant LED chip. By first modifying and etching the passivation layer before exposing the electrode layer through opening holes, it avoids the subsequent poor bonding of the LED chip caused by the modified etching affecting the electrode layer. It also avoids the impact of incomplete photoresist removal after introduction on the hydrophobic modification effect of the passivation layer surface. By using O2 to assist CF4 gas in modifying and etching the passivation layer, the consumption of CF4 gas is reduced and the hydrophobic effect is enhanced. This invention provides a method for manufacturing a hydrolysis-resistant LED chip, including the following steps:

[0006] An epitaxial wafer is obtained, and a transparent conductive layer, an electrode layer, and a passivation layer are sequentially formed on the epitaxial wafer. The surface of the passivation layer is modified and etched with O2-assisted CF4 gas to form a hydrophobic passivation layer. The hydrophobic passivation layer is then photolithographically etched to create openings to expose the electrode layer.

[0007] Specifically, the modification etching of the passivation layer surface using CF4 gas includes:

[0008] First stage: In a vacuum environment, 5-10 sccm of CF4 gas is introduced for pressure stabilization.

[0009] Second stage: In a vacuum environment, turn on the radio frequency with a power of 80-100W, and introduce 5-10 sccm of CF4 gas to etch the passivation layer.

[0010] Specifically, the temperature conditions in the first stage are 280–320°C, and the temperature conditions in the second stage are 280–320°C.

[0011] Specifically, the pressure of the vacuum environment in the first stage is 80-120 Pa; the pressure of the vacuum environment in the second stage is 80-120 Pa.

[0012] Specifically, the voltage stabilization treatment time in the first stage is 30-60 seconds; the corrosion treatment time in the second stage is 100-120 seconds.

[0013] Specifically, in the first and second stages, a certain amount of O2 is introduced as a dilution gas, and the gas flow ratio CF4:O2 is controlled to be 1:3 to 4.

[0014] Specifically, in the second stage, the CF4 gas is ionized into CF3. + and F - plasma.

[0015] Specifically, a layer is formed on the transparent conductive layer. A thick electrode layer; formed on the electrode layer A thick passivation layer; the electrode layer is completely covered by the passivation layer.

[0016] Specifically, the overall thickness of the hydrophobic passivation layer is in The hydrophobic passivation layer includes a hydrophobic sublayer and a passivation sublayer.

[0017] Specifically, the passivation layer is a silicon dioxide film or a silicon nitride film.

[0018] The method for manufacturing hydrolysis-resistant LED chips provided by this invention has the following advantages:

[0019] First, the passivation layer is modified and etched, and then photolithography and etching are used to open holes to expose the electrode layer. This avoids the CF4 plasma from directly bombarding the electrode layer and causing damage, and also avoids the CF4 plasma from adhering to the surface of the electrode layer. This avoids the modified corrosion from having an adverse effect on the subsequent wire bonding of the LED chip.

[0020] First, the passivation layer is modified and etched, and then photolithography and etching are used to open holes to expose the electrode layer. This also avoids introducing photoresist before modifying and etching the passivation layer, thus avoiding the effect of hydrophobic modification on the surface of the passivation layer due to incomplete removal of the photoresist after its introduction.

[0021] By using O2 to assist CF4 gas in modifying and corroding the passivation layer, the consumption of CF4 gas was reduced and the hydrophobic effect was enhanced. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart of the method for manufacturing a hydrolysis-resistant LED chip in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of the epitaxial wafer obtained in an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of the N-type GaN layer steps formed by MESA etching of the epitaxial wafer in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the structure of an epitaxial wafer patterned with ITO to form a transparent conductive layer in an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of the epitaxial wafer formed by vapor deposition in an embodiment of the present invention;

[0027] Figure 6 This is a schematic diagram of the structure of the epitaxial wafer deposited to form a passivation layer in an embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of the structure of the passivation layer formed by modified corrosion in an embodiment of the present invention to create a hydrophobic passivation layer;

[0029] Figure 8 This is a schematic diagram of the structure of the hydrophobic passivation layer exposing the electrode layer through openings in an embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of the passivation layer surface modification corrosion process in an embodiment of the present invention.

[0031] In the attached figure, 10 is a sapphire substrate; 20 is an N-type GaN layer; 30 is a quantum well light-emitting structure; 40 is a P-type GaN layer; 50 is an N-type GaN layer step; 60 is a transparent conductive layer; 70 is an electrode layer; 80 is a passivation layer; 90 is a hydrophobic passivation layer; 91 is a passivation sublayer; 92 is a hydrophobic sublayer; and 100 is an opening. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Figure 1 A schematic flowchart of a method for fabricating a hydrolysis-resistant LED chip according to an embodiment of the present invention is shown. The method includes the following steps:

[0034] S1. Obtain an epitaxial wafer, and sequentially form a transparent conductive layer, an electrode layer, and a passivation layer on the epitaxial wafer;

[0035] Figure 2 This diagram illustrates the structure of an epitaxial wafer obtained in an embodiment of the present invention. The epitaxial wafer includes a sapphire substrate 10 (500–600 μm thick), an N-type GaN layer 20, a quantum well light-emitting structure 30, and a P-type GaN layer 40. Specifically, an N-type GaN layer step 50 is formed on the epitaxial wafer by MESA etching. Figure 3 This diagram illustrates the structure of an epitaxial wafer formed with N-type GaN layer steps via MESA etching in an embodiment of the present invention; a transparent conductive layer 60 is formed on the P-type GaN layer 40 by ITO patterning. Figure 4 This diagram illustrates the structure of an epitaxial wafer patterned with ITO to form a transparent conductive layer in an embodiment of the present invention; the electrode layer 70 is formed by vapor deposition. Figure 5 This diagram illustrates the structure of an electrode layer formed by vapor deposition on an epitaxial wafer in an embodiment of the present invention. The thickness of the electrode layer 70 is [missing information]. It is composed of one or more elements such as chromium, titanium, ruthenium, aluminum, nickel, platinum, and gold. The electrode layer 70 includes a P-type electrode located on the transparent conductive layer 60 and an N-type electrode located on the N-type GaN layer step 50.

[0036] A passivation layer 80 is deposited along the surface of the transparent conductive layer 60, the electrode layer 70, and the N-type GaN layer step 50, completely covering the electrode layer 70. Figure 6 This diagram illustrates the structure of a passivation layer formed by deposition on an epitaxial wafer in an embodiment of the present invention; the thickness of the passivation layer 80 should be appropriate. The thickness is just right. If it is too thick, the stress between the film layers will be too great, making it easy to break and weakening the light emission effect of the chip. If it is too thin, it will be easy to leak current and affect the electrical performance of the chip. Here, the passivation layer 80 has a suitable thickness and completely covers the electrode layer 70, protecting the electrode layer 70 from being bombarded or attached by CF4 plasma during the subsequent modification and etching process, thereby avoiding affecting the quality of subsequent wire bonding.

[0037] The temperature during the deposition of passivation layer 80 is controlled to be 280-320℃. If the temperature is below 280℃, the passivation layer 80 formed will have poor density, and water vapor can easily pass through the passivation layer 80 to reach the chip surface, causing hydrolytic corrosion. If the temperature is above 320℃, the Al in the electrode layer 70 will be abnormally active, which will cause the electrode layer 70 to blister.

[0038] The passivation layer 80 can be a silicon dioxide film or a silicon nitride film, which can react with CF4 gas to form a hydrophobic film on the film surface.

[0039] S2. Use O2-assisted CF4 gas to modify and etch the surface of the passivation layer to form a hydrophobic passivation layer.

[0040] The passivation layer 80 deposition process and the passivation layer 80 modification and etching process are carried out in the same equipment cavity, which can keep the obtained hydrophobic passivation layer 90 clean and ensure that it has a good hydrophobic effect.

[0041] Figure 7 This diagram illustrates the structure of a hydrophobic passivation layer formed by modified etching in an embodiment of the present invention, where the overall thickness of the hydrophobic passivation layer 90 is controlled within a certain range. The hydrophobic passivation layer 90 includes a hydrophobic sublayer 92 and a passivation sublayer 91.

[0042] Modified corrosion is carried out in an enhanced plasma vapor deposition (IPD) system and mainly consists of two stages:

[0043] The first stage is the pressure stabilization stage. In a vacuum environment with a pressure of 80-120 Pa and a temperature of 280-320℃, 5-10 sccm of CF4 gas is introduced into the equipment cavity for pressure stabilization. At the same time, a certain amount of O2 is introduced as a dilution gas. The ratio of CF4 to O2 is controlled to be 1:3-4. The radio frequency is not turned on in the first stage, and the CF4 gas does not ionize.

[0044] The first stage of pressure stabilization needs to be maintained for 30-60 seconds. This is to purge the gas used in the previous passivation layer deposition process and to allow the pressure, temperature, and atmosphere conditions inside the equipment cavity to transition to the next stage, preventing instability in the process curve due to changes in process parameters. If the pressure stabilization time is too short, the gas used in the previous passivation layer 80 deposition process will not be expelled in time, affecting the subsequent modification and corrosion effect of passivation layer 80. If the pressure stabilization time is too long, it will be time-consuming, affecting production efficiency and wasting resources. The first stage of pressure stabilization improves the stability of the process, making the hydrophobic passivation layer 90 obtained by subsequent modification and corrosion more stable, denser, and with better hydrophobic effect.

[0045] The second stage is the modification and corrosion stage. In a vacuum environment with a pressure of 80–120 Pa and a temperature of 280–320 °C, the passivation layer is etched with CF4 gas at a flow rate of 5–10 sccm for 100–120 seconds. Simultaneously, a certain amount of O2 is introduced as a dilution gas, and the gas flow ratio of CF4:O2 is controlled to be 1:3–4. In this second stage, radio frequency (RF) is activated to ionize the CF4 gas into CF3. + and F - Plasma; radio frequency power is 80-100W. If the power is too low, the corrosion rate will be too slow; if the power is too high, the corrosion rate will be too fast, making it difficult to control the corrosion reaction process. In the second stage of corrosion treatment, under O2 and certain temperature and pressure conditions, the reaction rate is precisely controlled, resulting in low consumption of CF4 gas and excellent hydrophobicity of the obtained hydrophobic passivation layer 90.

[0046] When the passivation layer 80 is a silicon dioxide film layer Figure 9 This diagram illustrates the process of surface modification corrosion of passivation layer 80 in an embodiment of the present invention. The hydroxyl groups on the surface of passivation layer 80 are coated with F... - Plasma substitution transforms Si-O bonds into Si-F bonds, thereby changing the surface of the passivation layer 80 from hydrophilic to hydrophobic.

[0047] The pressure of the vacuum environment should be controlled at 80-120 Pa. If the pressure is too low, the CF4 gas will not be fully ionized, and if the pressure is too high, the reaction products will not be discharged in time.

[0048] To stabilize the vacuum environment pressure at 80–120 Pa, a certain flow rate of gas is required. If only CF4 gas is introduced, the demand for CF4 gas will be high, and the modification corrosion rate will be relatively fast, making precise control difficult. Introducing a certain amount of O2 as a diluent gas, specifically controlling the gas flow ratio of CF4:O2 to 1:3–4, fills the equipment cavity with O2 to stabilize the pressure. This reduces the proportion of CF4 gas, preventing excessive CF4 gas from causing an excessively fast modification corrosion rate, thus facilitating stable control of the modification corrosion rate. Furthermore, O2, when exposed to radio frequency, will form O2... - Plasma, in this environment, O - Plasma can cause CF4 gas to release more F - Plasma, CF4+O - →COF2+2F - It relatively improved F - The proportion of plasma allows for more efficient utilization of CF4 gas, thereby reducing the consumption of CF4 gas.

[0049] The temperature for modified corrosion is controlled at 280–320℃. This temperature range is consistent with the temperature of the passivation layer 80 deposition process. This allows for surface corrosion modification of the passivation layer 80 immediately after deposition, enabling rapid connection between processes and improving efficiency. Maintaining a constant temperature range helps to keep the structure of the passivation layer 80 stable and also helps to keep the process curve stable, thus improving product quality.

[0050] When etching the passivation layer 80 with CF4 gas, a flow rate of 5–10 sccm is suitable for controlling the corrosion rate. If the CF4 gas flow rate is too low, the surface modification of the passivation layer 80 will be uneven, and the formed hydrophobic sublayer 92 will not completely cover the surface of the passivation sublayer 91, affecting the hydrophobic effect. If the CF4 gas flow rate is too high, the corrosion rate will be too fast and difficult to control, potentially severely corroding the passivation layer 80, resulting in an uneven hydrophobic passivation layer 90, or even a local thickness less than [a certain value]. It is prone to leakage, which affects the electrical performance of the chip;

[0051] Furthermore, the etching time of the CF4 gas to passivate layer 80 needs to be controlled to 100-120 seconds. If the etching time is too short, the hydrophobic sublayer 92 formed will be incomplete and the hydrophobic effect will be poor; if the etching time is too long, the passivation layer 80 will be severely corroded, affecting the electrical performance of the chip.

[0052] S3. Perform photolithography and etching on the hydrophobic passivation layer to create openings and expose the electrode layer. Figure 8 This diagram illustrates a structure in an embodiment of the present invention where the hydrophobic passivation layer exposes the electrode layer through openings.

[0053] Photolithography refers to the process of using an exposure system to precisely transfer a pattern pre-made on a photomask to a photoresist layer pre-coated on the surface of a wafer, according to the required positions. Photolithography includes three sub-processes: photoresist coating, exposure, and development.

[0054] Photoresist coating involves applying positive photoresist to the wafer to create a photoresist layer with a thickness of 2–4 μm. If the photoresist layer is too thin, it will fail to protect the wafer surface during etching, resulting in the etching of some areas that do not need to be etched. If the photoresist layer is too thick, it will be difficult to develop completely, which will also reduce the resolution and increase the cost.

[0055] After exposure, the photoresist at the corresponding location is modified by passing it through a photomask, allowing the pattern to be preserved during the subsequent development process. The exposure amount is 40-80 mJ. If the exposure amount is too low, the photoresist may not be fully exposed, and the pattern will not be preserved after the subsequent development process. If the exposure amount is too high, the photoresist will become difficult to remove due to changes in its chemical properties, leaving residue in the subsequent photoresist removal process.

[0056] Development preserves the desired pattern in the photoresist layer. The development time and exposure amount can be matched to ensure that the pattern size matches the design value.

[0057] Etching, using a plasma-coupled etching machine, mainly using O2 and CF4 gases, etches the silicon dioxide that is not covered and protected by photoresist, thereby exposing the electrode layer;

[0058] In this embodiment of the invention, the main processes of photolithography and etching are as follows:

[0059] In the photolithography process, positive photoresist is dropped onto the surface of the hydrophobic passivation layer 90 on the wafer. A photoresist layer with a thickness of 2.8–3.4 μm is formed by controlling the rotation speed (1500–2000 r / min). Then, a mask with a specific pattern is placed between the UV exposure machine and the photoresist layer on the wafer surface. The UV exposure machine is turned on for exposure at a dose of 50–70 mJ, causing the photoresist to denature under UV irradiation. After exposure, baking (conditions: temperature 100–120℃, time 60–100 s) reduces the standing wave effect formed during exposure and effectively solidifies the denatured photoresist. Finally, a developer is dropped onto the photoresist layer on the wafer surface, and development takes 50–80 s. The resulting photoresist layer on the wafer surface forms a pattern identical to that of the mask.

[0060] During the etching process, the wafer with the positive photoresist pattern is placed into an inductively coupled plasma etching machine, and a certain amount of O2 and CF4 gas is introduced. The ratio of CF4 to O2 gas is 1:5 to 10. The upper RF power is 60 to 180W, the lower RF power is 200 to 800W, and the equipment cavity pressure is maintained at 5 to 10 mtor.

[0061] If the proportion of CF4 gas is small, the reaction rate is slow; if the proportion of CF4 gas is too high, the reaction rate is difficult to control.

[0062] If the up-frequency power is too low, it will result in a small amount of plasma being generated and a slow reaction; if the up-frequency power is too high, it will generate too much plasma, which will inhibit the reaction rate.

[0063] If the lower RF power is too low, it will affect the energy of the plasma bombardment, resulting in a weaker physical bombardment capability and a slower response; if the lower RF power is too high, the plasma etching process of silicon dioxide will damage the surface of the Au electrode, leading to a higher chip voltage.

[0064] If the chamber pressure is set too low, i.e. the vacuum is too low, the equipment may not be able to perform its function, or the vacuuming time may be too long, affecting efficiency. If the chamber pressure is set too high, i.e. the vacuum is too high, there will be gaseous impurities such as ions, atoms, and molecules in the chamber, which will affect the dry etching effect.

[0065] By a certain amount of O2, the etching of the silicon dioxide in the passivation layer can be accelerated. In addition, since the etching is carried out under oxygen-rich conditions, it is equivalent to diluting the CF4 gas, which can avoid the reaction between CF4 and the surface of the Au electrode layer.

[0066] First, the passivation layer 80 is subjected to modified etching, and then holes are opened to expose the electrode layer 70, which avoids the direct bombardment of the electrode layer 70 by CF4 plasma and causes damage to it. It also avoids the attachment of CF4 plasma on the surface layer of the electrode layer 70, thereby avoiding the adverse effects of modified etching on the subsequent wire bonding of the LED chip.

[0067] After the modified etching of the passivation layer 80, photolithography and etching are carried out to open holes to expose the electrode layer 70, which also avoids the influence of incomplete photoresist removal on the hydrophobic modification effect of the surface of the passivation layer 80 after the introduction of the photoresist.

[0068] Finally, the packaged LED chip is subjected to hydrolysis resistance verification under the conditions of 85°C and 85% RH. Essentially, it is to detect whether water vapor can penetrate through the passivation layer 80 into the chip interior for electrochemical corrosion under high temperature and high humidity conditions, causing the LED chip to fail. If there is no failure, it is judged as qualified. The qualification rate of the LED chip before modified etching is 60%, and the qualification rate of the hydrolysis-resistant LED chip after modified etching is 95%. The qualification rate has increased by 35%, and the hydrolysis resistance ability has been significantly enhanced.

[0069] In the manufacturing method of a hydrolysis-resistant LED chip provided by the embodiment of the present invention, the passivation layer 80 is first subjected to modified etching, and then photolithography and etching are carried out to open holes to expose the electrode layer 70, which avoids the direct bombardment of the electrode layer 70 by CF4 plasma and causes damage to it. It also avoids the attachment of CF4 plasma on the surface layer of the electrode layer 70, thereby avoiding the adverse effects of modified etching on the subsequent wire bonding of the LED chip.

[0070] The passivation layer 80 is first subjected to modified etching, and then photolithography and etching are carried out to open holes to expose the electrode layer 70, which also avoids the introduction of the photoresist before the modified etching of the passivation layer 80, thereby avoiding the influence of incomplete photoresist removal on the hydrophobic modification effect of the surface of the passivation layer 80 after the introduction of the photoresist.

[0071] By using O2 to assist the CF4 gas to carry out modified etching on the passivation layer 80, after the radio frequency is turned on, the proportion of F - plasma is relatively increased under the action of O2, and the consumption of CF4 gas is greatly reduced, which is more environmentally friendly.

[0072] Moreover, the deposition process of the passivation layer 80 and the modified etching process of the passivation layer 80 are carried out in the same equipment cavity, and the transition between processes is stable. It can not only keep the obtained hydrophobic passivation layer 90 clean and ensure its good hydrophobic effect, but also improve the stability of the process. The formed hydrophobic passivation layer 90 has good compactness and better hydrolysis resistance ability.

[0073] The above provides a detailed description of a method for manufacturing a hydrolysis-resistant LED chip according to embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for manufacturing a hydrolysis-resistant LED chip, characterized in that, Includes the following steps: An epitaxial wafer is obtained, and a transparent conductive layer, an electrode layer, and a passivation layer that completely encloses the electrode layer are sequentially formed on the epitaxial wafer; the passivation layer is a silicon dioxide film or a silicon nitride film. With the electrode layer completely covered by the passivation layer, the surface of the passivation layer is modified and etched by O2-assisted CF4 gas to form a hydrophobic passivation layer. The hydrophobic passivation layer is photolithographically and etched to create openings, thereby exposing the electrode layer; The step of modifying and etching the surface of the passivation layer with O2-assisted CF4 gas includes: First stage: In a vacuum environment, 5-10 sccm of CF4 gas is introduced for pressure stabilization. Second stage: In a vacuum environment, turn on the radio frequency with a power of 80-100W and introduce 5-10 sccm of CF4 gas to etch the passivation layer. In the first and second stages, a certain amount of O2 is introduced as a dilution gas, and the gas flow ratio CF4:O2 is controlled to be 1:3 to 4.

2. The method for manufacturing a hydrolysis-resistant LED chip according to claim 1, characterized in that, The temperature conditions for the first stage are 280–320°C, and the temperature conditions for the second stage are 280–320°C.

3. The method for manufacturing a hydrolysis-resistant LED chip according to claim 1, characterized in that, The pressure of the vacuum environment in the first stage is 80-120 Pa; the pressure of the vacuum environment in the second stage is 80-120 Pa.

4. The method for manufacturing a hydrolysis-resistant LED chip according to claim 1, characterized in that, The voltage stabilization treatment time in the first stage is 30-60 seconds; the corrosion treatment time in the second stage is 100-120 seconds.

5. The method for manufacturing a hydrolysis-resistant LED chip according to claim 1, characterized in that, In the second stage, the CF4 gas is ionized into CF3. + and F - plasma.

6. The method for manufacturing a hydrolysis-resistant LED chip according to claim 1, characterized in that, An electrode layer with a thickness of 10,000 to 20,000 Å is formed on the transparent conductive layer; a passivation layer with a thickness of 600 to 2,600 Å is formed on the electrode layer.

7. The method for manufacturing a hydrolysis-resistant LED chip according to claim 1, characterized in that, The overall thickness of the hydrophobic passivation layer is 600–2600 Å; the hydrophobic passivation layer includes a hydrophobic sublayer and a passivation sublayer.

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