A general PLL clock control circuit and SOC chip

Abstract

The application provides a general PLL clock control circuit and an SOC chip, the circuit comprises: a PLL unit; an output end of a PLL parameter control unit is connected to the PLL unit and is configured to update clock configuration parameters of the PLL unit in real time; an input end of a clock control unit is connected to an external crystal oscillator and an output end of the PLL unit and is configured to output a control signal for selecting a clock frequency based on software or hardware selection configuration information; an input end of a clock switching unit is connected to the external crystal oscillator, the output end of the PLL unit and an output end of the clock control unit and is configured to select an output clock frequency according to the control signal output by the clock control unit; and an input end of a clock generation unit is connected to an output end of the clock switching unit and is configured to receive the clock frequency output by the clock switching unit and reduce the clock frequency output by the clock switching unit to a clock frequency required by other functional modules. By using the scheme of the application, the chip cost can be reduced and the complex clock requirements of the chip can be met.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a general-purpose PLL clock control circuit and a SOC chip. Background Technology

[0002] The rapid development of integrated circuits has continuously improved people's lives, and the ever-increasing social demand has driven the development of integrated circuits towards System-on-a-Chip (SoC). An integrated system contains many functional modules: microprocessors, memory, analog IP, digital IP, etc. In order to realize complex system functions, these functional sub-modules often need to operate under certain timing conditions, requiring clock circuits to provide an effective clock for each sub-module.

[0003] PLL (Phase-Locked Loop)-based clocking technology is characterized by its simple structure, good jitter performance, wide frequency range, and ease of implementation, leading to its widespread application and development. It has also become one of the main choices for clock generation sources in system integrated circuits. With the continuous development of integrated circuits and the increasing size of System-on-a-Chip (SoC) chips, the number of clocks associated with a single SoC clock network may reach hundreds or even thousands. This results in a corresponding increase in the number of PLLs, with frequency distributions ranging from a few kHz to several GHz. Consequently, circuit designs need to consider a wider range of clock usage scenarios.

[0004] In this context, using the dispersed clock circuit modules in existing technologies easily leads to problems such as complex clock control and chaotic clock relationships. Therefore, how to reasonably and reliably control different clock frequencies using a universal clock network circuit, and generate the clock signals required by sub-modules according to different clock controls, is a crucial issue in SOC chip design. As chip project design cycles become shorter and chip design costs increase, it is becoming increasingly important for system-on-a-chip (SoC) designs with millions or even hundreds of millions of gates to be based on iterative designs of previous chips. In existing designs, if user requirements change, circuit redesign and custom-designed SoC chips are necessary, resulting in high costs. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a universal PLL clock control circuit and SOC chip. By using the technical solution of this invention, chip costs can be reduced and the complex clock requirements of the chip can be met.

[0006] To achieve the above objectives, one aspect of the present invention provides a general PLL clock control circuit, comprising:

[0007] The PLL unit is configured to receive the low-frequency signal provided by the general-purpose clock unit output by the external crystal oscillator and multiply the low-frequency system clock to the high-frequency clock required by the chip.

[0008] The PLL parameter control unit has its output connected to the PLL unit and is configured to update the clock configuration parameters of the PLL unit in real time.

[0009] The clock control unit has its input connected to the external crystal oscillator and the output of the PLL unit, and is configured to output a control signal to select the clock frequency based on software or hardware selection configuration information.

[0010] The clock switching unit has its input connected to an external crystal oscillator, the output of the PLL unit, and the output of the clock control unit. The clock switching unit is configured to select the output clock frequency according to the control signal output by the clock control unit.

[0011] The clock generation unit has its input connected to the output of the clock switching unit. The clock generation unit is configured to receive the clock frequency output by the clock switching unit and downclock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules.

[0012] According to one embodiment of the present invention, the clock control unit includes:

[0013] The first inverter has its input connected to the output of the programmable memory.

[0014] The first AND gate has its first input connected to the output of the first inverter and its second input connected to the software-configured bypass PLL signal.

[0015] The first flip-flop has its D pin connected to the output of the first AND gate, and its CLK pin connected to an external crystal oscillator.

[0016] The second flip-flop has its D pin connected to the Q pin of the first flip-flop, and its CLK pin connected to an external crystal oscillator.

[0017] The second inverter has its input connected to the Q pin of the second flip-flop;

[0018] The third flip-flop has its D pin connected to the Lock output of the PLL unit, and its CLK pin connected to an external crystal oscillator.

[0019] The fourth flip-flop has its D pin connected to the Q pin of the third flip-flop, and its CLK pin connected to an external crystal oscillator.

[0020] The delay circuit has its input connected to the Q pin of the fourth flip-flop.

[0021] The selector has its first channel connected to the software frequency selection configuration data, its second channel connected to the output of the delay circuit, and its data gating control terminal connected to the clock switching configuration data.

[0022] The second AND gate has its first input connected to the output of the second inverter, its second input connected to the output of the selector, and its output connected to the clock switching unit.

[0023] According to one embodiment of the present invention, the PLL parameter control unit includes:

[0024] The selector's first channel is connected to the PLL enable configuration data, the data strobe control terminal is connected to the PLL enable selection data, and the output terminal is connected to the PLLEN pin of the PLL unit.

[0025] The trigger's D pin is connected to the PLL parameter configuration data, and its Q pin is connected to the PLL unit's parameter configuration port.

[0026] The counter's output is connected to the second channel of the selector.

[0027] According to one embodiment of the present invention, the clock switching unit includes:

[0028] The clock selector has its first channel connected to an external crystal oscillator, its second channel connected to the first output of the PLL unit, its data gating control terminal connected to the output of the clock control unit, and its output terminal connected to the clock generation unit.

[0029] According to one embodiment of the present invention, the clock generation unit includes:

[0030] The buffer's input is connected to the output of the clock switching unit, and its output is connected to other functional modules.

[0031] The first clock gate has its input connected to the output of the clock switching unit, and its output connected to other functional modules.

[0032] The frequency divider and the second clock gate are connected. The input of the frequency divider is connected to the output of the clock switching unit, and the output is connected to the input of the second clock gate. The output of the second clock gate is connected to other functional modules.

[0033] In another aspect, embodiments of the present invention also provide a SOC chip, the SOC chip including a general-purpose PLL clock control circuit, the general-purpose PLL clock control circuit including:

[0034] The PLL unit is configured to receive the low-frequency signal provided by the general-purpose clock unit output by the external crystal oscillator and multiply the low-frequency system clock to the high-frequency clock required by the chip.

[0035] The PLL parameter control unit has its output connected to the PLL unit and is configured to update the clock configuration parameters of the PLL unit in real time.

[0036] The clock control unit has its input connected to the external crystal oscillator and the output of the PLL unit, and is configured to output a control signal to select the clock frequency based on software or hardware selection configuration information.

[0037] The clock switching unit has its input connected to an external crystal oscillator, the output of the PLL unit, and the output of the clock control unit. The clock switching unit is configured to select the output clock frequency according to the control signal output by the clock control unit.

[0038] The clock generation unit has its input connected to the output of the clock switching unit. The clock generation unit is configured to receive the clock frequency output by the clock switching unit and downclock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules.

[0039] According to one embodiment of the present invention, the clock control unit includes:

[0040] The first inverter has its input connected to the output of the programmable memory.

[0041] The first AND gate has its first input connected to the output of the first inverter and its second input connected to the software-configured bypass PLL signal.

[0042] The first flip-flop has its D pin connected to the output of the first AND gate, and its CLK pin connected to an external crystal oscillator.

[0043] The second flip-flop has its D pin connected to the Q pin of the first flip-flop, and its CLK pin connected to an external crystal oscillator.

[0044] The second inverter has its input connected to the Q pin of the second flip-flop;

[0045] The third flip-flop has its D pin connected to the Lock output of the PLL unit, and its CLK pin connected to an external crystal oscillator.

[0046] The fourth flip-flop has its D pin connected to the Q pin of the third flip-flop, and its CLK pin connected to an external crystal oscillator.

[0047] The delay circuit has its input connected to the Q pin of the fourth flip-flop.

[0048] The selector has its first channel connected to the software frequency selection configuration data, its second channel connected to the output of the delay circuit, and its data gating control terminal connected to the clock switching configuration data.

[0049] The second AND gate has its first input connected to the output of the second inverter, its second input connected to the output of the selector, and its output connected to the clock switching unit.

[0050] According to one embodiment of the present invention, the PLL parameter control unit includes:

[0051] The selector's first channel is connected to the PLL enable configuration data, the data strobe control terminal is connected to the PLL enable selection data, and the output terminal is connected to the PLLEN pin of the PLL unit.

[0052] The trigger's D pin is connected to the PLL parameter configuration data, and its Q pin is connected to the PLL unit's parameter configuration port.

[0053] The counter's output is connected to the second channel of the selector.

[0054] According to one embodiment of the present invention, the clock switching unit includes:

[0055] The clock selector has its first channel connected to an external crystal oscillator, its second channel connected to the first output of the PLL unit, its data gating control terminal connected to the output of the clock control unit, and its output terminal connected to the clock generation unit.

[0056] According to one embodiment of the present invention, the clock generation unit includes:

[0057] The buffer's input is connected to the output of the clock switching unit, and its output is connected to other functional modules.

[0058] The first clock gate has its input connected to the output of the clock switching unit, and its output connected to other functional modules.

[0059] The frequency divider and the second clock gate are connected. The input of the frequency divider is connected to the output of the clock switching unit, and the output is connected to the input of the second clock gate. The output of the second clock gate is connected to other functional modules.

[0060] The present invention has the following beneficial technical effects: The general PLL clock control circuit provided in the embodiments of the present invention, by setting up a PLL unit, the PLL unit is configured to receive a low-frequency signal provided by a general clock unit output by an external crystal oscillator, and multiply the low-frequency system clock to the high-frequency clock required by the chip; a PLL parameter control unit, the output terminal of which is connected to the PLL unit and configured to update the clock configuration parameters of the PLL unit in real time; a clock control unit, the input terminal of which is connected to the external crystal oscillator and the output terminal of the PLL unit, and configured to output a control signal to select the clock frequency based on software or hardware selection configuration information; a clock switching unit, the input terminal of which is connected to the external crystal oscillator, the output terminal of the PLL unit and the output terminal of the clock control unit, and configured to select the output clock frequency according to the control signal output by the clock control unit; and a clock generation unit, the input terminal of which is connected to the output terminal of the clock switching unit, and configured to receive the clock frequency output by the clock switching unit and down-clock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules, can reduce chip costs and meet the complex clock requirements of the chip. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a schematic diagram of a general PLL clock control circuit according to an embodiment of the present invention;

[0063] Figure 2 A schematic diagram of a clock control unit according to an embodiment of the present invention;

[0064] Figure 3 This is a schematic diagram of a PLL parameter control unit and a PLL unit according to an embodiment of the present invention;

[0065] Figure 4 This is a schematic diagram of a clock switching unit and a clock generating unit according to an embodiment of the present invention;

[0066] Figure 5 This is a schematic diagram of a clock network circuit in a SOC chip according to an embodiment of the present invention;

[0067] Figure 6 This is a schematic diagram illustrating the components in various circuit diagrams according to an embodiment of the present invention. Detailed Implementation

[0068] The following describes embodiments of the present disclosure. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various alternative forms. The drawings are not necessarily drawn to scale; certain functions may be exaggerated or minimized to show details of particular components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to use the invention in various ways. As will be understood by those skilled in the art, various features shown and described with reference to any of the drawings may be combined with features shown in one or more other drawings to produce embodiments not explicitly shown or described. The combinations of features shown provide representative embodiments for typical applications. However, various combinations and modifications of features consistent with the teachings of this disclosure may be desirable for certain particular applications or implementations.

[0069] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a general PLL clock control circuit. Figure 1 The diagram shown is a schematic of the circuit.

[0070] like Figure 1 As shown, the circuit may include:

[0071] The PLL unit is configured to receive the low-frequency signal provided by the general-purpose clock unit output by the external crystal oscillator and multiply the low-frequency system clock to the high-frequency clock required by the chip.

[0072] The PLL parameter control unit has its output connected to the PLL unit and is configured to update the clock configuration parameters of the PLL unit in real time.

[0073] The clock control unit has its input connected to the external crystal oscillator and the output of the PLL unit, and is configured to output a control signal to select the clock frequency based on software or hardware selection configuration information.

[0074] The clock switching unit has its input connected to an external crystal oscillator, the output of the PLL unit, and the output of the clock control unit. The clock switching unit is configured to select the output clock frequency according to the control signal output by the clock control unit.

[0075] The clock generation unit has its input connected to the output of the clock switching unit. The clock generation unit is configured to receive the clock frequency output by the clock switching unit and downclock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules.

[0076] An external crystal oscillator provides a low-frequency signal to the general-purpose clock unit. The PLL unit multiplies the low-frequency system clock to the high-frequency clock required by the chip. The clock control unit is responsible for switching between software and hardware. The clock switching unit outputs the clock frequency according to the selection of the clock control unit. The PLL parameter control unit supports real-time updating of the clock configuration parameters of the PLL unit through software during chip operation, and supports dynamic adjustment of the output clock frequency. The clock generation unit will reasonably allocate the clock, down-clock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules in the chip, and manage the clock supply of each functional module of the chip. When a sub-module is not working, it can be turned off to reduce the power consumption caused by the chip clock flipping.

[0077] The technical solution of this invention can reduce chip costs and meet the complex clock requirements of chips.

[0078] In a preferred embodiment of the present invention, such as Figure 2 As shown, the clock control unit includes:

[0079] The first inverter has its input connected to the output of the programmable memory.

[0080] The first AND gate has its first input connected to the output of the first inverter and its second input connected to the software-configured bypass PLL signal.

[0081] The first flip-flop has its D pin connected to the output of the first AND gate, and its CLK pin connected to an external crystal oscillator.

[0082] The second flip-flop has its D pin connected to the Q pin of the first flip-flop, and its CLK pin connected to an external crystal oscillator.

[0083] The second inverter has its input connected to the Q pin of the second flip-flop.

[0084] The third flip-flop has its D pin connected to the Lock output of the PLL unit, and its CLK pin connected to an external crystal oscillator.

[0085] The fourth flip-flop has its D pin connected to the Q pin of the third flip-flop, and its CLK pin connected to an external crystal oscillator.

[0086] The delay circuit has its input connected to the Q pin of the fourth flip-flop.

[0087] The selector has its first channel connected to the software frequency selection configuration data, its second channel connected to the output of the delay circuit, and its data gating control terminal connected to the clock switching configuration data.

[0088] The second AND gate has its first input connected to the output of the second inverter, its second input connected to the output of the selector, and its output connected to the clock switching unit. The programmable memory is EFUSE, which stores chip information such as the chip's power supply voltage, version number, production date, and key configuration information. The clock control unit performs a series of inversions and AND operations based on the PLL control information programmed into EFUSE and the software-configured bypass PLL signal to obtain a hardware bypass PLL clock control path. The names of the components in the circuit diagram are as follows: Figure 6 As shown.

[0089] Since the PLL unit output clock and the clock control unit belong to different clock domains, cross-clock domain synchronization is required, which is accomplished through two-stage flip-flops. Additionally, a delay circuit is needed for the PLL lock signal to ensure a clean path clock for the PLL unit. The selector here is a 2-to-1 MUX, used to switch between the software frequency and the hardware PLL lock output, primarily to complete the software and hardware clock switching process upon chip power-on.

[0090] In a preferred embodiment of the present invention, such as Figure 3 As shown, the PLL parameter control unit includes:

[0091] The selector's first channel is connected to the PLL enable configuration data, the data strobe control terminal is connected to the PLL enable selection data, and the output terminal is connected to the PLLEN pin of the PLL unit.

[0092] The trigger's D pin is connected to the PLL parameter configuration data, and its Q pin is connected to the PLL unit's parameter configuration port, which includes BYPASS, REFDIV, FBDIV, POSTDIV1, and POSTDIV2 ports.

[0093] The counter's output is connected to the second channel of the selector.

[0094] The PLL parameter control unit includes a counter and a parameter configuration module. The PLL parameter configuration module latches the PLL parameter configuration information generated by the register through a flip-flop and sends it to the PLL unit for use. Since the chip clock must remain stable and reliable, this parameter configuration information is only affected by the chip's power-on reset. For the PLL to function properly, certain timing requirements must be met; that is, after the PLL power supply stabilizes, the PLL enable signal should remain low for at least a certain period. Therefore, after a system reset, counting is performed under the system clock. When the counter meets the PLL timing requirements, the PLL enable signal is set, opening the PLL unit. Alternatively, software configuration can be performed based on the PLL enable configuration selection signal. This allows the PLL to be opened via software in case of a hardware-enabled PLL failure, ensuring normal chip operation. Simultaneously, the PLL unit provides a lock signal to the clock control unit. During chip operation, if the PLL frequency division parameters need to be updated, two corresponding control flows are proposed based on the aforementioned hardware and software methods; the hardware control flow is the default here. For example, if you want to change the operating frequency of a submodule, you can first switch the system clock to a low-frequency system clock according to the clock switching procedure, then update the PLL parameters, wait for its output clock signal to stabilize at the new frequency, and then switch back to the PLL's output clock. Because a glitch-free clock selector is used, the submodule can still operate normally during the switching process.

[0095] The software update process is as follows: 1) Configure the reset register to generate a PLL reset; 2) Configure the register to select the PLL enable signal (PLLEN) to be controlled by software; 3) Configure the reset register to release the PLL reset; 4) Change the default parameters of the PLL (REFDIV, FBDIV, POSTDIV1, POSTDIV2); 5) Control the timing conditions of PLLEN by software; 6) Query the lock status after processing by the clock control unit to confirm that the software update of the PLL clock is complete.

[0096] The hardware update process is as follows: 1) Configure the reset register to generate a PLL reset (at this time, PLLEN is automatically pulled low); 2) Change the default parameters of the PLL; 3) Configure the reset register to release the PLL reset; 4) Use the hardware counter of the PLL parameter control unit to ensure the timing requirements of PLL power-on; 5) Query the lock status after processing by the clock control unit to confirm that the hardware update of the PLL clock is complete.

[0097] In a preferred embodiment of the present invention, such as Figure 4 As shown, the clock switching unit includes:

[0098] The clock selector has its first channel connected to an external crystal oscillator, its second channel connected to the first output of the PLL unit, its data gating control terminal connected to the output of the clock control unit, and its output terminal connected to the clock generation unit.

[0099] In a preferred embodiment of the present invention, such as Figure 4 As shown, the clock generation unit includes:

[0100] The buffer's input is connected to the output of the clock switching unit, and its output is connected to other functional modules.

[0101] The first clock gate has its input connected to the output of the clock switching unit, and its output connected to other functional modules.

[0102] The frequency divider and the second clock gate are connected. The input of the frequency divider is connected to the output of the clock switching unit, and the output is connected to the input of the second clock gate. The output of the second clock gate is connected to other functional modules.

[0103] Based on the clock information type of each submodule in the SOC chip, the clock generation unit can be divided into the following three paths: Clock buffers increase clock driving capability, can be used to buffer and debouncing input clock signals, and facilitate the definition of clock constraints. Clock dividers generate frequency-divided signals based on the master clock, which will be used to generate the functional clocks of subsequent submodules. Clock gating uses gating units from the standard unit library; when a submodule is not in operation, its clock can be turned off.

[0104] The clock switching unit (clk_switch) employs glitch-free clock switching technology. Directly using multiplexers or selection logic can lead to clock glitches, which are dangerous for the entire system. This invention's clock switching unit receives the clock switching output signal, adopts the basic principle of a glitch-free clock selector, and extends it to support two clock inputs. During clock switching, the gating switch for the second clock is turned on only after the first clock input is turned off, ensuring no glitches occur during the switching process and completing the dynamic switching between the system clock and the PLL clock. The clock generation unit rationally allocates the clock, downclocking the clock frequency output by the clock switching unit to the frequency required by other functional modules in the chip, and managing the clock supply to each functional module. When a submodule is not in operation, it can be shut down, reducing the power consumption caused by the chip's clock flipping.

[0105] Based on the aforementioned clock circuit structure, a clock switching procedure for chip power-on is proposed. This clock switching unit involves four switching modes, supporting both software and hardware switching, with software clock switching as the default. Switching is achieved by determining whether the clock switching signal output from the clock control unit is 0 or 1. 0 represents switching to the chip system clock, while 1 represents switching to the PLL clock, as detailed below:

[0106] 1. The clock switching unit is controlled by the hardware bypass method of the clock control unit. The output of the clock switching configuration signal is 0. At this time, the chip works at the system clock. This method is to prevent the system from malfunctioning due to clock abnormality after PLL lock.

[0107] 2. If hardware clock switching is required, the clock switching configuration signal of the clock control unit needs to be configured to 1. In this case, you can only wait for the PLL lock to go high and for the delay circuit of the clock control unit to process the signal before the hardware automatically switches the clock to the PLL clock.

[0108] 3. During the power-on startup process, before the PLL is in the locked state, the clock switching signal of the clock control unit is controlled by the software selection input terminal 0 of the 2-to-1 MUX. Therefore, the clock selection signal of the clock switching unit is 0, which makes the output clock transmitted to the clock generation unit the system clock provided by the external crystal oscillator.

[0109] 4. During the power-on startup process, after the PLL is in a locked state, by configuring the software frequency selection signal of the clock control unit to 1 and the clock selection signal of the clock switching unit to 1, the output clock transmitted to the clock generation unit is the PLL clock provided by the PLL, and the system will switch to work under the PLL output clock.

[0110] In a preferred embodiment of the present invention, a method for implementing and integrating a universal clock circuit is also proposed. Considering that SOC design requires manual integration of the universal clock circuit unit, errors in integration connections inevitably lead to logic function failures. Based on the universality of this design scheme, an automated method will be used for implementation.

[0111] To address the issue of automatic code generation, the top-level module automatically connects the necessary sub-modules (PLL unit, clock control unit, PLL parameter control unit, clock switching unit, and clock generation unit). For each sub-module, the necessary functional code needs to be automatically generated based on different customized functional requirements, and then called and connected by the top-level module.

[0112] Initially, pre-defined clock requirement templates and clock code templates from each standard cell library need to be prepared. Based on the specific requirements of the actual chip, different clock parameter definitions are selected from the templates. A generation script reads the template, extracting required connections, frequencies, clock domains, switches, and whether software control is needed. A database is built based on this information, and different clock sub-modules are selected from the database for design use. An integration script integrates all sub-modules to generate a top-level module for a general-purpose clock cell. Finally, based on this database, all clock design code is generated.

[0113] Reading a predefined clock requirement template using a scripting language (such as Python) and converting it into clock design code in SystemVerilog (SV) format has the following advantages:

[0114] 1) Ensure consistency: For clock network circuits of different SOC chips, once the design requirements change, the clock requirement table can be modified directly to update the corresponding design code. No manual code modification is required, which realizes the need for rapid project iteration.

[0115] 2) It has strong scalability and is easy to maintain. In the later stages, it can not only automatically generate design code, but also collect clock constraint information from the database to provide clock constraint information to the backend and test case information to provide verification.

[0116] In a preferred embodiment of the present invention, a circuit for the clock network in a SOC chip is also provided, such as... Figure 5 As shown, it includes multiple general-purpose clock units and register modules. The general-purpose clock units receive an external crystal oscillator clock input. The number of general-purpose clock units is selected according to the chip's clock requirements, and they output signals such as low-frequency clock, high-frequency CPU clock, and variable-frequency DDR clock. The register modules configure the clock units via the AHB bus in software, enabling real-time adjustment of the chip's clock frequency, resulting in a versatile and flexible design.

[0117] The clock circuit of this invention adopts an automated general design, supports hardware and software collaborative operation, selectable and configurable output clock frequency, and adds auxiliary means to discover design problems in advance. While ensuring design quality, it reduces chip cost and meets the complex clock requirements of chips.

[0118] Based on the above objectives, a second aspect of the embodiments of the present invention provides a System-on-a-Chip (SOC) chip, which includes a general-purpose PLL clock control circuit. The general-purpose PLL clock control circuit includes:

[0119] The PLL unit is configured to receive the low-frequency signal provided by the general-purpose clock unit output by the external crystal oscillator and multiply the low-frequency system clock to the high-frequency clock required by the chip.

[0120] The PLL parameter control unit has its output connected to the PLL unit and is configured to update the clock configuration parameters of the PLL unit in real time.

[0121] The clock control unit has its input connected to the external crystal oscillator and the output of the PLL unit, and is configured to output a control signal to select the clock frequency based on software or hardware selection configuration information.

[0122] The clock switching unit has its input connected to an external crystal oscillator, the output of the PLL unit, and the output of the clock control unit. The clock switching unit is configured to select the output clock frequency according to the control signal output by the clock control unit.

[0123] The clock generation unit has its input connected to the output of the clock switching unit. The clock generation unit is configured to receive the clock frequency output by the clock switching unit and downclock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules.

[0124] In a preferred embodiment of the present invention, the clock control unit includes:

[0125] The first inverter has its input connected to the output of the programmable memory.

[0126] The first AND gate has its first input connected to the output of the first inverter and its second input connected to the bypass PLL signal configured in the software.

[0127] The first flip-flop has its D pin connected to the output of the first AND gate, and its CLK pin connected to an external crystal oscillator.

[0128] The second flip-flop has its D pin connected to the Q pin of the first flip-flop, and its CLK pin connected to an external crystal oscillator.

[0129] The second inverter has its input connected to the Q pin of the second flip-flop;

[0130] The third flip-flop has its D pin connected to the Lock output of the PLL unit, and its CLK pin connected to an external crystal oscillator.

[0131] The fourth flip-flop has its D pin connected to the Q pin of the third flip-flop, and its CLK pin connected to an external crystal oscillator.

[0132] The delay circuit has its input connected to the Q pin of the fourth flip-flop.

[0133] The selector has its first channel connected to the software frequency selection configuration data, its second channel connected to the output of the delay circuit, and its data gating control terminal connected to the clock switching configuration data.

[0134] The second AND gate has its first input connected to the output of the second inverter, its second input connected to the output of the selector, and its output connected to the clock switching unit.

[0135] In a preferred embodiment of the present invention, the PLL parameter control unit includes:

[0136] The selector's first channel is connected to the PLL enable configuration data, the data strobe control terminal is connected to the PLL enable selection data, and the output terminal is connected to the PLLEN pin of the PLL unit.

[0137] The trigger's D pin is connected to the PLL parameter configuration data, and its Q pin is connected to the PLL unit's parameter configuration port.

[0138] The counter's output is connected to the second channel of the selector.

[0139] In a preferred embodiment of the present invention, the clock switching unit includes:

[0140] The clock selector has its first channel connected to an external crystal oscillator, its second channel connected to the first output of the PLL unit, its data gating control terminal connected to the output of the clock control unit, and its output terminal connected to the clock generation unit.

[0141] In a preferred embodiment of the present invention, the clock generation unit includes:

[0142] The buffer's input is connected to the output of the clock switching unit, and its output is connected to other functional modules.

[0143] The first clock gate has its input connected to the output of the clock switching unit, and its output connected to other functional modules.

[0144] The frequency divider and the second clock gate are connected. The input of the frequency divider is connected to the output of the clock switching unit, and the output is connected to the input of the second clock gate. The output of the second clock gate is connected to other functional modules.

[0145] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0146] The above embodiments, especially any "preferred" embodiments, are possible examples of implementation and are presented merely for the purpose of clearly understanding the principles of the invention. Many variations and modifications can be made to the above embodiments without departing from the spirit and principles of the technology described herein. All modifications are intended to be included within the scope of this disclosure and protected by the appended claims.

Claims

1. A universal PLL clock control circuit, characterized in that, include: The PLL unit is configured to receive a low-frequency signal from a general-purpose clock unit output by an external crystal oscillator and multiply the low-frequency system clock to the high-frequency clock required by the chip. The PLL parameter control unit has its output connected to the PLL unit and is configured to update the clock configuration parameters of the PLL unit in real time. A clock control unit, the input of which is connected to the output of an external crystal oscillator and a PLL unit, and configured to output a control signal to select the clock frequency based on software or hardware selection configuration information; The clock switching unit has its input connected to an external crystal oscillator, the output of the PLL unit, and the output of the clock control unit. The clock switching unit is configured to select the output clock frequency according to the control signal output by the clock control unit. The clock generation unit has its input connected to the output of the clock switching unit. The clock generation unit is configured to receive the clock frequency output by the clock switching unit and downclock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules. The clock control unit includes: The first inverter has its input connected to the output of the programmable memory. The first AND gate has its first input connected to the output of the first inverter and its second input connected to the software-configured bypass PLL signal. The first flip-flop has its D pin connected to the output of the first AND gate, and its CLK pin connected to an external crystal oscillator. The second flip-flop has its D pin connected to the Q pin of the first flip-flop, and its CLK pin connected to an external crystal oscillator. The second inverter has its input connected to the Q pin of the second flip-flop; The third flip-flop has its D pin connected to the Lock output of the PLL unit, and its CLK pin connected to an external crystal oscillator. The fourth flip-flop has its D pin connected to the Q pin of the third flip-flop, and its CLK pin connected to an external crystal oscillator. The delay circuit has its input connected to the Q pin of the fourth flip-flop. The selector has its first channel connected to the software frequency selection configuration data, its second channel connected to the output of the delay circuit, and its data gating control terminal connected to the clock switching configuration data. The second AND gate has its first input connected to the output of the second inverter, its second input connected to the output of the selector, and its output connected to the clock switching unit.

2. The general-purpose PLL clock control circuit according to claim 1, characterized in that, The PLL parameter control unit includes: The selector's first channel is connected to the PLL enable configuration data, the data strobe control terminal is connected to the PLL enable selection data, and the output terminal is connected to the PLLEN pin of the PLL unit. The trigger's D pin is connected to the PLL parameter configuration data, and its Q pin is connected to the PLL unit's parameter configuration port. The counter's output is connected to the second channel of the selector.

3. The general-purpose PLL clock control circuit according to claim 1, characterized in that, The clock switching unit includes: The clock selector has its first channel connected to an external crystal oscillator, its second channel connected to the first output of the PLL unit, its data gating control terminal connected to the output of the clock control unit, and its output terminal connected to the clock generation unit.

4. The general-purpose PLL clock control circuit according to claim 1, characterized in that, The clock generation unit includes: The buffer's input is connected to the output of the clock switching unit, and its output is connected to other functional modules. The first clock gate has its input connected to the output of the clock switching unit, and its output connected to other functional modules. The frequency divider and the second clock gate are connected. The input of the frequency divider is connected to the output of the clock switching unit, and the output is connected to the input of the second clock gate. The output of the second clock gate is connected to other functional modules.

5. A SOC chip, characterized in that, The SOC chip includes a general-purpose PLL clock control circuit, which includes: The PLL unit is configured to receive a low-frequency signal from a general-purpose clock unit output by an external crystal oscillator and multiply the low-frequency system clock to the high-frequency clock required by the chip. The PLL parameter control unit has its output connected to the PLL unit and is configured to update the clock configuration parameters of the PLL unit in real time. A clock control unit, the input of which is connected to the output of an external crystal oscillator and a PLL unit, and configured to output a control signal to select the clock frequency based on software or hardware selection configuration information; The clock switching unit has its input connected to an external crystal oscillator, the output of the PLL unit, and the output of the clock control unit. The clock switching unit is configured to select the output clock frequency according to the control signal output by the clock control unit. The clock generation unit has its input connected to the output of the clock switching unit. The clock generation unit is configured to receive the clock frequency output by the clock switching unit and downclock the clock frequency output by the clock switching unit to the clock frequency required by other functional modules. The clock control unit includes: The first inverter has its input connected to the output of the programmable memory. The first AND gate has its first input connected to the output of the first inverter and its second input connected to the software-configured bypass PLL signal. The first flip-flop has its D pin connected to the output of the first AND gate, and its CLK pin connected to an external crystal oscillator. The second flip-flop has its D pin connected to the Q pin of the first flip-flop, and its CLK pin connected to an external crystal oscillator. The second inverter has its input connected to the Q pin of the second flip-flop; The third flip-flop has its D pin connected to the Lock output of the PLL unit, and its CLK pin connected to an external crystal oscillator. The fourth flip-flop has its D pin connected to the Q pin of the third flip-flop, and its CLK pin connected to an external crystal oscillator. The delay circuit has its input connected to the Q pin of the fourth flip-flop. The selector has its first channel connected to the software frequency selection configuration data, its second channel connected to the output of the delay circuit, and its data gating control terminal connected to the clock switching configuration data. The second AND gate has its first input connected to the output of the second inverter, its second input connected to the output of the selector, and its output connected to the clock switching unit.

6. The SOC chip according to claim 5, characterized in that, The PLL parameter control unit includes: The selector's first channel is connected to the PLL enable configuration data, the data strobe control terminal is connected to the PLL enable selection data, and the output terminal is connected to the PLLEN pin of the PLL unit. The trigger's D pin is connected to the PLL parameter configuration data, and its Q pin is connected to the PLL unit's parameter configuration port. The counter's output is connected to the second channel of the selector.

7. The SOC chip according to claim 5, characterized in that, The clock switching unit includes: The clock selector has its first channel connected to an external crystal oscillator, its second channel connected to the first output of the PLL unit, its data gating control terminal connected to the output of the clock control unit, and its output terminal connected to the clock generation unit.

8. The SOC chip according to claim 5, characterized in that, The clock generation unit includes: The buffer's input is connected to the output of the clock switching unit, and its output is connected to other functional modules. The first clock gate has its input connected to the output of the clock switching unit, and its output connected to other functional modules. The frequency divider and the second clock gate are connected. The input of the frequency divider is connected to the output of the clock switching unit, and the output is connected to the input of the second clock gate. The output of the second clock gate is connected to other functional modules.

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