Devices containing contacts in the peripheral area and methods for forming them

Abstract

This application relates to an apparatus and a method for forming contacts in a peripheral region. An apparatus and method for manufacturing a semiconductor memory device are described. An example method includes: forming a first interconnect; forming a first dielectric layer over the first interconnect in a peripheral region; removing a portion of the first dielectric layer to form a first opening through the first dielectric layer in the peripheral region, thereby exposing the first interconnect at the bottom of the first opening; depositing a first conductive material in the peripheral region to form a first contact portion in the first opening; forming a second dielectric layer in the peripheral region on the first dielectric layer and the first contact portion; removing a second portion of the second dielectric layer to form a second opening through the second dielectric layer, thereby exposing the first contact portion at the bottom of the second opening; depositing a second conductive material to form a plurality of second contact portions in the corresponding first opening; and forming a second interconnect on the second contact portions.

Description

Technical Field

[0001] This application relates to semiconductor devices, and more specifically, to devices and methods of forming contacts in a peripheral area. Background Technology

[0002] High data reliability, high-speed memory access, reduced power consumption, and smaller chip size are desirable characteristics of semiconductor memories. To reduce chip size, the distance between signal lines has become increasingly shorter. Semiconductor devices may also include contacts (e.g., vias) in their peripheral regions. Contacts transmit signals between transistors on the substrate and signal lines in the upper layers of the semiconductor device. To form contacts, openings are created by etching the layers above the substrate. Recently, contacts have become increasingly taller due to the increased height of semiconductor devices. Semiconductor devices typically contain several layers of conductive, semiconducting, and dielectric materials to form the various circuits within the device. Due to the greater height of the multilayers of conductive, semiconducting, and dielectric materials, openings (e.g., openings for vias, contacts, etc.) have become increasingly deep. This increasing depth presents challenges for opening formation (e.g., etching). For example, deeper etching results in openings with larger cross-sections. Therefore, adjacent contacts with larger cross-sections in the opening tend to become undesirable short circuits. Summary of the Invention

[0003] One aspect of this disclosure provides an apparatus comprising: a plurality of first interconnects extending along a first direction; a plurality of second interconnects located above the plurality of first interconnects, the plurality of second interconnects extending along a second direction different from the first direction; a plurality of contacts, wherein each of the plurality of contacts includes: a first portion coupled to a corresponding first interconnect among the plurality of first interconnects; and a second portion located on the first portion, the second portion being coupled to a corresponding second interconnect among the plurality of second interconnects, wherein the first portion has a first cross-section comprising: a first length along the first direction; and a first width perpendicular to the first length and less than the first length, and wherein the second portion has a second cross-section comprising: a second length along the second direction; and a second width perpendicular to the second length and less than the second length.

[0004] Another aspect of this disclosure provides a method comprising: forming a plurality of first interconnects; forming one or more first dielectric layers in a peripheral region over the plurality of first interconnects; removing a first portion of the one or more first dielectric layers to form a plurality of first openings through the one or more first dielectric layers in the peripheral region, thereby exposing the plurality of first interconnects at the bottom of the plurality of first openings; depositing a first conductive material in the peripheral region to form a plurality of first contact portions in the plurality of first openings; forming one or more second dielectric layers in the peripheral region on the one or more first dielectric layers and the plurality of first contact portions; removing a second portion of the one or more second dielectric layers to form a plurality of second openings through the one or more second dielectric layers, thereby exposing the plurality of first contact portions at the bottom of the plurality of second openings; depositing a second conductive material to form a plurality of second contact portions in the plurality of corresponding first openings; and forming a plurality of second interconnects on the plurality of second contact portions.

[0005] Another aspect of this disclosure provides an apparatus comprising: a first interconnect extending along a first direction; a second interconnect positioned above the first interconnect, the second interconnect extending along a second direction different from the first direction; and a contact coupled between the first interconnect and the second interconnect, wherein the contact comprises: a first portion on the first interconnect, wherein the first portion has an elliptical cross-section having a major diameter along the first direction; and a second portion between the first portion and the second interconnect, wherein the second portion has an elliptical cross-section having a major diameter along the second direction. Attached Figure Description

[0006] Figure 1 This is a top view of a portion of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2A It is included according to the embodiments of this disclosure. Figure 1 A vertical cross-sectional view of the structure of another part of the semiconductor device.

[0008] Figure 2B According to embodiments of this disclosure Figure 2A Another vertical cross-sectional view of the structure of the other part of the semiconductor device.

[0009] Figure 3A This is a vertical cross-sectional view of a portion of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3B According to embodiments of this disclosure Figure 3AAnother vertical cross-sectional view of the structure of the other part of the semiconductor device.

[0011] Figure 4A This is a vertical cross-sectional view of a portion of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4B According to embodiments of this disclosure Figure 4A Another vertical cross-sectional view of the structure of the portion of the semiconductor device.

[0013] Figure 5A This is a vertical cross-sectional view of a portion of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5B According to embodiments of this disclosure Figure 5A Another vertical cross-sectional view of the structure of the portion of the semiconductor device.

[0015] Figure 5C The pattern is based on an embodiment of this disclosure.

[0016] Figure 6A This is a vertical cross-sectional view of a portion of the structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 6B According to embodiments of this disclosure Figure 6A Another vertical cross-sectional view of the structure of the portion of the semiconductor device.

[0018] Figure 6C This is a schematic diagram of a mask according to an embodiment of the present disclosure. Detailed Implementation

[0019] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects of embodiments in which this disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0020] Figure 1 This is a top view of the structure of a portion 100 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2A This is a vertical cross-sectional view of the structure of another part 200 of part 100 including a semiconductor device according to an embodiment of the present disclosure. Figure 2BThis is another vertical cross-sectional view of the structure of another portion 200 of portion 100 including a semiconductor device according to an embodiment of the present disclosure.

[0021] In some embodiments, Figure 1 A portion 100 of the semiconductor device 200 may be included in a peripheral region 204 of the semiconductor device 100. The semiconductor device 100 may include a substrate 110. In the following description, the location “above” means the substrate 110 is oriented relative to the bottom of the semiconductor device 100. In some embodiments, the substrate 110 may extend in a plane that may include a direction 112 and a direction 114 other than direction 112. In some embodiments, direction 114 may be perpendicular to direction 112. It can be viewed from above, i.e., along a direction perpendicular to directions 112 and 114. Figure 1 . Figure 2A The vertical cross-sectional view of part 200 is a view along segment V1 in direction 112. Figure 2B Another vertical cross-sectional view of part 200 is a view along segment V2 in direction 114.

[0022] Semiconductor device 100 may include interconnects 102a-102d disposed above substrate 110. In some embodiments, interconnects 102a-102d may extend parallel to each other in direction 112. In some embodiments, interconnects 102a-102d may comprise a conductive material, such as copper or aluminum. In some embodiments, interconnects 102a-102d may be formed in a wiring layer (e.g., metal layer 1). Semiconductor device 100 may include interconnects 104a-104d above interconnects 102a-102d. In some embodiments, interconnects 104a-104d may extend parallel to each other in direction 114 perpendicular to direction 112. In some embodiments, interconnects 104a-104d may comprise a conductive material, such as copper or aluminum. In some embodiments, interconnects 104a-104d may be formed in another wiring layer (e.g., metal layer 2).

[0023] Semiconductor device 100 may include contacts coupling interconnects 102a-102d to interconnects 104a-104d. Each of the contacts may include a conductive portion extending through a respective layer between interconnects 102a-102d and interconnects 104a-104d. For example, Figure 2A and 2B The diagram shows contacts 214a-214h. Contacts 214a-214h each comprise contact portions 106a-106g and contact portions 108a-108g.

[0024] Each of contact portions 106a-106g can be mounted on one of interconnects 102a-102d. For example, contact portions 106a, 106c, and 106e can be mounted on interconnect 102a. Contact portion 106g can be mounted on interconnect 102b. Contact portions 106b, 106d, and 106f can be mounted on interconnect 102c. Contact portion 106h can be mounted on interconnect 102d.

[0025] like Figure 1 As shown in the top view, each of the contact portions 106a-106h has a cross-section. The cross-section of each of the contact portions 106a-106h has a length along direction 112 and a width DL1 less than the length along direction 114. In some embodiments, the cross-section may have an elliptical shape. The cross-section may have a major diameter DL1 along direction 112 and a minor diameter along direction 114. In some embodiments, the minor diameter is less than the sum of the width W1 of each of the interconnects 102a-102d and the spacing Int1 between adjacent interconnects in the interconnects 102a-102d. In some embodiments, the minor diameter of the cross-section may be less than the width W1 of each of the interconnects 102a-102d. Therefore, adjacent interconnects of the interconnects 102a-102d may not be short-circuited to each other through the contact portions 106a-106h.

[0026] Each of contact portions 108a-108g can be disposed on a corresponding contact portion of contact portions 106a-106g. Interconnectors 104a-104d can be disposed on one or more corresponding contact portions of contact portions 108a-108g. For example, interconnector 104a can be disposed on contact portions 108a and 108b. Interconnector 104b can be disposed on contact portions 108c and 108d. Interconnector 104c can be disposed on contact portions 108e and 108f. Interconnector 104d can be disposed on contact portions 108g and 108h.

[0027] like Figure 1As shown in the top view, each of the contact portions 108a-108h has a cross-section. The cross-section of each of the contact portions 108a-108h has a length DL2 along direction 114 and a width less than the length along direction 112. In some embodiments, the cross-section of each of the contact portions 108a-108h may have an elliptical shape. The cross-section of each of the contact portions 108a-108h may have a major diameter DL2 along direction 114 and a minor diameter along direction 112. In some embodiments, the minor diameter is less than the sum of the width W2 of each of the interconnects 104a-104d and the spacing Int2 between adjacent interconnects in the interconnects 104a-104d. In some embodiments, the minor diameter of the cross-section of each of the contact portions 108a-108h may be less than the width W2 of each of the interconnects 104a-104d. Adjacent contact portions, such as contact portions 108a and 108c, 108c and 108e, 108b and 108d, 108d and 108f, can be spaced apart from each other. Therefore, adjacent interconnects in interconnects 104a-104d can be connected to each other without short-circuiting through contact portions 108a-108h.

[0028] Contact portions 106a-106h and 108a-108h may comprise a conductive material. In some embodiments, contact portions 106a-106h and 108a-108h may comprise the same conductive material. In some embodiments, the conductive material may be tungsten. In some embodiments, contact portions 106a-106h and 108a-108h may comprise different conductive materials.

[0029] In some embodiments, the semiconductor device 100 may include, for example, [missing information - likely a specific component or feature]. Figure 2A The memory device (e.g., dynamic random access memory (DRAM)) in memory cell 206.

[0030] Semiconductor device 100 may additionally include memory array region 202. Memory array region 202 may include memory cells 206. Each memory cell of memory cell 206 may include a transistor (e.g., transistor 212a or transistor 212b) on substrate 110. In some embodiments, the transistor (e.g., transistor 212a or transistor 212b) may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) in DRAM.

[0031] Each memory cell of memory cell 206 may include a capacitor on the corresponding transistor (e.g., transistor 212a or transistor 212b respectively). Figure 2AThe capacitors are either capacitor 210a or capacitor 210b. Each capacitor (e.g., capacitor 210a or capacitor 210b) can store a value representing a binary data bit. In some embodiments, each capacitor (e.g., capacitor 210a or capacitor 210b) may have a pillar structure extending in a direction perpendicular to the substrate 110. Each capacitor (e.g., capacitor 210a or capacitor 210b) may include a lower capacitor electrode at one end of the pillar structure and an upper capacitor electrode at the other end of the pillar structure. The lower capacitor electrode of each capacitor (e.g., capacitor 210a or capacitor 210b) may be coupled to a corresponding transistor (e.g., transistor 212a or transistor 212b, respectively).

[0032] Semiconductor device 100 may include a power supply line 208 that provides a power supply voltage. The power supply line 208 may contain a conductive material, such as tungsten. The power supply line 208 may include a portion located in a memory array region 202 and another portion located in a peripheral region 204. The portion of the power supply line 208 located in the memory array region 202 is disposed above and coupled to the upper capacitor electrode of the memory cell 206. The other portion of the power supply line 208 located in the peripheral region 204 is disposed below interconnects 102a-102d. In some embodiments, interconnects 102a-102d may be disposed on the other portion of the power supply line 208 located in the peripheral region 204. Contact portions 106a-106h may be disposed on interconnects 102a-102d. In some embodiments, the height of the portion of the power supply line 208 located in the memory array region 202 may be substantially the same as the height of the contact portions 106a-106h.

[0033] Semiconductor device 100 may include a dielectric layer 216 over a portion of power supply line 208 located in peripheral region 204. In some embodiments, the height of the top surface of the dielectric layer may be the same as the height of the portion of power supply line 208 located in memory array region 202. Contact portions 106a-106h may be disposed in dielectric layer 216. Semiconductor device 100 may include dielectric layer 218. Dielectric layer 218 may be disposed across memory array region 202 and peripheral region 204. A portion of dielectric layer 218 located in peripheral region 204 may be disposed on dielectric layer 216 and contact portions 106a-106h. A portion of dielectric layer 218 located in memory array region 202 may be disposed on the portion of power supply line 208 located in memory array region 202. In some embodiments, contact portions 108a-108h may be disposed in dielectric layer 218. In some embodiments, dielectric layers 216 and 218 may comprise silicon oxide (SiO2).

[0034] The following describes the forming apparatus, for example, according to reference. Figures 3A to 6B The method of the semiconductor device 100 in the embodiment. The dimensions and aspect ratios of each part in each figure need not be consistent with the dimensions and aspect ratios of the actual semiconductor device.

[0035] Figure 3A This is a vertical cross-sectional view of a schematic structure of a portion 300 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3B This is another vertical cross-sectional view of a schematic structure of a portion 300 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3A The vertical cross-sectional view of part 300 is a view along direction 114. Figure 3B Another vertical cross-sectional view of portion 300 is a view along direction 112. In some embodiments, portion 300 of the semiconductor device 100 may be used for manufacturing Figure 2A and 2B Part 200 of the intermediate structure.

[0036] Figure 3A A portion 300 of the semiconductor device 100 includes a memory array region 202 and a peripheral region 204. In some embodiments, the semiconductor device 100 may include a substrate 110 spanning the memory array region 202 and the peripheral region 204. In some embodiments, the substrate 110 may include, for example, monocrystalline silicon.

[0037] In some embodiments, portion 300 may include Figure 3A Memory cell 206 in memory array region 202. As previously referenced. Figure 2A As described, each memory cell in memory cell 206 may include a transistor on substrate 110 (e.g., Figure 2A Transistor 212a or transistor 212b) and the corresponding capacitor on the transistor (e.g., Figure 2A (Capacitor 210a or capacitor 210b). In some embodiments, conductive material may be deposited in the memory array region 202 and the peripheral region 204. The conductive material may be, for example, tungsten. The conductive material may be deposited on the substrate 110 in the peripheral region 204 and above the capacitors (including capacitors 210a and 210b) of the memory cells 206 in the memory array region 202. Power supply lines 208 may be formed of the deposited conductive material.

[0038] In some embodiments, conductive material may be deposited simultaneously in the memory array region 202 and the peripheral region 204. Therefore, power supply lines 208 may be formed on the substrate 110 in the peripheral region 204 and above the capacitors of the memory cells 206 in the memory array region 202 to couple to the upper capacitor electrodes of the memory cells 206.

[0039] Figure 4AThis is a vertical cross-sectional view of a schematic structure of a portion 400 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4B This is another vertical cross-sectional view of a schematic structure of a portion 400 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4A The vertical cross-sectional view of part 400 is a view along direction 114. Figure 4B Another vertical cross-sectional view of portion 400 is a view along direction 112. In some embodiments, portion 400 of the semiconductor device 100 may be for manufacturing Figure 2A and 2B Part 200 of the intermediate structure.

[0040] Part 400 includes a memory array region 202 and a peripheral region 204 of the semiconductor device 100. A dielectric layer 402 may be disposed on a power supply line 208 in the peripheral region 204. In some embodiments, the dielectric layer 402 may comprise a dielectric material. The dielectric material may comprise, for example, silicon oxide (SiO2). The dielectric material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, interconnects 102a-102d may be formed in the dielectric layer 402 in the peripheral region 204. In some embodiments, a conductive material may be deposited and excess portions of the conductive material surrounding the interconnects 102a-102d may be removed. A dielectric material may then be deposited to form the dielectric layer 402. The dielectric layer 402 may cover the interconnects 102a-102d, and the top portion of the dielectric layer 402 may be removed to expose the top surface of the interconnects 102a-102d. In other embodiments, a dielectric layer 402 may be formed and openings may be provided in the dielectric layer 402 to form interconnects 102a-102d in the openings. Thus, in some embodiments, interconnects 102a-102d may be positioned above power supply lines 208 in the peripheral region 204.

[0041] Conductive materials can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD). The conductive material can be, for example, copper or aluminum. Figure 4A As shown, adjacent interconnects 102a-102d can be spaced apart by a distance. Interconnects 102a-102d can be insulated from each other through dielectric layer 402. Figure 4B As shown, interconnects 102a-102d may extend over power supply line 208 in peripheral region 204, which may extend in direction 112.

[0042] Figure 5A This is a vertical cross-sectional view of a schematic structure of a portion 500 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 5BThis is another vertical cross-sectional view of a schematic structure of a portion 500 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 5A The vertical cross-sectional view of part 500 is a view along direction 114. Figure 5B Another vertical cross-sectional view of portion 500 is a view along direction 112. In some embodiments, portion 500 of the semiconductor device 100 may be used for manufacturing Figure 2A and 2B Part 200 of the intermediate structure.

[0043] One or more dielectric layers 502 may be formed over the interconnects 102a-102d and the dielectric layer 402. In some embodiments, Figure 2A and 2B The dielectric layer 216 may include a dielectric layer 402 and one or more dielectric layers 502. In some embodiments, the one or more dielectric layers 502 may include a dielectric material. The dielectric material may include, for example, silicon oxide (SiO2). The dielectric material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, the height 508 of the top surface of the one or more dielectric layers 502 from the substrate 110 and the height 510 of the power supply line 208 from the substrate 110 in the memory array region 202 may be substantially the same.

[0044] One or more portions of dielectric layer 502 may be removed to form an opening. In some embodiments, the removal of one or more portions of dielectric layer 502 to form an opening may be performed by photo-patterning a mask and dry etching a pattern in the mask. Figure 5C This is a schematic diagram of a mask 506 according to an embodiment of the present disclosure. In some embodiments, the mask 506 may be disposed over a dielectric layer 502. For example, using photolithography, a mask 506 comprising a pattern of holes 504a-504h may be disposed. Holes 504a-504h may correspond to the cross-sections of contact portions 106a-106h. In some embodiments, holes 504a-504h may be elliptical in shape. In some embodiments, holes 504a-504h may have a long diameter along direction 112. Holes 504a, 504c, and 504e may be disposed over interconnect 102a. Hole 504g may be disposed over interconnect 102b. Holes 504b, 504d, and 504f may be disposed over interconnect 102c. Hole 504h may be disposed over interconnect 102d.

[0045] Dry etching can be performed through holes 504a to 504h to remove portions of one or more dielectric layers 502. Portions of one or more dielectric layers 502 below holes 504a-504h that are not covered by mask 506 can be exposed for etching. In some embodiments, dry etching can be performed until the etching is stopped by interconnects 102a-102d. Thus, portions of one or more dielectric layers 502 below holes 504a-504h can be removed, and openings can be formed. These openings expose interconnects 102a-102d at their bottom. Mask 506 can be removed in post-etching processes (e.g., dry ashing and wet cleaning).

[0046] In some embodiments, conductive material may be deposited on one or more dielectric layers 502 in the opening to form contact portions 106a-106h in the opening. The contact portions 106a-106h are formed in the holes 504a-504h such that the contact portions 106a-106h have an elliptical shape with a long diameter DL1 along direction 112, as shown below. Figure 2B As shown in the diagram. The conductive material may be, for example, tungsten. The conductive material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Contact portions 106a-106h may be disposed on interconnects 102a-102d. In some embodiments, the height 510 of the power supply line 208 in the memory array region 202 may be substantially the same as the height 508 of the contact portions 106a-106h.

[0047] Figure 6A This is a vertical cross-sectional view of a schematic structure of a portion 600 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 6B This is another vertical cross-sectional view of a schematic structure of a portion 600 of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 6A The vertical cross-sectional view of part 600 is a view along direction 114. Figure 6B Another vertical cross-sectional view of portion 600 is a view along direction 112. In some embodiments, portion 600 of the semiconductor device 100 may be used for manufacturing Figure 2A and 2B Part 200 of the intermediate structure.

[0048] One or more dielectric layers 218 may be formed over the contact portions 106a-106h in the peripheral region 204 and over the power supply lines 208 in the memory array region 202. In some embodiments, the dielectric layer 218 may comprise a dielectric material. The dielectric material may comprise, for example, silicon oxide (SiO2). The dielectric material may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0049] One or more portions of dielectric layer 218 may be removed to form an opening. In some embodiments, the removal of one or more portions of dielectric layer 218 to form an opening may be performed by photo-patterning a mask and dry etching a pattern in the mask. Figure 6C This is a schematic diagram of a mask 602 according to an embodiment of the present disclosure. In some embodiments, the mask 602 may be disposed over a dielectric layer 218. For example, using photolithography, a mask 602 comprising a pattern of holes 604a-604h may be disposed. Holes 604a-604h may correspond to the cross-sections of contact portions 108a-108h. In some embodiments, holes 604a-604h may be elliptical in shape. In some embodiments, each of holes 604a-604h may have a long diameter along direction 114. Holes 604a, 604c, and 604e may be disposed over interconnect 102a. Hole 604g may be disposed over interconnect 102b. Holes 604b, 604d, and 604f may be disposed over interconnect 102c. Hole 604h may be disposed over interconnect 102d.

[0050] Dry etching can be performed through holes 604a-604h to remove portions of one or more dielectric layers 218. Portions of one or more dielectric layers 218 below holes 604a-604h that are not covered by mask 602 can be exposed for etching. In some embodiments, dry etching can be performed until the etching stops at the contact. Therefore, portions of one or more dielectric layers 502 below holes 504a-504h can be removed, and an opening can be formed. This opening exposes the contact portions 106a-106h at the bottom of the opening. Mask 602 can be removed in post-etching processes (e.g., dry ashing and wet cleaning).

[0051] In some embodiments, conductive material may be deposited on one or more dielectric layers 502 to form contact portions 108a-108hh in the openings. The contact portions 108a-108h are formed in the holes 604a-604h such that the contact portions 108a-108h have an elliptical shape with a long diameter DL2 along direction 114, as shown below. Figure 2A As shown in the diagram. The conductive material can be, for example, tungsten. The conductive material can be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0052] Figure 1 The interconnects 104a-104d can be disposed on one or more dielectric layers 218 and on contact portions 108a-108h in the one or more dielectric layers 218. The interconnects 104a-104d can extend along direction 114. The formation of the interconnects 104a-104d can be similar to that in the previous reference. Figure 4A and4B The formation of interconnects 102a-102d in dielectric layer 402 is described and shown; therefore, for the sake of brevity, the description of the formation of interconnects 104a-104d is omitted. Figure 1 As shown, interconnect 104a can be disposed on contact portions 108a and 108b, interconnect 104b can be disposed on contact portions 108c and 108d, interconnect 104c can be disposed on contact portions 108e and 108f, and interconnect 104d can be disposed on contact portions 108g and 108h.

[0053] In the above description, contacts are formed through two steps; however, the number of steps for forming contacts is not limited to two. Forming contacts (e.g., vias) in the peripheral area through multiple etching steps, rather than a single etching step, results in openings with smaller cross-sections, unlike contacts formed using a single etching step. Each contact may have an elliptical cross-section with a long diameter along a direction in which each interconnect coupled to each contact extends. This prevents short circuits between adjacent interconnects.

[0054] While various embodiments have been disclosed in this disclosure, those skilled in the art will understand that the scope of this disclosure extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses, as well as their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form varied embodiments. Therefore, it is intended that the scope of at least some of this disclosure should not be limited to the specific disclosed embodiments described above.

Claims

1. A device comprising contacts in a peripheral area, comprising: A plurality of first interconnects extending along a first direction; A plurality of second interconnects located above the plurality of first interconnects, the plurality of second interconnects extending along a second direction different from the first direction; Multiple contacts, wherein each of the multiple contacts includes: A first portion of a corresponding first interconnect in the plurality of first interconnects; and The second portion is located on the first portion, and the second portion is coupled to a corresponding second interconnect among the plurality of second interconnects. The first portion has a first cross-section, the first cross-section comprising: The first length along the first direction; and A first width that is perpendicular to the first length and smaller than the first length, and The second portion has a second cross-section, the second cross-section comprising: The second length along the second direction; and A second width that is perpendicular to the second length and smaller than the second length.

2. The device according to claim 1, wherein when viewed from above the device, the first direction and the second direction are perpendicular to each other.

3. The device according to claim 1, wherein the first cross-section has an elliptical shape, the elliptical shape having a major diameter along the first direction.

4. The device of claim 3, wherein the short diameter of the first cross section is less than the sum of the width of each first interconnect and the spacing between adjacent first interconnects in the plurality of first interconnects.

5. The device according to claim 1, wherein the second cross-section has an elliptical shape, the elliptical shape having a major diameter along the second direction.

6. The device of claim 5, wherein the short diameter of the second cross section is less than the sum of the width of each second interconnect and the spacing between adjacent second interconnects in the plurality of second interconnects.

7. The device of claim 1, wherein one or more of the plurality of first interconnects, one or more of the plurality of second interconnects, and one or more of the plurality of contacts comprise one or more conductive materials.

8. The device of claim 7, wherein the one or more contacts comprise tungsten.

9. The device of claim 7, wherein the one or more first interconnects and the one or more second interconnects comprise at least one of copper or aluminum.

10. The device according to claim 1, further comprising: The memory array region comprises multiple memory cells, and The plurality of contacts are located in the peripheral area.

11. The device of claim 10, wherein each of the plurality of memory cells further comprises: Transistors on a substrate; The capacitor on the transistor, the capacitor comprising: Coupled to the lower capacitor electrode of the transistor; and Upper capacitor electrodes; and Power supply lines coupled to the upper capacitor electrodes; The height of the first portion from the substrate is approximately the same as the height of the portion of the power supply line located in the memory array area from the substrate.

12. The device of claim 11, wherein the portion of the power supply line located in the memory array region is a first portion. The power supply line includes a second portion of the peripheral area located below the plurality of first interconnects.

13. A method for forming a contact in a peripheral area, comprising: Forming multiple first interconnects; One or more first dielectric layers are formed over the plurality of first interconnects in the peripheral region; Removing a first portion of the one or more first dielectric layers to form a plurality of first openings through the one or more first dielectric layers in the peripheral region, thereby exposing the plurality of first interconnects at the bottom of the plurality of first openings, wherein removing the first portion of the one or more first dielectric layers includes: Deposit a first mask on one or more first dielectric layers; The first pattern is optically patterned on the first mask; Dry etching of the first pattern to form the plurality of first openings; and Remove the first mask. The first pattern on the first mask includes a plurality of first ellipses corresponding to the plurality of first openings, wherein each of the plurality of first ellipses has a first major diameter along a first direction; A first conductive material is deposited in the peripheral region to form a plurality of first contact portions in the plurality of first openings; In the peripheral region, one or more second dielectric layers are formed on the one or more first dielectric layers and the multiple first contact portions; Removing a second portion of the one or more second dielectric layers to form a plurality of second openings through the one or more second dielectric layers, thereby exposing a plurality of first contact portions at the bottom of the plurality of second openings, wherein removing the second portion of the one or more second dielectric layers includes: Deposit a second mask on one or more second dielectric layers; A second pattern is optically patterned on the second mask; Dry etching of the second pattern to form the plurality of second openings; and Remove the second mask. The second pattern on the second mask includes a plurality of second ellipses corresponding to the plurality of second openings, wherein each of the plurality of second ellipses has a second long diameter along a second direction; Deposit a second conductive material to form a plurality of second contact portions in the corresponding plurality of first openings; and A plurality of second interconnects are formed on the plurality of second contact portions, wherein the plurality of first interconnects extend along the first direction and the plurality of second interconnects extend along a second direction different from the first direction.

14. The method of claim 13, wherein forming the plurality of first interconnects comprises forming the plurality of first interconnects to extend along the first direction. Forming the plurality of second interconnects includes forming the plurality of second interconnects to extend along a second direction perpendicular to the first direction.

15. The method of claim 13, wherein forming the plurality of first interconnects comprises forming the plurality of first interconnects to extend along the first direction. Forming the plurality of second interconnects includes forming the plurality of second interconnects to extend along a second direction different from the first direction. Each of the plurality of first openings has a first cross-section including a first length along the first direction, and Each of the plurality of second openings has a second cross-section including a second length along the second direction.

16. The method of claim 15, wherein the short diameter of the first cross-section is less than the sum of the width of each first interconnect and the first spacing between adjacent first interconnects in the plurality of first interconnects, and The short diameter of the second cross section is less than the sum of the width of each second interconnect and the second spacing between adjacent second interconnects in the plurality of second interconnects.

17. A device comprising contacts in a peripheral area, comprising: A first interconnect extending along a first direction; A second interconnect located above the first interconnect, the second interconnect extending along a second direction different from the first direction; and A contact coupled between the first interconnect and the second interconnect, wherein the contact includes: A first portion located on the first interconnect, wherein the cross-section of the first portion has an elliptical shape, the elliptical shape having a major diameter along the first direction; and A second portion located between the first portion and the second interconnect, wherein the cross-section of the second portion has an elliptical shape, the elliptical shape having a long diameter along the second direction.

18. The device according to claim 17, further comprising: Substrate; Memory array area; Multiple capacitors disposed in the memory array region and above the substrate of multiple memory cells; and A power supply line extends over the plurality of capacitors in the memory array region and further over the substrate and under the first interconnect in the peripheral region.

19. The device of claim 18, wherein the cross-section of the first portion has a short diameter along the second direction, the short diameter being less than the sum of the width of the first interconnect and the first spacing between the first interconnect and another first interconnect adjacent to the first interconnect, and The short diameter of the cross section of the second portion is less than the sum of the width of the second interconnect and the second spacing between the second interconnect and another second interconnect adjacent to the second interconnect.

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