Method and apparatus for high level syntax in video coding
Patent Information
- Application Number
- CN202180039854.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-04-04
- Filing Date
- 2021-04-02
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2041-04-02
Smart Images
Figure CN115715467B_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application is based on and claims priority to provisional application No. 63 / 005,203 filed on April 3, 2020 and provisional application No. 63 / 005,309 filed on April 4, 2020, the entire contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field
[0003] This disclosure relates to video encoding / decoding and compression. More specifically, this application relates to high-level syntax in video bitstreams applicable to one or more video encoding / decoding standards. Background Technology
[0004] Various video codec techniques can be used to compress video data. Video codecs are performed according to one or more video codec standards. Examples of video codec standards include Universal Video Codec (VVC), Joint Explore Test Model (JEM), High Efficiency Video Codec (H.265 / HEVC), High-Level Video Codec (H.264 / AVC), and Moving Picture Experts Group (MPEG) codecs. Video codecs typically use predictive methods (e.g., inter-frame prediction, intra-frame prediction, etc.) that utilize redundancy present in video images or sequences. A key goal of video codec techniques is to compress video data into a form that uses a lower bitrate while avoiding or minimizing video quality degradation. Summary of the Invention
[0005] Examples of this disclosure provide methods and apparatus for lossless encoding and decoding in video encoding and decoding.
[0006] According to a first aspect of this disclosure, a method for decoding a video signal is provided. The method may include a decoder receiving at least one general video codec (VVC) syntax flag. The at least one VVC syntax flag may include a first VVC syntax flag that can indicate whether inter-frame prediction is allowed in a corresponding codec level. The decoder may also receive an inter-frame correlation syntax element in response to a syntax element indicating that inter-frame prediction is allowed. The decoder may also obtain a first reference picture I associated with a video block in the bitstream. (0) Second reference image I (1) According to the display order, the first reference image I (0) It can be before the current image and the second reference image I (1) It can be after the current image. The decoder can also be from the first reference image I. (0) The reference block in the video block obtains the first predicted sample I of the video block. (0)(i, j). i and j can represent the coordinates of a sample point in the current image. The decoder can also obtain coordinates from the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i, j). The decoder can also be based on the at least one VVC syntax flag, the inter-frame correlation syntax element, and the first prediction sample I. (0) (i, j) and the second predicted sample I (1) (i, j) are used to obtain bidirectional prediction samples.
[0007] According to a second aspect of this disclosure, a method for decoding a video signal is provided. The method may include a decoder receiving permutation partitioning constraint syntax elements at the sequence parameter set (SPS) level. The permutation partitioning constraint syntax elements are arranged such that inter-frame prediction related syntax elements are grouped according to VVC syntax at the codec level. The decoder may also obtain a first reference picture I associated with a video block in the bitstream. (0) Second reference image I (1) According to the display order, the first reference image I (0) It can be before the current image and the second reference image I (1) It can be after the current image. The decoder can also be from the first reference image I. (0) The reference block in the video block obtains the first predicted sample I of the video block. (0) (i, j). i and j can represent the coordinates of a sample point in the current image. The decoder can also obtain coordinates from the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i, j). The decoder can also be based on the permutation partition constraint syntax element and the first prediction sample I. (0) (i, j) and the second predicted sample I (1) (i, j) are used to obtain bidirectional prediction samples.
[0008] According to a third aspect of this disclosure, a computing device is provided. The computing device may include one or more processors and a non-transitory computer-readable storage memory storing instructions executable by the one or more processors. The one or more processors may be configured to receive at least one VVC syntax flag. The at least one VVC syntax flag includes a first VVC syntax flag indicating whether inter-frame prediction is permitted in a corresponding codec level. The one or more processors may be further configured to receive an inter-frame related syntax element in response to a syntax element indicating that inter-frame prediction is permitted. The one or more processors may be further configured to obtain a first reference picture I associated with a video block in a bitstream. (0)Second reference image I (1) According to the display order, the first reference image I (0) It can be before the current image and the second reference image I (1) This can occur after the current image. The one or more processors can be further configured to start from the first reference image I. (0) The reference block in the video block obtains the first predicted sample I of the video block. (0) (i, j). i and j can represent the coordinates of a sample point in the current image. The one or more processors can be further configured to process data from the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i, j). The one or more processors may be further configured to base their operations on the at least one VVC syntax flag, the inter-frame correlation syntax element, and the first prediction sample I. (0) (i, j) and the second predicted sample I (1) (i, j) are used to obtain bidirectional prediction samples.
[0009] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided in which instructions are stored. When executed by one or more processors of the device, the instructions can cause the device to receive SPS-level permutation partition constraint syntax elements. The permutation partition constraint syntax elements are arranged such that inter-frame prediction related syntax elements are grouped according to VVC syntax at the codec level. The instructions can also cause the device to obtain a first reference picture I associated with a video block in the bitstream. (0) Second reference image I (1) According to the display order, the first reference image I (0) It can be before the current image and the second reference image I ( 1) It can be after the current image. The instruction can also cause the device to start from the first reference image I. (0) The reference block in the video block obtains the first predicted sample I of the video block. (0) (i, j). i and j can represent the coordinates of a sample point in the current image. The instruction can also cause the device to access the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i, j). The instructions can also cause the device to base its operation on the permutation partition constraint syntax element and the first prediction sample I. (0) (i, j) and the second predicted sample I (1) (i, j) are used to obtain bidirectional prediction samples.
[0010] It should be understood that the general description above and the detailed description below are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0011] Examples consistent with this disclosure are illustrated in conjunction with the accompanying drawings, which are included in and form part of this specification, and together with the description, serve to explain the principles of this disclosure.
[0012] Figure 1 This is a block diagram of an encoder based on an example of this disclosure.
[0013] Figure 2 This is a block diagram of a decoder based on an example of this disclosure.
[0014] Figure 3A This is a diagram illustrating block partitioning in a multi-type tree structure according to an example of this disclosure.
[0015] Figure 3B This is a diagram illustrating block partitioning in a multi-type tree structure according to an example of this disclosure.
[0016] Figure 3C This is a diagram illustrating block partitioning in a multi-type tree structure according to an example of this disclosure.
[0017] Figure 3D This is a diagram illustrating block partitioning in a multi-type tree structure according to an example of this disclosure.
[0018] Figure 3E This is a diagram illustrating block partitioning in a multi-type tree structure according to an example of this disclosure.
[0019] Figure 4 This is an example of a method for decoding video signals according to the present disclosure.
[0020] Figure 5 This is an example of a method for decoding video signals according to this disclosure.
[0021] Figure 6 This is an example of a method for decoding video signals according to this disclosure.
[0022] Figure 7 This is a diagram illustrating a computing environment coupled to a user interface according to an example of this disclosure. Detailed Implementation
[0023] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. All descriptions herein are made with reference to the accompanying drawings, in which, unless otherwise stated, the same reference numerals in different drawings denote the same or similar elements. The embodiments described below are not intended to represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with the aspects of this disclosure set forth in the appended claims.
[0024] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein is intended to represent and include any or all possible combinations of one or more of the associated enumerated items.
[0025] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various types of information, such information should not be limited by these terms. These terms are merely used to distinguish one type of information from another. For example, without departing from the scope of this disclosure, first information may be referred to as second information; and similarly, second information may be referred to as first information. As used herein, depending on the context, the term “if” may be understood to mean “when,” “in,” or “in response to a judgment.”
[0026] The first version of the HEVC standard was completed in October 2013, offering approximately 50% bitrate savings or equivalent perceived quality compared to its predecessor, H.264 / MPEG-AVC. While HEVC offered significant codec improvements over its predecessor, evidence suggested that even better codec efficiency could be achieved using additional codec tools. Building on this, both VCEG and MPEG began exploring new codec technologies to standardize future video codecs. In October 2015, ITU-T VECG and ISO / IEC MPEG established a Joint Video Exploration Team (JVET) to conduct significant research into advanced technologies that could substantially improve codec efficiency. JVET maintains a reference software called the Joint Exploration Model (JEM) by integrating multiple additional codec tools based on the HEVC Test Model (HM).
[0027] In October 2017, the ITU-T and ISO / IEC issued a joint call for proposals (CfP) on video compression capabilities exceeding HEVC. In April 2018, the 10th JVET meeting received and evaluated 23 CfP responses, demonstrating a compression efficiency improvement of approximately 40% compared to HEVC. Based on these evaluation results, JVET launched a new project to develop a next-generation video codec standard called Universal Video Codec (VVC). That same month, a reference software codebase called the VVC Test Model (VTM) was established to demonstrate a reference implementation of the VVC standard. Like HEVC, VVC is built on a block-based hybrid video codec framework.
[0028] Figure 1 A general diagram of a block-based video encoder for VVC is shown. Specifically, Figure 1 A typical encoder 100 is shown. The encoder 100 has a video input 110, motion compensation 112, motion estimation 114, intra / inter-frame mode decision 116, block prediction value 140, adder 128, transform 130, quantization 132, prediction related information 142, intra-frame prediction 118, image buffer 120, inverse quantization 134, inverse transform 136, adder 126, memory 124, loop filter 122, entropy coding 138, and bitstream 144.
[0029] In encoder 100, video frames are partitioned into multiple video blocks for processing. For each given video block, a prediction is formed based on either an inter-frame prediction method or an intra-frame prediction method.
[0030] The prediction residual, representing the difference between the current video block (a portion of video input 110) and its predicted value (a portion of block prediction value 140), is sent from adder 128 to transform 130. The transform coefficients are then sent from transform 130 to quantization 132 for entropy reduction. The quantization coefficients are then fed to entropy coding 138 to generate a compressed video bitstream. Figure 1 As shown, prediction-related information 142 (such as video block partitioning information, motion vectors (MV), reference picture indexes, and intra-prediction modes) from intra-frame / inter-frame mode decision 116 is also fed through entropy coding 138 and stored in compressed bitstream 144. Compressed bitstream 144 includes the video bitstream.
[0031] In encoder 100, decoder-related circuitry is also required to reconstruct pixels for prediction purposes. First, the prediction residual is reconstructed via inverse quantization 134 and inverse transform 136. This reconstructed prediction residual is combined with block prediction values 140 to generate the unfiltered reconstructed pixels for the current video block.
[0032] Spatial prediction (or "intra-frame prediction") uses pixels from samples (called reference samples) of already encoded neighboring blocks in the same video frame as the current video block to predict the current video block.
[0033] Timing prediction (also known as "inter-frame prediction") uses reconstructed pixels from its own encoded and decoded video frames to predict the current video block. Timing prediction reduces the temporal redundancy inherent in the video signal. The timing prediction signal for a given coding unit (CU) or coding block is typically sent by one or more MV signals indicating the amount and direction of motion between the current CU and its timing reference. Further, if multiple reference frames are supported, an additional reference frame index is sent to identify which reference frame in the reference frame storage the timing prediction signal originates from.
[0034] Motion estimation 114 acquires the video input 110 and the signal from the image buffer 120, and outputs the motion estimation signal to motion compensation 112. Motion compensation 112 acquires the video input 110, the signal from the image buffer 120, and the motion estimation signal from motion estimation 114, and outputs the motion compensation signal to intra / inter-frame mode decision 116.
[0035] After performing spatial and / or temporal prediction, the intra / inter-frame mode decision 116 in encoder 100 selects the optimal prediction mode, for example, based on a rate-distortion optimization method. Then, the block prediction value 140 is subtracted from the current video block, and the resulting prediction residual is decorrelated using transform 130 and quantization 132. The resulting quantization residual coefficients are dequantized by inverse quantization 134, and then inversely transformed by inverse transform 136 to form a reconstruction residual, which is then added back to the prediction block to form the reconstructed CU signal. Before placing the reconstructed CU in the reference picture storage of picture buffer 120 and using it for encoding and decoding future video blocks, further loop filtering 122, such as deblocking filters, sample adaptive offset (SAO), and / or adaptive loop filter (ALF), can be applied to the reconstructed CU. To form the output video bitstream 144, the encoding / decoding mode (inter-frame or intra-frame), prediction mode information, motion information, and quantization residual coefficients are sent to entropy coding unit 138 for further compression and packing to form the bitstream.
[0036] Figure 1A block diagram of a general block-based hybrid video coding system is presented. The input video signal is processed block by block (called a coding unit (CU)). In VTM-1.0, the CU can be up to 128×128 pixels. However, unlike HEVC, which partitions blocks solely based on quadtrees, in VVC, a coding tree unit (CTU) is divided into multiple CUs to accommodate different local characteristics based on quadtrees, binary trees, and ternary trees. Furthermore, the concept of multiple partitioned unit types in HEVC is removed; that is, the splitting of CUs, prediction units (PUs), and transform units (TUs) no longer exists in VVC. Instead, each CU is always used as the basic unit for both prediction and transform without further partitioning. In the multi-type tree structure, a CTU is first partitioned by a quadtree structure. Then, each quadtree leaf node can be further partitioned by binary and ternary tree structures.
[0037] like Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, there are five partitioning types: quad partitioning, horizontal binary partitioning, vertical binary partitioning, horizontal ternary partitioning, and vertical ternary partitioning.
[0038] Figure 3A A diagram illustrating block quadrilateral partitioning in a multi-type tree structure according to this disclosure is shown.
[0039] Figure 3B A diagram illustrating block vertical binary partitioning in a multi-type tree structure according to this disclosure is shown.
[0040] Figure 3C A diagram illustrating block-level binary partitioning in a multi-type tree structure according to this disclosure is shown.
[0041] Figure 3D A diagram illustrating block vertical ternary partitioning in a multi-type tree structure according to this disclosure is shown.
[0042] Figure 3E A diagram illustrating block-level ternary partitioning in a multi-type tree structure according to this disclosure is shown.
[0043] exist Figure 1In the encoder, spatial prediction and / or temporal prediction can be performed. Spatial prediction (or "intra-frame prediction") uses pixels from samples (called reference samples) of adjacent blocks already encoded and decoded within the same video picture / strip to predict the current video block. Spatial prediction reduces the spatial redundancy inherent in the video signal. Temporal prediction (also known as "inter-frame prediction" or "motion-compensated prediction") uses reconstructed pixels from already encoded and decoded video pictures to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in the video signal. The temporal prediction signal for a given CU is typically sent by one or more motion vectors (MVs) indicating the amount and direction of motion between the current CU and its temporal reference. Similarly, if multiple reference pictures are supported, an additional reference picture index is sent to identify which reference picture in the reference picture storage the temporal prediction signal comes from. After performing spatial and / or temporal prediction, a mode decision block in the encoder selects the optimal prediction mode, for example, based on a rate-distortion optimization method. The prediction block is then subtracted from the current video block; and the prediction residual is decorrelated and quantized using a transform. The quantized residual coefficients are dequantized and inversely transformed to form the reconstructed residuals, which are then added back to the prediction block to form the reconstructed CU signal. Further, before placing the reconstructed CU in the reference image storage and using it for encoding and decoding future video blocks, loop filtering such as deblocking filters, Sample Adaptive Offset (SAO), and Adaptive Loop Filter (ALF) can be applied to the reconstructed CU. To form the output video bitstream, the encoding / decoding mode (inter-frame or intra-frame), prediction mode information, motion information, and quantized residual coefficients are sent to the entropy coding unit for further compression and packing to form the bitstream.
[0044] Figure 2 A general block diagram of the video decoder used in VVC is shown. Specifically, Figure 2 A block diagram of a typical decoder 200 is shown. The decoder 200 has a bitstream 210, entropy decoding 212, dequantization 214, inverse transform 216, adder 218, intra / inter-frame mode selection 220, intra-frame prediction 222, memory 230, loop filter 228, motion compensation 224, image buffer 226, prediction-related information 234, and video output 232.
[0045] Decoder 200 is similar to that which exists Figure 1The reconstruction-related part is located in the encoder 100. In the decoder 200, the incoming video bitstream 210 is first decoded by entropy decoding 212 to obtain quantization coefficient levels and prediction-related information. Then, the quantization coefficient levels are processed by inverse quantization 214 and inverse transform 216 to obtain the reconstruction prediction residual. The block prediction mechanism implemented in the intra / inter-frame mode selector 220 is configured to perform intra-frame prediction 222 or motion compensation 224 based on the decoded prediction information. A set of unfiltered reconstructed pixels is obtained by summing the reconstruction prediction residual from inverse transform 216 with the prediction output generated by the block prediction mechanism using summer 218.
[0046] The reconstructed blocks can be further passed through loop filter 228 and then stored in image buffer 226, which serves as a reference image storage. The reconstructed video in image buffer 226 can be sent to drive the display device and used to predict future video blocks. With loop filter 228 enabled, filtering operations are performed on these reconstructed pixels to obtain the final reconstructed video output 232.
[0047] Figure 2 A general block diagram of a block-based video decoder is presented. First, entropy decoding of the video bitstream is performed at the entropy decoding unit. The encoding / decoding mode and prediction information are sent to the spatial prediction unit (in the case of intra-frame encoding / decoding) or the temporal prediction unit (in the case of inter-frame encoding / decoding) to form prediction blocks. The residual transform coefficients are sent to the inverse quantization unit and the inverse transform unit to reconstruct the residual blocks. Then, the prediction blocks and residual blocks are added together. The reconstructed blocks can be further filtered through a loop and then stored in a reference image store. Finally, the reconstructed video from the reference image store is sent to drive the display device and used to predict future video blocks.
[0048] Typically, the basic intra-prediction scheme used in VVC is the same as that in HEVC, with the difference being that several modules are further extended and / or improved, such as Matrix Weighted Intra-Prediction (MIP) encoding / decoding mode, Intra-Segmentation-Partition (ISP) encoding / decoding mode, Extended Intra-Prediction Utilizing Wide-Angle Intra-Direction, Position-Dependent Intra-Prediction Combination (PDPC), and 4-Tap Intra-Interpolation. The main focus of this disclosure is to improve the existing high-level syntax design in the VVC standard. The relevant background information is elaborated in detail in the following sections.
[0049] Like HEVC, VVC uses a bitstream structure based on Network Abstraction Layer (NAL) units. The encoded bitstream is partitioned into multiple NAL units, which should be smaller than the Maximum Transmission Unit (MTU) size when transmitted over a lossy packet network. Each NAL unit consists of a NAL unit header and a subsequent NAL unit payload. There are two conceptual categories of NAL units: Video Codec Layer (VCL) NAL units containing encoded sample data, such as encoded stripe NAL units; and non-VCL NAL units containing metadata typically belonging to more than one encoded picture, or parameter set NAL units where association with a single encoded picture would be meaningless, or SEI NAL units where information is not needed during decoding.
[0050] The VVC specification introduces a two-byte NAL unit header, a design intended to support future expansions. The syntax and associated semantics of the NAL unit header in the current VVC draft specification are illustrated in Tables 1 and 2, respectively. How to read Table 1 is illustrated in the appendix of this invention, which can also be found in the VVC specification.
[0051] Table 1. NAL Unit Header Syntax
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[0053] Table 2. Semantics of NAL Unit Headers
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[0055] Table 3. NAL Unit Type Codes and NAL Unit Type Categories
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[0058] VVC inherits the parameter set concept from HEVC and makes some modifications and additions. A parameter set can be part of the video bitstream or can be received by the decoder through other means (including out-of-band transmission using reliable channels, hard encoding / decoding in the encoder and decoder, etc.). The parameter set contains identifiers directly or indirectly referenced from the stripe header, as discussed in more detail later. This referencing process is called "activation." Activation occurs per picture or per sequence, depending on the parameter set type. The concept of activation by reference is introduced, among other reasons, because implicit activation cannot be performed by the location of information in the bitstream (such as information common to other syntax elements of the video codec) in the case of out-of-band transmission.
[0059] Video Parameter Sets (VPSs) are introduced to convey information applicable to multiple layers and sublayers. VPSs are introduced to address these shortcomings and enable a clean and scalable high-level design for multi-layer codecs. Regardless of whether each layer of a given video sequence has the same or different Sequence Parameter Sets (SPSs), they all refer to the same VPS. The syntax and associated semantics of video parameter sets in the current VVC draft specification are illustrated in Tables 4 and 5, respectively. How to read Table 4 is illustrated in the appendix of this invention, which can also be found in the VVC specification.
[0060] Table 4 Video Parameter Set RBSP Syntax
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[0065] Table 5. Semantics of Video Parameter Set RBSP
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[0075] In VVC, the SPS contains information applicable to all stripes of an encoded video sequence. An encoded video sequence begins with an Instantaneous Decode Refresh (IDR) picture, a BLA picture, or a CRA picture of the first picture in the bitstream, and includes all subsequent pictures that are not IDR or BLA pictures. The bitstream consists of one or more encoded video sequences. The content of the SPS can be broadly categorized into six types: 1) self-references (its own ID); 2) decoder operation point information (profile, level, picture size, number of sublayers, etc.); 3) enable flags for certain tools within the profile, and associated codec tool parameters when the tools are enabled; 4) information limiting the flexibility of encoding and decoding structures and transform coefficients; 5) temporal scalability controls; and 6) visual usability information (VUI) including HRD information. The syntax and associated semantics of the sequence parameter set in the current VVC draft specification are illustrated in Tables 6 and 7, respectively. How to read Table 6 is illustrated in the appendix of this invention, which can also be found in the VVC specification.
[0076] Table 6. Sequence Parameter Set (RBSP) Syntax
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[0084] Table 7. Sequence Parameter Set (RBSP) Semantics
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[0104] The Picture Parameter Set (PPS) of VVC contains information that can be changed between pictures. The PPS includes information roughly equivalent to a portion of the PPS in HEVC, including: 1) self-reference; 2) initial picture control information, such as initial quantization parameters (QP), the number of flags indicating the use or presence of certain tools, or control information in the strip header; and 3) tile information. The syntax and associated semantics of the sequence parameter set in the current VVC draft specification are illustrated in Tables 8 and 9, respectively. How to read Table 8 is illustrated in the appendix of this invention, which can also be found in the VVC specification.
[0105] Table 8. Image Parameter Set RBSP Syntax
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[0111] Table 9. Image Parameter Set RBSP Semantics
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[0122] The strip header contains information that can be changed between strips, as well as relatively small or picture-related information that is only relevant to a specific strip or picture type. The size of the strip header can be significantly larger than the PPS, especially when there are tile or wavefront entry point offsets in the strip header and RPS, explicitly modified by signal transmission prediction weights or reference picture lists. The syntax and associated semantics of the sequence parameter set in the current VVC draft specification are illustrated in Tables 10 and 11, respectively. How to read Table 10 is illustrated in the appendix of this invention, which can also be found in the VVC specification.
[0123] Table 10. Image Header Structure Syntax
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[0129] Table 11. Image header structure and semantics
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[0141] Improvements to syntactic elements
[0142] In the current VVC, when similar syntax elements exist for intra-frame prediction and inter-frame prediction respectively, in some places the syntax elements related to inter-frame prediction are defined before those related to intra-frame prediction. Given that intra-frame prediction is allowed but inter-frame prediction is not in all picture / strip types, this order may not be preferred. From a standardization perspective, it would be beneficial to always define the intra-frame prediction-related syntax before the syntax used for inter-frame prediction.
[0143] It was also observed that in the current VVC, some highly related syntactic elements are defined in a sprawling manner in different places. From a standardization perspective, grouping some syntactic elements together would also be beneficial.
[0144] The proposed method
[0145] Methods are provided to simplify and / or further improve existing designs of advanced grammars. It should be noted that the invented methods can be applied independently or in combination.
[0146] Grouping partition constraint syntax elements by prediction type
[0147] This disclosure proposes rearranging the syntax elements such that intra-prediction-related syntax elements are defined before those related to inter-frame prediction. According to this disclosure, partition constraint syntax elements are grouped by prediction type, with intra-prediction-related elements preceding inter-frame prediction-related elements. In one embodiment, the order of partition constraint syntax elements in the SPS is consistent with the order of partition constraint syntax elements in the picture header. An example of the decoding process for the VVC draft is illustrated in Table 12 below. Changes to the VVC draft are shown using bold and italic fonts.
[0148] Table 12. Proposed Sequence Parameter Set (RBSP) Syntax
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[0151] Grouping the two-tree chroma syntax elements
[0152] This disclosure proposes grouping syntax elements associated with dual-tree chroma types. In one embodiment, the partition constraint syntax elements of dual-tree chroma in the SPS should be signaled together in the case of dual-tree chroma. An example of the decoding process for the VVC draft is illustrated in Table 13 below. Changes to the VVC draft are shown in bold and italics.
[0153] Table 13. Proposed Sequence Parameter Set (RBSP) Syntax
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[0156] If we also consider defining intra-prediction related syntax before inter-prediction related syntax, then another example of the decoding process for the VVC draft is illustrated in Table 14 below, according to the method of this disclosure. Changes to the VVC draft are shown in bold and italics.
[0157] Table 14. Proposed Sequence Parameter Set (RBSP) Syntax
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[0160] Conditionally send inter-frame prediction related syntax elements using signals
[0161] As mentioned in the earlier description, current VVC allows intra-frame prediction but not inter-frame prediction in all picture / strip types. According to this disclosure, it is proposed to add a flag in the VVC syntax at a specific codec level to indicate whether inter-frame prediction is allowed in sequences, pictures, and / or stripes. If inter-frame prediction is not allowed, the inter-frame prediction related syntax is not signaled at the corresponding codec level (e.g., sequence, picture, and / or stripe level).
[0162] It also proposes adding flags to the VVC syntax at specific codec levels to indicate whether inter-frame striping, such as P-striping and B-striping, is allowed in sequences, pictures, and / or stripes. If inter-frame striping is not allowed, the inter-frame striping related syntax is not signaled at the corresponding codec level (e.g., sequence, picture, and / or stripe level).
[0163] The following sections provide some examples based on the proposed flags for allowing inter-frame striping. Furthermore, the proposed flags for allowing inter-frame prediction can be used in a similar manner.
[0164] When adding flags indicating the allowance of inter-frame striping at different levels, these flags can be signaled in a hierarchical manner. When a higher-level flag, signaled by signaling, indicates that inter-frame striping is not allowed, lower-level flags do not need to be signaled and can be inferred to be 0 (meaning that inter-frame striping is not allowed).
[0165] In one or more examples, flags are added in the SPS to indicate whether inter-frame striping is allowed during encoding and decoding of the current video sequence. If not allowed, inter-frame striping-related syntax elements are not signaled in the SPS. An example of the decoding process for the VVC draft is illustrated in Table 15 below. Changes to the VVC draft are shown in bold and italics. It should be noted that there are syntax elements other than those described in this example. For example, there are many inter-frame striping (or inter-frame prediction tool) related syntax elements, such as `sps_weighted_pred_flag`, `sps_temporal_mvp_enabled_flag`, `sps_amvr_enabled_flag`, `sps_bdof_enabled_flag`, etc.; there are also syntax elements related to the list of reference pictures, such as `long_term_ref_pics_flag`, `inter_layer_ref_pics_present_flag`, `sps_idr_rpl_present_flag`, etc. All these syntax elements related to inter-frame prediction can be selectively controlled by the proposed flags.
[0166] Table 15 presents the RBSP syntax for the sequence parameter set.
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[0173]
[0174]
[0175] 7.4.3.3 Sequence Parameter Set (RBSP) Semantics
[0176] `sps_inter_slice_allowed_flag` equal to 0 specifies that all encoded slices in the video sequence have a slice_type equal to 2 (which indicates that the encoded slices are I slices). `sps_inter_slice_allowed_flag` equal to 1 specifies that one or more encoded slices in the video sequence may or may not have a slice_type equal to 0 (which indicates that the encoded slices are P slices) or 1 (which indicates that the encoded slices are B slices).
[0177] In another example, according to the method of this disclosure, a flag is added to the Picture Parameter Set (PPS) to indicate whether inter-frame striping is allowed during encoding and decoding of the picture associated with this PPS. If not allowed, the selected inter-frame prediction related syntax elements are not signaled in the PPS.
[0178] In another example, according to the method of this disclosure, a flag indicating whether inter-slice is allowed can be signaled in a layered manner. A flag, such as `sps_inter_slice_allowed_flag`, is added to the SPS to indicate whether inter-slice is allowed during encoding and decoding of the picture associated with that SPS. When `sps_inter_slice_allowed_flag` equals 0 (meaning inter-slice is not allowed), the inter-slice allowance flag in the picture header can be omitted when signaling and inferred to be 0. An example of the decoding process for the VVC draft is illustrated in Table 16 below. Changes to the VVC draft are shown in bold and italics.
[0179] Table 16. Proposed Sequence Parameter Set (RBSP) Syntax
[0180]
[0181] 7.4.3.7 Image header structure and semantics
[0182] A value of 0 for `ph_inter_slice_allowed_flag` indicates that all encoded slices in the image have a slice_type of 2. A value of 1 for `ph_inter_slice_allowed_flag` indicates that one or more encoded slices with a slice_type of 0 or 1 may or may not exist in the image. If none exist, it is inferred that the value of `ph_inter_slice_allowed_flag` is 0.
[0183] Figure 4A method for decoding a video signal according to this disclosure is shown. For example, this method can be applied to a decoder.
[0184] In step 410, the decoder may receive at least one VVC syntax flag. This at least one VVC syntax flag may include a first VVC syntax flag indicating whether inter-frame prediction is allowed in the corresponding codec level.
[0185] In step 412, the decoder may receive inter-frame related syntax elements in response to an indication that inter-frame prediction is permitted.
[0186] In step 414, the decoder can obtain a first reference image I associated with a video block in the bitstream. (0) Second reference image I (1) In the order of display, the first reference image I (0) Before the current image and the second reference image I (1) Following the current image.
[0187] In step 416, the decoder can obtain the first reference image I (0) The reference block in the video block obtains the first predicted sample I of the video block. (0) (i, j). i and j represent the coordinates of a sample point in the current image.
[0188] In step 418, the decoder can obtain the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i, j).
[0189] In step 420, the decoder can base its work on at least one VVC syntax flag, inter-frame correlation syntax element, and first prediction sample I. (0) (i, j) and the second predicted sample I (1) (i, j) are used to obtain bidirectional prediction samples.
[0190] Grouping inter-frame related syntax elements
[0191] This disclosure proposes a rearrangement of syntax elements such that inter-frame prediction-related syntax elements are grouped according to VVC syntax at a certain codec level (e.g., sequence, picture, and / or stripe level). According to this disclosure, a rearrangement of syntax elements related to inter-frame stripes in the Sequence Parameter Set (SPS) is proposed. An example of the decoding process for the VVC draft is illustrated in Table 17 below. Changes to the VVC draft are shown below. Added portions are shown in bold and italic font, while deleted portions are shown in strikethrough font.
[0192] Table 17. Proposed Sequence Parameter Set (RBSP) Syntax
[0193]
[0194]
[0195]
[0196]
[0197]
[0198]
[0199]
[0200]
[0201] Figure 5 A method for decoding a video signal according to this disclosure is shown. For example, this method can be applied to a decoder.
[0202] In step 510, the decoder may receive SPS-level permutation partition constraint syntax elements. These permutation partition constraint syntax elements are arranged such that inter-frame prediction related syntax elements are grouped according to VVC syntax at the codec level.
[0203] In step 512, the decoder can obtain a first reference image I associated with a video block in the bitstream. (0) Second reference image I (1) In the order of display, the first reference image I (0) Before the current image and the second reference image I (1) Following the current image.
[0204] In step 514, the decoder can obtain the first reference image I (0) The reference block in the video block obtains the first predicted sample I of the video block. (0) (i, j). i and j represent the coordinates of a sample point in the current image.
[0205] In step 516, the decoder can obtain the second reference image I. (1) The reference block in the video block obtains the second prediction sample I of the video block. (1) (i, j).
[0206] In step 518, the decoder can perform the following based on the permutation of partition constraint syntax elements and the first predicted sample I. (0) (i, j) and the second predicted sample I (1) (i, j) are used to obtain bidirectional prediction samples.
[0207] Table 18 below illustrates another example of the decoding process for the VVC draft. Changes to the VVC draft are shown below. Added sections are shown in bold and italic font, while deleted sections are shown in strikethrough font.
[0208] Table 18. Proposed Sequence Parameter Set (RBSP) Syntax
[0209]
[0210]
[0211]
[0212]
[0213]
[0214]
[0215]
[0216]
[0217] According to this disclosure, it is also proposed to add flags in the VVC syntax at specific codec levels to indicate whether inter-frame slices, such as P-slices and B-slices, are allowed in sequences, pictures, and / or slices. If inter-frame slices are not allowed, the inter-frame slice-related syntax is not signaled in the corresponding codec level (e.g., sequence, picture, and / or slice level). In one example, according to the method of this disclosure, the flag `sps_inter_slice_allowed_flag` is added to the SPS to indicate whether inter-frame slices are allowed during the encoding and decoding of the current video sequence. If not allowed, the inter-frame slice-related syntax elements are not signaled in the SPS. An example of the decoding process for the VVC draft is illustrated in Table 19 below. Added portions are shown in bold and italic font, while deleted portions are shown in strikethrough font.
[0218] Table 19. Proposed Sequence Parameter Set (RBSP) Syntax
[0219]
[0220]
[0221]
[0222]
[0223]
[0224]
[0225]
[0226]
[0227] Table 20 below illustrates another example of the decoding process for the VVC draft. Changes to the VVC draft are shown below. Added sections are shown in bold and italic font, while deleted sections are shown in strikethrough font.
[0228] Table 20. Proposed Sequence Parameter Set RBSP Method
[0229]
[0230]
[0231]
[0232]
[0233]
[0234]
[0235]
[0236]
[0237] Figure 6 A method for decoding a video signal according to this disclosure is shown. For example, this method can be applied to a decoder.
[0238] In step 610, the decoder may receive a bitstream including VPS, SPS, PPS, picture header, and stripe header for the encoded video data.
[0239] In step 612, the decoder can decode the VPS.
[0240] In step 614, the decoder can decode the SPS and obtain the SPS-level permutation partition constraint syntax elements.
[0241] In step 616, the decoder can decode the PPS.
[0242] In step 618, the decoder can decode the image header.
[0243] In step 620, the decoder can decode the stripe header.
[0244] In step 622, the decoder can decode the video data based on VPS, SPS, PPS, image header, and stripe header.
[0245] The methods described above can be implemented using an apparatus comprising one or more circuits, including application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. The apparatus can be used in conjunction with other hardware or software components for performing the methods described above. Each module, submodule, unit, or subunit disclosed above can be implemented at least partially using the one or more circuits.
[0246] Figure 7 A computing environment 710 coupled to a user interface 760 is shown. The computing environment 710 may be part of a data processing server. The computing environment 710 includes a processor 720, memory 740, and I / O interface 750.
[0247] Processor 720 typically controls the overall operation of computing environment 710, such as operations associated with display, data acquisition, data communication, and image processing. Processor 720 may include one or more processors to execute instructions to perform all or some of the steps described above. Furthermore, processor 720 may include one or more modules that facilitate interaction between processor 720 and other components. The processor may be a central processing unit (CPU), microprocessor, microcontroller, GPU, etc.
[0248] Memory 740 is configured to store various types of data to support the operation of computing environment 710. Memory 740 may include predefined software 742. Examples of such data include instructions for any application or method operating on computing environment 710, video datasets, image data, etc. Memory 740 can be implemented using any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0249] I / O interface 750 provides an interface between processor 720 and peripheral interface modules (such as keyboard, click wheel, buttons, etc.). Buttons may include, but are not limited to, home button, start scan button, and stop scan button. I / O interface 750 can be coupled to encoder and decoder.
[0250] In some embodiments, a non-transitory computer-readable storage medium is also provided, which includes a plurality of programs, such as those included in memory 740, which can be executed by processor 720 in computing environment 710 to perform the methods described above. For example, the non-transitory computer-readable storage medium may be ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
[0251] The non-transitory computer-readable storage medium stores a plurality of programs for execution by a computing device having one or more processors, wherein the plurality of programs, when executed by the one or more processors, cause the computing device to perform the motion prediction method described above.
[0252] In some embodiments, the computing environment 710 may be implemented using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), graphics processing units (GPUs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.
[0253] Considering the specification and practice of the disclosure herein, other examples of this disclosure will be apparent to those skilled in the art. This application is intended to cover any changes, uses, or adaptations of the disclosure made in accordance with its general principles, including deviations from this disclosure within the scope of known or customary practice in the art. The specification and examples are intended to be illustrative only.
[0254] It should be understood that this disclosure is not limited to the exact examples shown in the description and figures above, and various modifications and changes can be made without departing from its scope.
Claims
1. A method for decoding a video signal, comprising: The decoder receives inter-frame prediction related syntax elements at the SPS level of the sequence parameter set, wherein the inter-frame prediction related syntax elements are arranged sequentially at the codec level, and wherein the inter-frame prediction related syntax elements are arranged in the following manner: Send the sps_weighted_pred_flag flag using a signal; Send the sps_weighted_bipred_flag flag using a signal; Send the sps_mmvd_enabled_flag flag using a signal; Set the value of the six_minus_max_num_merge_cand syntax element; and Set the value of the log2_parallel_merge_level_minus2 syntax element. Specifically, the `sps_weighted_pred_flag` flag being equal to 1 indicates that weighted prediction can be applied to the P-strips referencing the SPS; the `sps_weighted_pred_flag` flag being equal to 0 indicates that the weighted prediction is not applied to the P-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 1 indicates that explicit weighted prediction can be applied to the B-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 0 indicates that the explicit weighted prediction is not applied to the B-strips referencing the SPS; and the `sps_mmvd_enabled_flag` flag being equal to 1 indicates that the merging mode with motion vector differences is enabled. The `sps_mmvd_enabled_flag` flag being equal to 0 indicates that the merging mode with motion vector differences is disabled; the `six_minus_max_num_merge_cand` syntax element specifies the maximum number of merging motion vector prediction candidates supported in SPS, subtracted from 6; and the `log2_parallel_merge_level_minus2` syntax element plus 2 specifies the value of the variable `Log2ParMrgLevel`, which is used in at least one of the following processes: the process of obtaining spatial merging candidates, the process of obtaining motion vectors and reference indices in the sub-block merging mode, and the invocation of a process that controls the updating of the list of historical motion vector prediction values. The decoder obtains a first reference image and a second reference image associated with a video block in the bitstream, wherein, in display order, the first reference image precedes the current image and the second reference image follows the current image, and wherein the video block is associated with a segmentation method, the segmentation method including quadrilateral partitioning, horizontal binary partitioning, vertical binary partitioning, horizontal ternary partitioning, or vertical ternary partitioning. The decoder obtains the first predicted sample of the video block from the first reference image; The decoder obtains the second predicted sample of the video block from the second reference image; and The decoder obtains bidirectional prediction samples based on at least one of the inter-frame prediction correlation syntax elements, the first prediction sample, and the second prediction sample. The method further includes: Following the log2_parallel_merge_level_minus2 syntax element, the sps_isp_enabled_flag flag is received, wherein an sps_isp_enabled_flag flag of 1 indicates that intra-prediction with sub-partitions is enabled, and an sps_isp_enabled_flag flag of 0 indicates that intra-prediction with sub-partitions is disabled.
2. The method of claim 1, further comprising: The system continuously receives the `sps_wpp_entry_point_offsets_present_flag` flag and `log2_max_pic_order_cnt_lsb_minus4`, where `sps_wpp_entry_point_offsets_present_flag` equal to 1 indicates that the signal for the entry point offset of the CTU line may exist in the strip header of the image referencing SPS, and `sps_wpp_entry_point_offsets_present_flag` equal to 0 indicates that the signal for the entry point offset of the CTU line does not exist in the strip header of the image referencing SPS. The `log2_max_pic_order_cnt_lsb_minus4` syntax element specifies the value of the variable `MaxPicOrderCntLSb` used in the decoding process for image order counting. .
3. The method of claim 2, wherein receiving the inter-frame prediction related syntax elements includes: After log2_max_pic_order_cnt_lsb_minus4, the sps_weighted_pred_flag flag is received.
4. The method of claim 1, wherein the bit depth of the sample points of the video signal is in the range of 8 to 16 including the endpoints.
5. The method of claim 1, wherein the chroma format of the video signal is 4:4:
4.
6. A computing device, comprising: One or more processors; as well as A non-transitory computer-readable storage medium storing instructions executable by the one or more processors, wherein the one or more processors are configured to: Receive inter-frame prediction related syntax elements at the SPS level of the sequence parameter set, wherein the inter-frame prediction related syntax elements are arranged sequentially at the codec level, and wherein the inter-frame prediction related syntax elements are arranged in the following manner: Send the sps_weighted_pred_flag flag using a signal; Send the sps_weighted_bipred_flag flag using a signal; Send the sps_mmvd_enabled_flag flag using a signal; Set the value of the six_minus_max_num_merge_cand syntax element; and Set the value of the log2_parallel_merge_level_minus2 syntax element. Specifically, the `sps_weighted_pred_flag` flag being equal to 1 indicates that weighted prediction can be applied to the P-strips referencing the SPS; the `sps_weighted_pred_flag` flag being equal to 0 indicates that the weighted prediction is not applied to the P-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 1 indicates that explicit weighted prediction can be applied to the B-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 0 indicates that the explicit weighted prediction is not applied to the B-strips referencing the SPS; and the `sps_mmvd_enabled_flag` flag being equal to 1 indicates that the merging mode with motion vector differences is enabled. The `sps_mmvd_enabled_flag` flag being equal to 0 indicates that the merging mode with motion vector differences is disabled; the `six_minus_max_num_merge_cand` syntax element specifies the maximum number of merging motion vector prediction candidates supported in SPS, subtracted from 6; and the `log2_parallel_merge_level_minus2` syntax element plus 2 specifies the value of the variable `Log2ParMrgLevel`, which is used in at least one of the following processes: the process of obtaining spatial merging candidates, the process of obtaining motion vectors and reference indices in the sub-block merging mode, and the invocation of a process that controls the updating of the list of historical motion vector prediction values. Obtain a first reference image and a second reference image associated with a video block in a bitstream, wherein, in display order, the first reference image precedes the current image and the second reference image follows the current image, and wherein the video block is associated with a segmentation method, the segmentation method including quadrilateral partitioning, horizontal binary partitioning, vertical binary partitioning, horizontal ternary partitioning, or vertical ternary partitioning. The first predicted sample points of the video block are obtained from the first reference image; Obtain the second predicted sample points of the video block from the second reference image; and Bidirectional prediction samples are obtained based on at least one of the inter-frame prediction correlation syntax elements, the first prediction sample, and the second prediction sample. Wherein, the one or more processors are further configured to: Following the log2_parallel_merge_level_minus2 syntax element, the sps_isp_enabled_flag flag is received, wherein an sps_isp_enabled_flag flag of 1 indicates that intra-prediction with sub-partitions is enabled, and an sps_isp_enabled_flag flag of 0 indicates that intra-prediction with sub-partitions is disabled.
7. The computing device of claim 6, wherein the one or more processors are further configured to: It continuously receives the `sps_wpp_entry_point_offsets_present_flag` flag and `log2_max_pic_order_cnt_lsb_minus4`, where... The `sps_wpp_entry_point_offsets_present_flag` flag being equal to 1 indicates that the signal for the entry point offset of the CTU line can exist in the strip header of the image referencing SPS. The `sps_wpp_entry_point_offsets_present_flag` flag being equal to 0 indicates that the signal for the entry point offset of the CTU line does not exist in the strip header of the image referencing SPS. The `log2_max_pic_order_cnt_lsb_minus4` syntax element specifies the value of the variable `MaxPicOrderCntLSb` used in the decoding process for image order counting. .
8. The computing device of claim 7, wherein receiving the inter-frame prediction related syntax element comprises: After log2_max_pic_order_cnt_lsb_minus4, the sps_weighted_pred_flag flag is received.
9. The computing device of claim 6, wherein the bit depth of the sample points of the video signal is in the range of 8 to 16 including the endpoints.
10. The computing device of claim 6, wherein the chroma format of the video signal is 4:4:
4.
11. A computer-readable storage medium storing a bit stream formed by instructions, which, when executed by a computing device having one or more processors, cause the one or more processors to perform actions including: The decoder receives the bitstream and obtains the SPS-level inter-frame prediction related syntax elements from the bitstream, wherein... The inter-frame prediction related syntax elements are arranged sequentially at the codec level, and wherein the inter-frame prediction related syntax elements are arranged in the following manner: Send the sps_weighted_pred_flag flag using a signal; Send the sps_weighted_bipred_flag flag using a signal; Send the sps_mmvd_enabled_flag flag using a signal; Set the value of the six_minus_max_num_merge_cand syntax element; and Set the value of the log2_parallel_merge_level_minus2 syntax element. Specifically, the `sps_weighted_pred_flag` flag being equal to 1 indicates that weighted prediction can be applied to the P-strips referencing the SPS; the `sps_weighted_pred_flag` flag being equal to 0 indicates that the weighted prediction is not applied to the P-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 1 indicates that explicit weighted prediction can be applied to the B-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 0 indicates that the explicit weighted prediction is not applied to the B-strips referencing the SPS; and the `sps_mmvd_enabled_flag` flag being equal to 1 indicates that the merging mode with motion vector differences is enabled. The `sps_mmvd_enabled_flag` flag being equal to 0 indicates that the merging mode with motion vector differences is disabled; the `six_minus_max_num_merge_cand` syntax element specifies the maximum number of merging motion vector prediction candidates supported in SPS, subtracted from 6; and the `log2_parallel_merge_level_minus2` syntax element plus 2 specifies the value of the variable `Log2ParMrgLevel`, which is used in at least one of the following processes: the process of obtaining spatial merging candidates, the process of obtaining motion vectors and reference indices in the sub-block merging mode, and the invocation of a process that controls the updating of the list of historical motion vector prediction values. The decoder obtains a first reference image and a second reference image associated with a video block in the bitstream, wherein, in display order, the first reference image precedes the current image and the second reference image follows the current image, and wherein the video block is associated with a segmentation method, the segmentation method including quadrilateral partitioning, horizontal binary partitioning, vertical binary partitioning, horizontal ternary partitioning, or vertical ternary partitioning. The decoder obtains the first predicted sample of the video block from the first reference image; The decoder obtains the second predicted sample of the video block from the second reference image; and The decoder obtains bidirectional prediction samples based on at least one of the inter-frame prediction correlation syntax elements, the first prediction sample, and the second prediction sample. The instructions further cause the one or more processors to execute: Following the log2_parallel_merge_level_minus2 syntax element, the sps_isp_enabled_flag flag is received, wherein an sps_isp_enabled_flag flag of 1 indicates that intra-prediction with sub-partitions is enabled, and an sps_isp_enabled_flag flag of 0 indicates that intra-prediction with sub-partitions is disabled.
12. The computer-readable storage medium of claim 11, wherein, The instruction further causes the one or more processors to execute: The system continuously receives the `sps_wpp_entry_point_offsets_present_flag` flag and `log2_max_pic_order_cnt_lsb_minus4`, where `sps_wpp_entry_point_offsets_present_flag` equal to 1 indicates that the signal for the entry point offset of the CTU line may exist in the strip header of the image referencing SPS, and `sps_wpp_entry_point_offsets_present_flag` equal to 0 indicates that the signal for the entry point offset of the CTU line does not exist in the strip header of the image referencing SPS. The `log2_max_pic_order_cnt_lsb_minus4` syntax element specifies the value of the variable `MaxPicOrderCntLSb` used in the decoding process for image order counting. .
13. The computer-readable storage medium of claim 12, wherein, The instruction further causes the one or more processors to execute: After log2_max_pic_order_cnt_lsb_minus4, the sps_weighted_pred_flag flag is received.
14. The computer-readable storage medium of claim 11, wherein the bit depth of the sample points of the video signal is in the range of 8 to 16 including the endpoints.
15. The computer-readable storage medium of claim 11, wherein the chroma format of the video signal is 4:4:
4.
16. A computer program product comprising a plurality of programs for execution by a computing device having one or more processors, wherein, when executed by the one or more processors, the computing device receives a bit stream and performs the method of any one of claims 1 to 5 based on the bit stream.
17. A method for storing a bit stream, comprising: Perform the encoding method to generate a bitstream; as well as Store the bit stream, The encoding method includes: Inter-frame prediction related syntax elements are generated at the SPS level for the sequence parameter set, wherein the inter-frame prediction related syntax elements are arranged sequentially at the codec level, and wherein the inter-frame prediction related syntax elements are arranged in the following manner: Send the sps_weighted_pred_flag flag using a signal; Send the sps_weighted_bipred_flag flag using a signal; Send the sps_mmvd_enabled_flag flag using a signal; Set the value of the six_minus_max_num_merge_cand syntax element; and Set the value of the log2_parallel_merge_level_minus2 syntax element. Specifically, the `sps_weighted_pred_flag` flag being equal to 1 indicates that weighted prediction can be applied to the P-strips referencing the SPS; the `sps_weighted_pred_flag` flag being equal to 0 indicates that the weighted prediction is not applied to the P-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 1 indicates that explicit weighted prediction can be applied to the B-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 0 indicates that the explicit weighted prediction is not applied to the B-strips referencing the SPS; and the `sps_mmvd_enabled_flag` flag being equal to 1 indicates that the merging mode with motion vector differences is enabled. The `sps_mmvd_enabled_flag` flag being equal to 0 indicates that the merging mode with motion vector differences is disabled; the `six_minus_max_num_merge_cand` syntax element specifies the maximum number of merging motion vector prediction candidates supported in SPS, subtracted from 6; and the `log2_parallel_merge_level_minus2` syntax element plus 2 specifies the value of the variable `Log2ParMrgLevel`, which is used in at least one of the following processes: the process of obtaining spatial merging candidates, the process of obtaining motion vectors and reference indices in the sub-block merging mode, and the invocation of a process that controls the updating of the list of historical motion vector prediction values. Obtain a first reference image and a second reference image associated with a video block, wherein, in display order, the first reference image precedes the current image and the second reference image follows the current image; The first predicted sample points of the video block are obtained from the first reference image; Obtain the second predicted sample points of the video block from the second reference image; and Bidirectional prediction samples are obtained based on at least one of the inter-frame prediction correlation syntax elements, the first prediction sample, and the second prediction sample. The encoding method further includes: Following the log2_parallel_merge_level_minus2 syntax element, the sps_isp_enabled_flag flag is determined, wherein an sps_isp_enabled_flag flag of 1 indicates that intra-prediction with sub-partitions is enabled, and an sps_isp_enabled_flag flag of 0 indicates that intra-prediction with sub-partitions is disabled.
18. The method of claim 17, wherein the bit depth of the sample points of the video signal is in the range of 8 to 16 including the endpoints.
19. The method of claim 17, wherein the chroma format of the video signal is 4:4:
4.
20. A method for encoding a video signal, comprising: Inter-frame prediction related syntax elements are generated at the SPS level for the sequence parameter set, wherein the inter-frame prediction related syntax elements are arranged sequentially at the codec level, and wherein the inter-frame prediction related syntax elements are arranged in the following manner: Send the sps_weighted_pred_flag flag using a signal; Send the sps_weighted_bipred_flag flag using a signal; Send the sps_mmvd_enabled_flag flag using a signal; Set the value of the six_minus_max_num_merge_cand syntax element; and Set the value of the log2_parallel_merge_level_minus2 syntax element. Specifically, the `sps_weighted_pred_flag` flag being equal to 1 indicates that weighted prediction can be applied to the P-strips referencing the SPS; the `sps_weighted_pred_flag` flag being equal to 0 indicates that the weighted prediction is not applied to the P-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 1 indicates that explicit weighted prediction can be applied to the B-strips referencing the SPS; the `sps_weighted_bipred_flag` flag being equal to 0 indicates that the explicit weighted prediction is not applied to the B-strips referencing the SPS; and the `sps_mmvd_enabled_flag` flag being equal to 1 indicates that the merging mode with motion vector differences is enabled. The `sps_mmvd_enabled_flag` flag being equal to 0 indicates that the merging mode with motion vector differences is disabled; the `six_minus_max_num_merge_cand` syntax element specifies the maximum number of merging motion vector prediction candidates supported in SPS, subtracted from 6; and the `log2_parallel_merge_level_minus2` syntax element plus 2 specifies the value of the variable `Log2ParMrgLevel`, which is used in at least one of the following processes: the process of obtaining spatial merging candidates, the process of obtaining motion vectors and reference indices in the sub-block merging mode, and the invocation of a process that controls the updating of the list of historical motion vector prediction values. Obtain a first reference image and a second reference image associated with a video block, wherein, in display order, the first reference image precedes the current image and the second reference image follows the current image; The first predicted sample points of the video block are obtained from the first reference image; Obtain the second predicted sample points of the video block from the second reference image; and Bidirectional prediction samples are obtained based on at least one of the inter-frame prediction correlation syntax elements, the first prediction sample, and the second prediction sample. The method further includes: Following the log2_parallel_merge_level_minus2 syntax element, the sps_isp_enabled_flag flag is determined, wherein an sps_isp_enabled_flag flag of 1 indicates that intra-prediction with sub-partitions is enabled, and an sps_isp_enabled_flag flag of 0 indicates that intra-prediction with sub-partitions is disabled.
21. The method of claim 20, wherein the bit depth of the sample points of the video signal is in the range of 8 to 16 including the endpoints.
22. The method of claim 20, wherein the chroma format of the video signal is 4:4:4.