A fence device and its manufacturing method

Abstract

This application provides a gate-all-around device and its manufacturing method, comprising: providing a substrate; forming a buffer layer with a first doping on the substrate; the buffer layer including a first doped region and a second doped region located above the first doped region, wherein the doping concentration of the first doped region is a first doping concentration, the doping concentration of the second doped region is a second doping concentration, and the first doping concentration is higher than the second doping concentration; forming a stacked layer of alternating first epitaxial layers and second epitaxial layers on the buffer layer; forming fins in the stacked layer, the buffer layer, and the substrate, wherein the middle part of the fin is a channel region; removing the first epitaxial layer in the channel region and forming a gate surrounding the second epitaxial layer in the channel region. Thus, the first doped region with a higher doping concentration can suppress the off-state leakage current of the sub-fin parasitic silicon channel, and the second doped region with a lower doping concentration can suppress the tunneling current between the sub-fin parasitic silicon channel and the source / drain region, thereby maximizing the suppression of device leakage current in the off-state and improving device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and their manufacturing, and in particular to a gate-around device and its manufacturing method. Background Technology

[0002] As integrated circuit feature sizes continue to shrink, traditional triple-gate or double-gate FinFETs are limited below 3nm. Gate-all-around (GAA) FETs, compatible with mainstream high-k metal-gate FinFET processes, will be the next key structure for achieving size miniaturization. The channel of a GAA FET is primarily a stacked nanosheet structure. However, the presence of a sub-Fin parasitic silicon channel in the GAA FET substrate cannot completely suppress leakage current in the off-state, leading to a sharp increase in off-state leakage current. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a gate-around device and a method for manufacturing the same, thereby maximally suppressing device leakage current in the off-state and improving device performance. The specific solution is as follows:

[0004] In a first aspect, this application provides a method for manufacturing a gate device, comprising:

[0005] Provide substrate;

[0006] A buffer layer with a first doping is formed on the substrate; the buffer layer includes a first doped region and a second doped region located above the first doped region, the doping concentration of the first doped region is a first doping concentration, the doping concentration of the second doped region is a second doping concentration, and the first doping concentration is higher than the second doping concentration;

[0007] A stacked layer of alternating first and second epitaxial layers is formed on the buffer layer;

[0008] Fins are formed in the stacked layer, the buffer layer, and the substrate; the central part of the fin is a channel region;

[0009] The first epitaxial layer in the channel region is removed, and a gate surrounding the second epitaxial layer in the channel region is formed.

[0010] Secondly, embodiments of this application also provide a surrounding fence device, comprising:

[0011] Substrate;

[0012] A buffer layer with a first doping is located on the substrate; the buffer layer includes a first doped region and a second doped region located above the first doped region, the doping concentration of the first doped region is a first doping concentration, the doping concentration of the second doped region is a second doping concentration, and the first doping concentration is higher than the second doping concentration;

[0013] A fin located on the substrate; the fin comprises a substrate of a certain thickness, a buffer layer, and a second epitaxial layer arranged at intervals along the direction perpendicular to the substrate, wherein the second epitaxial layer is a channel region;

[0014] The source / drain regions with second doping are connected to both ends of the second epitaxial layer, and the first doping and the second doping have opposite doping types;

[0015] The gate surrounding the second epitaxial layer.

[0016] This application provides a gate-all-around device and its manufacturing method, comprising: providing a substrate; forming a buffer layer with a first doping on the substrate; the buffer layer including a first doped region and a second doped region located above the first doped region, the first doped region having a first doping concentration and the second doped region having a second doping concentration, the first doping concentration being higher than the second doping concentration; forming a stacked layer of alternating first and second epitaxial layers on the buffer layer; forming a fin in the stacked layer, the buffer layer, and the substrate, the middle of the fin being a channel region; removing the first epitaxial layer in the channel region and forming a gate surrounding the second epitaxial layer in the channel region. Thus, the first doped region with a higher doping concentration can suppress the off-state leakage current of the sub-fin parasitic silicon channel, and the second doped region with a lower doping concentration can suppress the tunneling current between the sub-fin parasitic silicon channel and the source / drain region, thereby maximizing the suppression of device leakage current in the off-state and improving device performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic flowchart of a method for manufacturing a fence device according to an embodiment of this application is shown;

[0019] Figure 2 This illustration shows a schematic diagram of a structure for forming a buffer layer on a substrate according to an embodiment of this application;

[0020] Figure 3This illustration shows a schematic diagram of a structure for forming a multilayer buffer layer on a substrate, according to an embodiment of this application.

[0021] Figure 4-11B A schematic diagram of the structure during the formation of the gate device provided in the embodiments of this application is shown. Detailed Implementation

[0022] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0023] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0024] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0025] As described in the background section, the presence of sub-fin parasitic silicon channels in the GAA-FET substrate makes it impossible to completely suppress leakage current in the off-state, resulting in a sharp increase in device leakage current in the off-state.

[0026] Based on the above technical problems, this application provides a gate-all-around device and its manufacturing method, comprising: providing a substrate; forming a buffer layer with a first doping on the substrate; the buffer layer including a first doped region and a second doped region located above the first doped region, wherein the doping concentration of the first doped region is the first doping concentration, the doping concentration of the second doped region is the second doping concentration, and the first doping concentration is higher than the second doping concentration; forming a stacked layer of alternating first epitaxial layers and second epitaxial layers on the buffer layer; forming fins in the stacked layer, the buffer layer, and the substrate, wherein the middle part of the fin is a channel region; removing the first epitaxial layer in the channel region and forming a gate surrounding the second epitaxial layer in the channel region. Thus, the first doped region with a higher doping concentration can suppress the off-state leakage current of the sub-fin parasitic silicon channel, and the second doped region with a lower doping concentration can suppress the tunneling current between the sub-fin parasitic silicon channel and the source / drain region, thereby maximizing the suppression of device leakage current in the off-state and improving device performance.

[0027] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides an embodiment of a fencing device and its manufacturing method.

[0028] refer to Figure 1The diagram shown is a flowchart illustrating a method for manufacturing a fence device according to an embodiment of this application. The method may include the following steps.

[0029] S101 provides a substrate.

[0030] In this embodiment of the application, a substrate 100 may be provided, for reference Figure 2 The diagram shown illustrates a structure for forming a buffer layer on a substrate according to an embodiment of this application. The substrate can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the substrate can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). In this embodiment, the substrate 100 can be a silicon substrate.

[0031] S102, a buffer layer with a first doping is formed on the substrate.

[0032] In the embodiments of this application, reference is made to Figure 2 As shown, a buffer layer 101 can be formed on the substrate 100. The buffer layer 101 has a first doping and includes a first doped region 1011 and a second doped region 1012 located above the first doped region. The doping concentration of the first doped region 1011 is the first doping concentration, and the doping concentration of the second doped region 1012 is the second doping concentration. The first doping concentration can be higher than the second doping concentration. In this way, the first doped region with a higher doping concentration can suppress the off-state leakage current of the sub-Fin parasitic silicon channel, and the second doped region with a lower doping concentration can suppress the tunneling current between the sub-Fin parasitic silicon channel and the source / drain region, thereby maximizing the suppression of device leakage current in the off-state and improving device performance.

[0033] Specifically, in-situ doping can be performed simultaneously with the epitaxial growth of the buffer layer to form a buffer layer with the first dopant. Alternatively, the buffer layer can be epitaxially grown first, followed by ion implantation to induce the first dopant in the buffer layer. Both the first and second doping concentrations can be greater than or equal to 1e15 cm⁻¹. -3 And less than or equal to 1e19cm -3 The first doping concentration is higher than the second doping concentration.

[0034] In this embodiment of the application, when a buffer layer 101 with a first doping is formed on the substrate 100, in the NMOS region, the material of the buffer layer includes at least one of the following materials: Si:B, Ge:B, SiGex:B, GeSn:B, SiSn:B. That is, the doping type of the first doping is P-type. The doping particles of P-type doping can be not only B, but also Al, Ga or In, etc. For example, the material of the buffer layer can be Si:Al.

[0035] In the embodiments of this application, in the PMOS region, the material of the buffer layer includes at least one of the following materials: Si:P, Ge:P, SiGex:P, GeSn:P, SiSn:P. In this case, the first doping type is N-type, and the doping particles of N-type doping can be not only P, but also N, As, S, etc.

[0036] It is understandable that when forming a buffer layer in a CMOS device, the buffer layer can be formed in part of the NMOS region and part of the PMOS region, and the region where the buffer layer is formed can be set according to actual needs.

[0037] In this embodiment, the thickness of the buffer layer 101 can be greater than or equal to 2 nm and less than or equal to 20 nm, thereby both suppressing device leakage and avoiding process waste. The thickness of the first doped region 1011 can be greater than the thickness of the second doped region 1012, as shown in the reference. Figure 2 As shown, the first doped region 1011 and the second doped region 1012 are distinguished by dashed lines, and the thickness of the first doped region 1011 is greater than the thickness of the second doped region 1012.

[0038] In one possible implementation, multiple buffer layers 101 can be formed on the substrate. The first doped region 1011 includes multiple buffer layers 101, and the second doped region 1012 can include one or more buffer layers 101, thereby better suppressing device leakage current. By controlling the doping concentration of each layer in the multiple buffer layers, the doping concentration of the first doped region and the second doped region can be reasonably controlled, so that the doping concentration variation in the first doped region is small, the doping concentration variation in the second doped region is small, and the doping concentration variation in the contact area between the first doped region and the second doped region is large, that is, the difference between the first doping concentration and the second doping concentration is large, thereby forming a steep heavy doping distribution in the multiple buffer layers, suppressing the off-state leakage current of the sub-Fin parasitic silicon channel, as well as the tunneling current between the sub-Fin parasitic silicon channel and the source / drain region.

[0039] refer to Figure 3The diagram shown is a schematic representation of a multilayer buffer layer structure formed on a substrate according to an embodiment of this application. Five buffer layers 101 are formed on the substrate 100, with three buffer layers in the first doped region 1011 and two buffer layers in the second doped region 1012. In subsequent diagrams, a single buffer layer is used as an example; however, in practical applications, multiple buffer layers can be configured according to actual needs.

[0040] In this embodiment, after the buffer layer is formed, the first dopant in the buffer layer can be activated by annealing. During annealing, the first dopant in the buffer layer can also diffuse into the substrate.

[0041] S103, forming a stacked layer on the buffer layer with alternating layers of the first epitaxial layer and the second epitaxial layer.

[0042] In this embodiment, a stacked layer 110 of alternating first epitaxial layer 102 and second epitaxial layer 104 can be formed on the buffer layer, wherein the second epitaxial layer is a channel material, as shown in the reference. Figure 4 As shown.

[0043] Specifically, an alternating first epitaxial layer 102 and a second epitaxial layer 104 are sequentially formed by epitaxial growth, wherein the first epitaxial layer 102 is a sacrificial layer and the second epitaxial layer 104 is formed using a channel material as a channel. The first epitaxial layer 102 will be removed subsequently, thereby releasing the second epitaxial layer 104 as a channel so that a gate surrounding the second epitaxial layer 104 can be formed.

[0044] Specifically, the materials of the first epitaxial layer 102 and the second epitaxial layer 104 can be determined according to the specific requirements of the process and the device. For example, an epitaxial layer with a crystal orientation similar to that of the semiconductor substrate can be epitaxial. In this embodiment, the first epitaxial layer 102 can be a germanium-based film layer, which may include an epitaxial germanium layer, an epitaxial silicon-germanium layer, or a combination thereof. The second epitaxial layer 104 can be an epitaxial silicon layer. The epitaxial process can be vacuum epitaxy or molecular beam epitaxy, etc.

[0045] S104 forms fins in the stacked layers, buffer layer, and substrate; the middle of the fin is the channel region.

[0046] In this embodiment, fins can be formed in the stacked layer 110, the buffer layer 101, and the substrate 100, with the central portion of the fin being a channel region, as shown in the reference. Figure 5 and Figure 5AAs shown, the stacked layer 110, buffer layer 101, and a partial thickness of substrate 100 can be patterned to form a fin 120 within the stacked layer 110, buffer layer 101, and partial thickness of substrate 100. The fin 120 includes a bottom layer of patterned substrate 100, buffer layer 101, and stacked layer 110. The central region of the patterned fin 120 is the channel region, referring to the middle section of the fin along its extension direction, where a gate will be formed.

[0047] S105, the first epitaxial layer in the channel region is removed, and a gate surrounding the second epitaxial layer in the channel region is formed.

[0048] In this embodiment, the first epitaxial layer in the channel region can be removed to form a gate surrounding the second epitaxial layer in the channel region, as shown in the reference. Figure 11 , Figure 11A and Figure 11B As shown. Specifically, a back-gate process can be used to form other structures of the device, or other suitable processes can be used to form other structures of the device.

[0049] In the back gate process, before removing the first epitaxial layer in the channel region, fins can be used to form source and drain regions with second doping at both ends of the channel region, with the first and second doping having opposite doping types.

[0050] In one possible implementation, shallow trench isolation (STI) is provided between any two adjacent device cells to isolate them. An isolation layer 122 can be formed on both sides of the fin substrate 100 and the buffer layer 101. Specifically, a low-temperature insulating dielectric, such as silicon oxide, can be deposited, followed by low-temperature annealing and chemical mechanical polishing (CMP) to etch back the silicon oxide isolation material. For example, wet etching can be used to remove a certain thickness of isolation material using hydrofluoric acid etching, leaving the remaining isolation material as isolation layer 122. (Refer to...) Figure 6 As shown. Next, the surface of the fin 120 covering the channel region is used to form a dummy gate 130, as shown in the figure. Figure 7 (Top view) and Figure 7A ( Figure 7 As shown in the AA-direction cross-sectional view.

[0051] Sidewalls 134 are formed on the sidewalls of the dummy gate 130, and source / drain regions 132 with second doping are formed at both ends of the channel region using fins. (Refer to...) Figure 9 (Top view) and Figure 9 ( Figure 9 (AA section view) Figure 9B ( Figure 9The BB-directed sectional view is shown.

[0052] In the embodiments of this application, the regions at both ends of the fins in the channel region are the source / drain regions. The source / drain regions are formed using fins. In some embodiments, the source / drain regions can be formed directly using the fins 120 at both ends of the channel region. For example, the source / drain regions can be formed by directly doping the fins 120 at both ends of the channel region. Alternatively, the source / drain regions can be formed by etching the fins 120 at both ends of the channel region and then re-forming the epitaxial source / drain regions from the ends of the etched fins. The epitaxial source / drain regions can be formed by in-situ doping or post-doping.

[0053] In this embodiment, a sidewall 134 can first be formed on the sidewall of the dummy gate 130. The sidewall 134 can be a single-layer or multi-layer structure, and can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials and combinations thereof, and / or other suitable materials. Then, a method for reforming the epitaxial source / drain region is used, and before the epitaxial source / drain region is formed, an inner sidewall 124 is formed on the first epitaxial layer 102 in the fin 120 at the end of the channel region, referring to... Figure 8 (Top view) and Figure 8A ( Figure 8 As shown in the BB-direction cross-sectional view, the inner wall 124 can prevent the drilling and erosion of the source and drain regions during the subsequent removal of the first epitaxial layer 102, thereby improving the quality of the source and drain regions and thus improving the performance of the device.

[0054] Specifically, this includes: removing the stacked layer 110 in the fin 120 that is not covered by the dummy gate 130 and sidewall 134; forming an inner sidewall 124 on the first epitaxial layer 102 at the end of the fin 120 in the channel region; and performing epitaxial growth at the end of the fin 120 in the channel region to form a source / drain region 132.

[0055] After the exposed stacked layer 110 is etched away using an etching process, the end of the stacked layer 110 in the channel region will be exposed. A portion of the first epitaxial layer 102 can be selectively etched away, and a dielectric material can be filled into the selectively removed portion to form the inner sidewall 124. (Refer to...) Figure 8 and Figure 8A As shown, source / drain regions 132 can then be epitaxially grown from the second epitaxial layer 104 at the end of the channel region 120. In-situ doping can be performed during epitaxial growth, and different epitaxial source / drain regions can be formed for different devices. For N-type devices, for example, source / drain regions of epitaxial silicon can be formed, and for P-type devices, for example, source / drain regions of epitaxial silicon germanium can be formed.

[0056] Then, an interlayer dielectric layer 140 is applied over the source / drain region 132, as referenced. Figure 9 and Figure 9A , Figure 9BAs shown. The interlayer dielectric layer 140 can be a single-layer or multi-layer structure, and its material can be, for example, undoped silicon oxide (SiO2), doped silicon oxide (such as borosilicate glass, borosilicate glass, etc.), silicon nitride (Si3N4), or other low-k dielectric materials. After depositing the dielectric material, a planarization process can be performed until the dummy gate 130 is exposed, thereby forming the interlayer dielectric layer 140. Then, the dummy gate 130 is removed to form the opening 142, as shown in the reference. Figure 9 and Figure 9A , Figure 9B As shown. Etching techniques, such as wet etching, can be used to remove the dummy gate 130, and the dummy gate dielectric layer can be further removed to form an opening 142 that exposes the stacked layer 110 of the channel region.

[0057] Next, the first epitaxial layer 102 is removed using opening 142, as shown in the reference. Figure 10A (along Figure 9 (Cross view along the AA direction) Figure 10B (along Figure 9 The cross-sectional view along the BB direction is shown.

[0058] The first epitaxial layer 102 in the exposed stacked layer 110 can be removed by wet etching. Since the ends of the first epitaxial layer 102 have inner sidewalls 124, the acid can be prevented from drilling into the source and drain regions at both ends during the removal process, thus improving the performance of the device. After the first epitaxial layer 102 is removed, the second epitaxial layer 104 is released, and a gate surrounding the second epitaxial layer 104 can then be formed.

[0059] In this embodiment of the application, the channel layer formed by the stacked layers and fins is the second epitaxial layer 104. The second epitaxial layer 104 has a sheet structure and a nanoscale size, also known as a nanosheet channel. Furthermore, the second epitaxial layer 104 can be modified by processes such as thermal oxidation and etching to give it a smoother surface.

[0060] Finally, a gate 150 is formed surrounding the second epitaxial layer 104 in the channel region, as referenced. Figure 11 (Top view) and Figure 11A ( Figure 11 (AA section view) Figure 11B ( Figure 11 (See the BB-directed sectional view). Reference Figure 11B As shown, by forming a first doped region with a first doping concentration on the substrate, the off-state leakage current of the sub-Fin parasitic silicon channel can be suppressed vertically. A second doped region with a lower doping concentration is formed above the first doped region, which can suppress the tunneling current from the source region to the sub-Fin parasitic silicon channel to the drain region laterally. This results in a steep heavy doping distribution in the buffer layer, thereby suppressing device leakage current.

[0061] Before reforming the gate 150, a gate dielectric layer (not shown) may be formed first. Then, the gate 150 is filled and planarized to form the gate 150 surrounding the second epitaxial layer 104. The gate dielectric layer may be a high-k dielectric material (e.g., a material with a high dielectric constant compared to silicon oxide) or other suitable dielectric materials. High-k dielectric materials include one or more of hafnium-based oxides, HFO2, HfSiO, HfSiON, HfTaO, HfTiO, ZrO2, Al2O3, and La2O3. The gate 150 may be a metal gate, and may be a single or multilayer structure. It may include metal materials or polysilicon or combinations thereof. Metal materials include one or more of Ti, TiAlx, TiN, TaNx, HfN, TiCx, TaCx, TiNSi, Al, TiAl, TiAlCx, etc.

[0062] Thus, the gate-around device of this application embodiment is formed. Afterward, other processing techniques of the device can be completed, such as forming gate contacts, source-drain contacts, interconnect layers, passivation layers, etc.

[0063] This application provides a method for manufacturing a gate-all-around device, comprising: providing a substrate; forming a buffer layer having a first doping concentration on the substrate; the buffer layer including a first doped region and a second doped region located above the first doped region, the first doped region having a first doping concentration and the second doped region having a second doping concentration, the first doping concentration being higher than the second doping concentration; forming a stacked layer of alternating first and second epitaxial layers on the buffer layer; forming a fin in the stacked layer, the buffer layer, and the substrate, the middle of the fin being a channel region; removing the first epitaxial layer in the channel region and forming a gate surrounding the second epitaxial layer in the channel region. Thus, the first doped region with a higher doping concentration can suppress the off-state leakage current of the sub-fin parasitic silicon channel, and the second doped region with a lower doping concentration can suppress the tunneling current between the sub-fin parasitic silicon channel and the source / drain region, thereby maximizing the suppression of device leakage current in the off-state and improving device performance.

[0064] Based on the above manufacturing method of the gate device, this application embodiment also provides a gate device, referencing... Figure 11 and Figure 11A , Figure 11B The diagram shown is a structural schematic of a fencing device provided in an embodiment of this application. The fencing device includes:

[0065] Substrate 100;

[0066] A buffer layer 101 with a first doping is located on the substrate 100; the buffer layer 101 includes a first doped region 1011 and a second doped region 1012 located above the first doped region 1011, the doping concentration of the first doped region 1011 is a first doping concentration, the doping concentration of the second doped region 1012 is a second doping concentration, and the first doping concentration is higher than the second doping concentration.

[0067] Fin 120 located on the substrate 100; the fin 120 includes a substrate 100 of a certain thickness, a buffer layer 101, and a second epitaxial layer 104 arranged at intervals along the direction perpendicular to the substrate, wherein the second epitaxial layer 104 is a channel region;

[0068] The source / drain regions 132 with second doping are connected to both ends of the second epitaxial layer 104, and the first doping and the second doping have opposite doping types.

[0069] Specifically, the thickness of the buffer layer is greater than or equal to 2 nm and less than or equal to 20 nm.

[0070] Specifically, the first dopant in the buffer layer is activated by an annealing process.

[0071] Specifically, in the NMOS region, the material of the buffer layer includes at least one of the following materials: Si:B, Ge:B, SiGex:B, GeSn:B, SiSn:B;

[0072] In the PMOS region, the buffer layer is made of at least one of the following materials: Si:P, Ge:P, SiGex:P, GeSn:P, or SiSn:P.

[0073] Specifically, the second doping concentration is greater than or equal to 1e15 cm⁻¹ -3 And less than or equal to 1e19cm -3 .

[0074] Specifically, it also includes an interlayer dielectric layer 140 and a sidewall 134 between the interlayer dielectric layer 140 and the gate 150.

[0075] Specifically, an inner wall 124 is also formed on the side where the source / drain region 132 is connected to the gate 150.

[0076] The gate-around device of this application embodiment has a first doped buffer layer on the substrate; the buffer layer includes a first doped region and a second doped region located above the first doped region, the doping concentration of the first doped region is a first doping concentration, the doping concentration of the second doped region is a second doping concentration, and the first doping concentration is higher than the second doping concentration. In this way, the first doped region with a higher doping concentration can suppress the off-state leakage current of the sub-Fin parasitic silicon channel, and the second doped region with a lower doping concentration can suppress the tunneling current between the sub-Fin parasitic silicon channel and the source-drain region, thereby maximally suppressing device leakage current in the off-state and improving device performance.

[0077] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0078] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a fencing device, characterized in that, include: Provide substrate; A buffer layer with a first doping is formed on the substrate; The buffer layer consists of a first doped region and a second doped region located above the first doped region. The doping concentration of the first doped region is a first doping concentration, and the doping concentration of the second doped region is a second doping concentration. The first doping concentration is higher than the second doping concentration. A stacked layer of alternating first and second epitaxial layers is formed on the surface of the buffer layer; Fins are formed in the stacked layer, the buffer layer, and the substrate; the central part of the fin is a channel region; The first epitaxial layer in the channel region is removed, and a gate surrounding the second epitaxial layer in the channel region is formed; The thickness of the buffer layer is greater than or equal to 2 nm and less than or equal to 20 nm; In the NMOS region, the first doping type is P-type; In the PMOS region, the first doping type is N-type.

2. The manufacturing method according to claim 1, characterized in that, Before forming a stacked layer of alternating first and second epitaxial layers on the buffer layer, the method further includes: The first dopant in the buffer layer is activated by annealing.

3. The manufacturing method according to claim 1, characterized in that, In the NMOS region, the buffer layer is made of at least one of the following materials: Si:B, Ge:B, SiGex:B, GeSn:B, SiSn:B; In the PMOS region, the buffer layer is made of at least one of the following materials: Si:P, Ge:P, SiGex:P, GeSn:P, or SiSn:P.

4. The manufacturing method according to claim 1, characterized in that, The second doping concentration is greater than or equal to 1e15 cm⁻¹ -3 And less than or equal to 1e19cm -3 .

5. The manufacturing method according to any one of claims 1-4, characterized in that, Before removing the first epitaxial layer in the channel region, the method further includes: The fins are used to form source / drain regions with a second doping at both ends of the channel region, wherein the first doping and the second doping have opposite doping types.

6. The manufacturing method according to claim 5, characterized in that, The method of forming second-doped source / drain regions at both ends of the channel region using the fins and removing the first epitaxial layer in the channel region includes: An isolation layer is formed on both sides of the substrate and buffer layer in the fin; The surface of the fin covering the channel region is used to form a pseudo-gate. A sidewall is formed on the sidewall of the dummy gate, and source / drain regions with a second doping are formed at both ends of the channel region using the fins; An interlayer dielectric layer is covered over the source / drain region; Remove the dummy gate to form an opening; The first epitaxial layer is removed using the opening.

7. The manufacturing method according to claim 6, characterized in that, The fins are used to form source / drain regions with a second doping at both ends of the channel region, including: Remove the stacked layers in the fins not covered by the dummy gate; An inner wall is formed on the first epitaxial layer at the end of the fin in the channel region; The fins in the channel region are used for epitaxial growth to form the source-drain region.

8. A fencing device, characterized in that, include: Substrate; A buffer layer with a first doping is located on the substrate; The buffer layer consists of a first doped region and a second doped region located above the first doped region. The doping concentration of the first doped region is a first doping concentration, and the doping concentration of the second doped region is a second doping concentration. The first doping concentration is higher than the second doping concentration. A fin located on the substrate; the fin comprises a substrate of a certain thickness, a buffer layer, and a second epitaxial layer arranged at intervals along the direction perpendicular to the substrate, wherein the second epitaxial layer is a channel region; The source / drain regions with second doping are connected to both ends of the second epitaxial layer, and the first doping and the second doping have opposite doping types; The gate surrounding the second epitaxial layer; The thickness of the buffer layer is greater than or equal to 2 nm and less than or equal to 20 nm; In the NMOS region, the first doping type is P-type; In the PMOS region, the first doping type is N-type.

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