Semiconductor devices and manufacturing methods thereof

Abstract

Semiconductor device and method of manufacturing thereof. A semiconductor package and a method of manufacturing thereof, the semiconductor package and method of manufacturing thereof capable of reducing the size of the semiconductor package and improving product reliability. In a non-limiting example embodiment, the method may include forming an insert on a wafer, forming at least one reinforcing member on the insert, coupling and electrically connecting at least one semiconductor die to the insert, filling the area between the semiconductor die and the insert with an underfill, and encapsulating the reinforcing member, the semiconductor die, and the underfill on the insert with an encapsulating agent.

Description

[0001] Cross-references to related applications / applications incorporated by reference

[0002] This application cites and claims priority to Korean Patent Application No. 10-2015-0147395, filed on October 22, 2015, with the Korean Intellectual Property Office, entitled “METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This invention relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] Current semiconductor packaging and methods used to form sensor devices (e.g., fingerprint sensor devices) are unsuitable, for example, leading to insufficient sensing accuracy and / or device reliability, manufacturability problems, devices that are thicker than needed, difficulties in integrating devices into other products, and / or high costs associated with integration into other products, etc. Further limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing conventional and traditional methods with the present invention as illustrated in the remainder of this application with reference to the drawings. Summary of the Invention

[0005] Various aspects of the present invention provide a semiconductor package and a method for manufacturing the same, which can reduce the size of the semiconductor package and improve product reliability. In a non-limiting example embodiment, the method may include forming an insert on a wafer, forming at least one reinforcing member on the insert, coupling and electrically connecting at least one semiconductor die to the insert, filling the area between the semiconductor die and the insert with an underfill, and encapsulating the reinforcing member, the semiconductor die, and the underfill on the insert with an encapsulant. Attached Figure Description

[0006] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention;

[0007] Figure 2A to 2K It is shown Figure 1 A cross-sectional view of a method for manufacturing a semiconductor package;

[0008] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention;

[0009] Figures 4A to 4C It is shown Figure 3 A cross-sectional view of a method for manufacturing a semiconductor package;

[0010] Figure 5 This is a plan view illustrating another embodiment of the step of forming a reinforcing component in a method for manufacturing a semiconductor package according to the present invention; and

[0011] Figure 6 This is a plan view illustrating yet another embodiment of the step of forming a reinforcing component in a method for manufacturing a semiconductor package according to the present invention. Detailed Implementation

[0012] The following discussion illustrates various aspects of the invention by way of examples. Such examples are non-limiting, and thus the scope of the various aspects of the invention should not be limited to any particular feature of the examples provided. In the following discussion, the phrases “for example” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limiting,” “for example and not limiting,” etc.

[0013] As used herein, “and / or” means any one or more items in a list linked by “and / or”. As an example, “x and / or y” means any element in the three-element set {(x),(y),(x,y)}. In other words, “x and / or y” means “one or both of x and y”. As another example, “x, y and / or z” means any element in the seven-element set {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}. In other words, “x, y and / or z” means “one or more of x, y and z”.

[0014] The terminology used herein is for the purpose of describing particular instances only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “including,” “having,” etc., as used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0015] It will be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of the invention, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part. Similarly, various spatial terms, such as “upper,” “lower,” “side,” etc., may be used to distinguish one element from another in a relative manner. However, it should be understood that components may be oriented in different ways; for example, without departing from the teachings of the invention, a semiconductor device may be laterally rotated such that its “top” surface faces horizontally and its “side” surface faces vertically.

[0016] In the drawings, the thickness or size of layers, regions, and / or components may be enlarged for clarity. Accordingly, the scope of the invention should not be limited by such thickness or size. Additionally, similar reference numerals in the drawings may refer to similar elements throughout the discussion.

[0017] Furthermore, it should be understood that when element A is referred to as “connected to” or “coupled to” element B, element A may be directly connected to element B or indirectly connected to element B (e.g., insert element C (and / or other elements) may be placed between element A and element B).

[0018] Some embodiments of the present invention relate to a method for manufacturing a semiconductor package and a semiconductor package using the method.

[0019] Recently, mobile communication terminals such as cellular phones or smartphones, or small electronic devices such as tablets, MP3 players, or digital cameras, have become smaller and lighter. Along with this trend, the semiconductor packages that make up these small electronic devices are becoming smaller and lighter.

[0020] To accommodate various semiconductor dies and achieve high-density redistribution layers (or structures), semiconductor packaging employs inserts (or substrates). Since inserts typically contain through-silicon vias (TSVs) that penetrate the silicon substrate, the manufacturing process can become complex and potentially increase manufacturing costs. Furthermore, differences in the coefficients of thermal expansion between the insert and the semiconductor die, and between the insert and the encapsulation, can lead to warping.

[0021] The present invention provides a method for manufacturing a semiconductor package and a semiconductor package using the method, which can reduce the size of the semiconductor package and improve product reliability.

[0022] The above and other objects of the invention will be described in or will become clear from the following description of preferred embodiments.

[0023] According to an aspect of the present invention, a method for manufacturing a semiconductor package is provided, the method comprising forming an insert on a wafer, forming at least one reinforcing member on the insert, attaching at least one semiconductor die to the insert die to electrically connect the at least one semiconductor die to the insert, filling a region between the semiconductor die and the insert with an underfill, and encapsulating the reinforcing member, the semiconductor die, and the underfill on the insert with an encapsulant.

[0024] According to an aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: an insert; at least one reinforcing member formed on the insert; at least one semiconductor die formed on the insert to be electrically connected to the insert; a primer filling a region between the semiconductor die and the insert; and an encapsulant encapsulating the reinforcing member, the semiconductor die, and the primer on the insert.

[0025] As described above, in the method for manufacturing a semiconductor package according to the present invention and in the semiconductor package using the method, since the reinforcing member can be formed on the insert to prevent the underfill filling the area between the insert and the semiconductor die from flowing to the side of the insert, the size of the semiconductor package is reduced and the product reliability is improved.

[0026] Furthermore, in the method for manufacturing a semiconductor package according to the present invention and the semiconductor package using the method, since the reinforcing component and the base adhesive are formed on the insert, it is possible to suppress warping caused by the difference in the coefficients of thermal expansion between the insert and the semiconductor die and between the insert and the encapsulant.

[0027] Examples of the present invention will now be described in detail with reference to the present embodiments, and examples of the embodiments are illustrated in the accompanying drawings.

[0028] Various aspects of the invention may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In fact, these exemplary embodiments of the invention are provided so that the invention will be fully and completely understood, and will convey various aspects of the invention to those skilled in the art.

[0029] In the diagrams, the thickness of layers and regions has been enlarged for clarity. Similar reference numerals refer to similar elements throughout. As used herein, the term "and / or" encompasses any and all combinations of one or more of the associated listed items.

[0030] Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the term "comprising," as used in this specification, means the presence of the stated features, numbers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0031] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention, and Figure 2A to 2K It is shown Figure 1 The cross-sectional view shown is of a method for manufacturing a semiconductor package.

[0032] like Figure 1 As shown, a method for manufacturing a semiconductor package according to an embodiment of the present invention includes the following steps: forming an insert (S1), forming a reinforcing member (S2), attaching a semiconductor die (S3), filling with an underfill (S4), encapsulating (S5), forming conductive bumps (S6), and forming a shielding layer (S7). Reference will now be made to... Figure 2A to 2K Detailed description Figure 1 Each step of the process.

[0033] During the formation of the insert (S1), the insert 110 is formed on the wafer 10. For example... Figure 2A As shown, the insert 110 includes multiple redistribution layers 111 (or redistribution structures) and a passivation layer 112 covering the redistribution layers 111. Specifically, as Figure 2B ( Figure 2B yes Figure 2A As shown in the enlarged view of part A), during the formation of the insert (S1), a first redistribution layer 111a (or conductive layer) is formed on the wafer 10, and a portion of the first redistribution layer 111a is covered by a first passivation layer 112a (or dielectric layer). Next, a second redistribution layer 111b (or conductive layer) electrically connected to the first redistribution layer 111a is further formed, and a portion of the second redistribution layer 111b is covered by a second passivation layer 112b (or dielectric layer). Furthermore, a third redistribution layer 111c (or conductive layer) electrically connected to the second redistribution layer 111b is further formed, and a portion of the third redistribution layer 111c is covered by a third passivation layer 112c (or dielectric layer), thereby completing the example insert 110. Here, the third redistribution layer 111c is exposed on the top surface of the insert 110. Although in Figures 2A to 2CThe diagram shows a redistribution layer 111 with three layers, but the number of layers in the redistribution layer 111 may be more or less than three. Additionally, the wafer 10 may be made of silicon (Si), glass, or metal, but aspects of the invention are not limited thereto.

[0034] The redistribution layer 111 (or its conductive layer) can be formed by electroless plating, electroplating, and / or sputtering of a material selected from the group consisting of copper, aluminum, gold, silver, palladium, and their equivalents, but the invention is not limited thereto. Alternatively, the patterning or wiring of the redistribution layer 111 (or its conductive layer) can be performed using a conventional photoresist via photolithography, but the invention is not limited thereto.

[0035] The passivation layer 112 (or dielectric layer) may be made of a material selected from the group consisting of polymers (e.g., polyimide, benzocyclobutene, or polybenzoxazole, and equivalents thereof), but aspects of the invention are not limited thereto. Alternatively, the passivation layer 112 may be formed by a method selected from the group consisting of spin coating, spray coating, dip coating, bar coating, and equivalents thereof, but aspects of the invention are not limited thereto.

[0036] Alternatively, the insert 110 can be completed by supplying a portion of the redistribution layer 111 formed on the wafer 10 during the manufacturing process (or factory) of the wafer 10 and further forming the redistribution layer 111 on said portion during the packaging process (or factory). Therefore, high-density interconnects can be achieved because the insert 110 achieves a finer linewidth (less than 100 μm) and finer pitch interconnects. This type of insert 110 can be referred to, for example, as a silicon-free integrated module (SLIM) insert. Alternatively, the insert 110 can be manufactured by supplying only the wafer 10 during the manufacturing process (or factory) of the wafer 10 and forming the redistribution layer 111 (or redistribution structure) on the wafer 10 during the packaging process (or factory). This type of insert 110 can be referred to, for example, as a silicon wafer integrated fan-out (SWIFT) insert. As another example, the insert 110 can be a printed circuit board (PCB).

[0037] When forming the reinforcing member (S2), the reinforcing member 120 is formed on the insert 110. For example... Figure 2C As shown, the reinforcing member 120 is cylindrical or wall-shaped, positioned generally perpendicular to the insert 110, and formed at the edge of the insert 110. The reinforcing member 120 may be made of a conductive material with high electrical and thermal conductivity (e.g., a material selected from copper (Cu) or its equivalent) or a plastic material with high thermal conductivity, but aspects of the invention are not limited thereto.

[0038] like Figure 2DAs shown, reinforcement members 120 can be formed on wafer 10 in a matrix configuration during the process of using wafer 10. Specifically, reinforcement members 120 are formed on the slitting line used to saw wafer 10 to form a single semiconductor package. Thus, the reinforcement members 120 are formed to completely surround the edge of insert 110, thereby forming a receiving space S (or die space or component space) on which the semiconductor die 130 is mounted (described later).

[0039] When attaching the semiconductor die (S3), the semiconductor die 130 is attached to the insert 110. First, as... Figure 2E As shown, when attaching the semiconductor die (S3), a conductive pad 131 is formed on the redistribution layer 111 exposed on the top surface of the insert 110. Therefore, the conductive pad 131 is electrically connected to the redistribution layer 111 (or the redistribution structure). Alternatively, the conductive pad 131 can be formed before forming the insert (S1) or it can be formed together with the reinforcing member 120 during the formation of the reinforcing member (S2). The conductive pad 131 can be made of a material selected from the group consisting of copper, aluminum, gold, silver, palladium, and equivalents thereof, but aspects of the invention are not limited thereto. Furthermore, the conductive pad 131 can be formed by sputtering, vacuum deposition, or photolithography, but aspects of the invention are not limited thereto.

[0040] Next, as Figure 2F As shown, during the attachment of the semiconductor die (S3), the semiconductor die 130 is electrically connected to the conductive pad 131. For example, the conductive bumps 132 of the semiconductor die 130 are electrically connected to the conductive pad 131 via solder 133. For example, the semiconductor die 130 can be electrically connected to the conductive pad 131 using a mass reflow process, a thermoforming process, or a laser bonding process. The solder 133 can be formed using a material selected from metallic materials (e.g., lead / tin (Pb / Sn) or lead-free Sn and its equivalents), but aspects of the invention are not limited thereto.

[0041] Additionally, the semiconductor die 130 may contain, for example, circuitry such as a digital signal processor (DSP), a microprocessor, a network processor, a power management processor, an audio processor, an RF circuit, a wireless baseband system-on-a-chip (SoC) processor, a sensor, or an application-specific integrated circuit (ASIC).

[0042] During the filling process with primer (S4), primer 140 fills the area between insert 110 and semiconductor die 130. For example... Figure 2GAs shown, primer 140 fills the area between the top surface of insert 110 and the bottom surface of semiconductor die 130, and then cures. Primer 140 protects the bump bonding portion from external factors such as mechanical shock or corrosion during the semiconductor packaging manufacturing process. Here, primer 140 can be made of a material selected from the group consisting of: epoxy resin, thermoplastic material, thermocurable material, polyimide, polyurethane, polymeric material, filled epoxy resin, filled thermoplastic material, filled thermocurable material, filled polyimide, filled polyurethane, filled polymeric material, flux primer, and equivalents thereof, but the invention is not limited thereto.

[0043] Furthermore, the primer 140 completely covers the top surface of the insert 110 and is configured to contact one side surface of the reinforcing member 120. Therefore, the primer 140 can be prevented from flowing to the side of the insert 110 by means of the reinforcing member 120. In other words, the reinforcing member 120 can act as a barrier layer to prevent the primer 140 from flowing when it is filled.

[0044] In addition, since the base adhesive 140 is formed between the insert 110 and the semiconductor die 130 and completely covers the top surface of the insert 110, it is possible to suppress warping caused by the difference in the coefficient of thermal expansion between the insert 110 and the semiconductor die 130 and between the insert 110 and the encapsulant 150.

[0045] During encapsulation (S5), the top of the insert 110 is encapsulated using encapsulating material 150. For example... Figure 2H As shown, during encapsulation (S5), encapsulant 150 is used to encapsulate the reinforcing member 120, the semiconductor die 130, and the primer 140 mounted on the insert 110. Encapsulant 150 completely encapsulates the reinforcing member 120, the semiconductor die 130, and the primer 140, thereby protecting them from damage caused by external impact and oxidation. Encapsulant 150 may be made of a material selected from the group consisting of: thermosetting epoxy molding compounds for general transfer molding, room temperature curable encapsulants for conditioning, and equivalents thereof, but aspects of the invention are not limited thereto. Here, encapsulant 150 is spaced apart from the top surface of insert 110 and does not directly contact the top surface of insert 110.

[0046] Although not shown, an unwanted portion of the top surface of the encapsulation 150 can be removed to a predetermined thickness by grinding. Here, grinding can be performed using, for example, a diamond grinding machine or an equivalent thereof, but the invention is not limited thereto.

[0047] During the formation of conductive bumps (S6), the wafer 10 placed under the insert 110 is removed and conductive bumps 160 are formed under the insert 110. First, as Figure 2I As shown, during the formation of conductive bumps (S6), the wafer 10 placed under the insert 110 is removed. For example, the wafer 10 can be removed by a conventional grinding process. Therefore, the redistribution layer 111 (e.g., a first redistribution layer or conductive layer) is exposed on the bottom surface of the insert 110. Then, as... Figure 2J As shown, during the formation of conductive bumps (S6), conductive bumps 160 are formed on the redistribution layer 111 exposed to the bottom surface of the insert 110. Here, under-bump metallization (UBM) can be formed on the redistribution layer 111 exposed to the bottom surface of the insert 110, and conductive bumps 160 can be formed on said UBM. The UBM can improve the board-level reliability of conductive bumps 160 by preventing the formation of intermetallic compounds between conductive bumps 160 and the redistribution layer 111.

[0048] The conductive bump 160 may be made of a material selected from, but not limited to, eutectic solder (e.g., Sn). 37 Pb), and high-lead solders with high melting points (e.g., Sn). 95 Pb), lead-free solders (e.g., SnAg, SnCu, SnZn, SnZnBi, SnAgCu and SnAgBi), and their equivalents.

[0049] Next, although not shown, a sawing process is performed to form a single unit consisting of at least one semiconductor die 130 and a reinforcement member 120 corresponding to the at least one semiconductor die disposed in the receiving space S (or die space or component space), thereby manufacturing a semiconductor package 100 according to an embodiment of the invention. Here, the sawing process can be performed using a sawing device (e.g., a hacksaw blade or a laser beam).

[0050] During the formation of the shielding layer (S7), a shielding layer 170 is formed on the surface of the encapsulant 150. During the formation of the shielding layer (S7), as... Figure 2K As shown, a shielding layer 170 is formed to cover the entire surface of the encapsulation 150 and at least a portion of the reinforcing member 120. For example, the shielding layer 170 can be formed by spraying or sputtering a conductive paste containing conductive metal powder onto the surface of the encapsulation 150, but aspects of the invention are not limited thereto.

[0051] Here, when the shielding layer 170 is formed, the reinforcing member 120 can be made of conductive metal, and one end of it is preferably grounded. Therefore, the shielding layer 170 can shield electromagnetic waves generated by at least one semiconductor die 130 in the encapsulation 150 from being scattered to the outside, and the shielding layer 170 can also shield externally applied electromagnetic waves from penetrating into at least one semiconductor die 130 in the encapsulation 150.

[0052] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention, and Figures 4A to 4C It is shown Figure 3 The cross-sectional view shown is of a method for manufacturing a semiconductor package.

[0053] refer to Figure 3 A method for manufacturing a semiconductor package according to another embodiment of the present invention includes the following steps: forming an insert (S11), forming a reinforcing member (S12), attaching a semiconductor die (S13), filling with an underfill (S14), encapsulating (S15), forming a die through-hole (S16), and forming a conductive bump (S17). Reference will now be made to... Figures 4A to 4C Detailed description Figure 3 Each step of the process.

[0054] Steps S11, S12, S13, S14 and S15 Figure 1 Steps S1, S2, S3, S4, and S5 are the same, and the corresponding diagrams for steps S11, S12, S13, S14, and S15 are shown. Figures 2A to 2H Since they are the same, detailed descriptions of the figures will not be provided.

[0055] When forming the mold through-hole (S16), a mold through-hole (TMV) 280 is formed in the encapsulation 150. For example... Figure 4A As shown, during the formation of the through-hole (TMV) (S16), the TMV 280 passes through the region between the top surface of the encapsulation 150 and the top surface of the insert 110. The TMV 280 is formed between the semiconductor die 130 and the reinforcement member 120. Specifically, the TMV 280 is formed by the following steps: forming a through-hole through the encapsulation 150 by, for example, a laser drilling process; electroplating a thermally conductive metal with high electrical and thermal conductivity, such as aluminum (Al) or copper (Cu), on the inner wall surface of the through-hole; and then filling the through-hole with a conductive material such as a metal paste. Therefore, the semiconductor package according to the invention can easily dissipate the heat generated by the insert 110 through the TMV 280. In addition, semiconductor dies or semiconductor packages can be further electrically stacked on the TMV 280.

[0056] During the formation of conductive bumps (S17), the wafer 10 placed under the insert 110 is removed, and conductive bumps 160 are formed under the insert 110. First, as Figure 4B As shown, during the formation of conductive bumps (S17), the wafer 10 placed under the insert 110 is removed. For example, the wafer 10 can be removed by a conventional grinding process. Therefore, the redistribution layer 111 (e.g., a first redistribution layer or conductive layer) is exposed on the bottom surface of the insert 110. Then, as... Figure 4C As shown, during the formation of conductive bumps (S17), conductive bumps 160 are formed on the redistribution layer 111 exposed to the bottom surface of the insert 110. Here, under-bump metallization (UBM) can be formed on the redistribution layer 111 exposed to the bottom surface of the insert 110, and conductive bumps 160 can be formed on said UBM. The UBM can improve the board-level reliability of conductive bumps 160 by preventing the formation of intermetallic compounds between conductive bumps 160 and the redistribution layer 111.

[0057] The conductive bump 160 may be made of a material selected from, but not limited to, eutectic solder (e.g., Sn). 37 Pb), and high-lead solders with high melting points (e.g., Sn). 95 Pb), lead-free solders (e.g., SnAg, SnCu, SnZn, SnZnBi, SnAgCu and SnAgBi), and their equivalents.

[0058] Next, although not shown, a sawing process is performed to form a single unit consisting of at least one semiconductor die 130 and a reinforcement member 120 corresponding to the at least one semiconductor die disposed in the receiving space S (or die space or component space), thereby manufacturing a semiconductor package 200 according to another embodiment of the invention. Here, the sawing process can be performed using a sawing device (e.g., a hacksaw blade or a laser beam).

[0059] Figure 5 This is a plan view illustrating another embodiment of the step of forming a reinforcing component in a method for manufacturing a semiconductor package according to the present invention.

[0060] refer to Figure 5During the formation of the reinforcement components, reinforcement components 220 are formed on the wafer 10. The reinforcement components 220 are formed at the corners of the slicing lines used to saw the wafer 10 to form a single semiconductor package. Therefore, the reinforcement component 220 may comprise four components spaced apart from each other. The reinforcement component 220 may be formed in a generally 'L'-shaped configuration and includes a first reinforcement component portion 221 and a second reinforcement component portion 222 perpendicular to the first reinforcement component portion 221. Here, the first reinforcement component portion 221 is formed perpendicular to one of the slicing lines. Additionally, the corresponding components of the reinforcement component 220 are spaced apart to form a receiving space (or die space or component space) for mounting semiconductor dies. After sawing the wafer 10, the reinforcement components 220 support the top surface of the insert at each corner of the single semiconductor package, thereby preventing twisting or warping during the semiconductor manufacturing process.

[0061] Figure 6 This is a plan view illustrating yet another embodiment of the step of forming a reinforcing component in a method for manufacturing a semiconductor package according to the present invention.

[0062] refer to Figure 6 During the formation of the reinforcement components, reinforcement components 320 are formed on the wafer 10. Reinforcement components 320 are formed at each corner of the sawing line used to form a single semiconductor package by sawing the wafer 10. Therefore, the reinforcement component 320 may comprise four components spaced apart from each other. The reinforcement component 320 may be formed in a generally arrow-shaped configuration and includes a first reinforcement component portion 321, a second reinforcement component portion 322 perpendicular to the first reinforcement component portion 321, and a third reinforcement component portion 323 disposed between the first reinforcement component portion 321 and the second reinforcement component portion 322. Here, the first reinforcement component portion 321 is formed perpendicular to a line in the sawing line. Furthermore, the corresponding components of the reinforcement component 320 are formed to be spaced apart from each other to form a receiving space S (or die space or component space) on which a semiconductor die is mounted. After sawing the wafer 10, the reinforcement component 320 supports the top surface of the insert at each corner of the single semiconductor package, thereby preventing twisting or warping during the semiconductor manufacturing process.

[0063] While methods for manufacturing semiconductor packages according to various aspects of the present invention and semiconductor packages using said methods have been described with reference to certain supporting embodiments, those skilled in the art will understand that the invention is not limited to the specific embodiments disclosed, but rather encompasses all embodiments falling within the scope of the appended claims.

[0064] The discussion herein contains numerous schematic diagrams illustrating various parts of an electronic device and methods of its manufacture. For clarity, these diagrams do not show all aspects of each example assembly. Any example assembly and / or method provided herein may share any or all of its features with any or all other assemblies and / or methods provided herein.

[0065] In summary, various aspects of the present invention provide a semiconductor package and a method for manufacturing the same, which can reduce the size of the semiconductor package and improve product reliability. In a non-limiting example embodiment, the method may include forming an insert on a wafer, forming at least one reinforcing member on the insert, coupling and electrically connecting at least one semiconductor die to the insert, filling the area between the semiconductor die and the insert with an underfill, and encapsulating the reinforcing member, the semiconductor die, and the underfill on the insert with an encapsulant. While the above has been described with reference to certain aspects and examples, those skilled in the art will understand that various modifications and substitutions for equivalents can be made without departing from the scope of the invention. Furthermore, many modifications can be made to adapt specific situations or materials to the teachings of the invention without departing from the scope of the invention. Therefore, it is intended that the invention be limited to the specific examples disclosed, but rather that the invention encompass all examples falling within the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor package, the method comprising: Forming a substrate on a wafer; At least one reinforcing member is formed on a portion of the periphery of the substrate, wherein the reinforcing member is formed at a saw line or a corner of a saw line used to cut the wafer to form a single semiconductor package, and the at least one reinforcing member comprises a conductive material. At least one semiconductor die is coupled and electrically connected to the substrate; The at least one reinforcing component and the semiconductor die are encapsulated on the substrate using an encapsulating material; as well as A shielding layer is formed, which surrounds the encapsulation and covers a portion of the at least one reinforcing member, wherein the shielding layer is electrically connected to the at least one reinforcing member.

2. The method of claim 1, wherein forming the at least one reinforcing member comprises forming a plurality of discrete reinforcing members such that the plurality of discrete reinforcing members surround the periphery of the substrate in a discontinuous manner with gaps separating adjacent discrete reinforcing members.

3. The method of claim 1, wherein forming the at least one reinforcing member comprises forming a closed peripheral wall along the periphery of the substrate.

4. The method of claim 1, further comprising bottom filling the space between the at least one semiconductor die and the substrate.

5. The method of claim 4, wherein the underfill includes underfilling prior to the encapsulation.

6. The method of claim 5, wherein the bottom filling results in a base coat extending to the at least one reinforcing member.

7. The method of claim 5, wherein the bottom filling results in a base coat that does not extend to the at least one reinforcing member.

8. The method of claim 1, further comprising, after the encapsulation: The wafer is removed from the substrate, and conductive bumps are formed on the surface of the substrate covered by the wafer; and The substrate is sawn to form discrete semiconductor packages.

9. The method of claim 1, further comprising forming a die through-hole from the top surface of the encapsulation to the top surface of the substrate.

10. A semiconductor package, comprising: Substrate; At least one reinforcing member is located on the substrate, wherein the reinforcing member is located at a cut line or a corner of a single semiconductor package, and each of the at least one reinforcing member comprises a conductive material. At least one semiconductor die is coupled to the substrate and electrically connected to a first surface of the substrate; An encapsulation material that encapsulates the at least one reinforcement component and the at least one semiconductor die on the substrate; as well as A shielding layer that surrounds the encapsulation and covers a portion of the at least one reinforcing member, wherein the shielding layer is electrically connected to the at least one reinforcing member.

11. The semiconductor package of claim 10, wherein the at least one reinforcement member comprises a plurality of discrete reinforcement members surrounding the periphery of the substrate in a discontinuous manner with gaps separating adjacent discrete reinforcement members.

12. The semiconductor package of claim 10, wherein the at least one reinforcing member comprises a closed peripheral wall along the periphery of the substrate.

13. The semiconductor package of claim 10, wherein an underfill is provided beneath the encapsulation between the semiconductor die and the substrate, the underfill contacting the vertical surface of the at least one reinforcing member.

14. The semiconductor package of claim 10, wherein an underfill is provided beneath the encapsulation, between the semiconductor die and the substrate, the underfill not contacting any of the at least one of the reinforcing members.

15. The semiconductor package of claim 10, wherein the substrate is a printed circuit board.

16. The semiconductor package of claim 10, comprising conductive bumps electrically connected to the substrate on a second surface of the substrate opposite to the first surface.

17. The semiconductor package of claim 10, comprising a die through-hole extending through a region from the top surface of the encapsulation to the top surface of the substrate, wherein each of the die through-holes is located between the semiconductor die and one of the at least one reinforcement member.

18. A semiconductor package, comprising: Substrate, said substrate on a wafer; At least one reinforcing member is located on the substrate, wherein the reinforcing member is located at a cut line or a corner of a cut line of a single semiconductor package, and the at least one reinforcing member comprises a conductive material. At least one semiconductor die, said at least one semiconductor die being coupled to and electrically connected to the substrate; An encapsulation covering the at least one reinforcing component and the at least one semiconductor die; as well as A shielding layer that surrounds the encapsulation and covers a portion of the at least one reinforcing member, wherein the shielding layer is electrically connected to the at least one reinforcing member; in: The substrate includes a vertical surface at one end of the substrate. Each of the at least one reinforcing member has an inner vertical surface facing the at least one semiconductor die and an outer vertical surface opposite to the inner vertical surface. The encapsulation has a vertical surface at the end of the encapsulation, and The outer vertical surface of each of the at least one reinforcing component, the corresponding vertical surface of the vertical surface of the substrate, and the corresponding vertical surface of the vertical surface of the encapsulation are substantially coplanar with each other.

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