lateral bipolar transistor

Abstract

The present disclosure relates to semiconductor structures, and more particularly to a lateral bipolar transistor and method of fabrication. A structure includes an inner base including a semiconductor material located in a channel region of a semiconductor substrate, an outer base vertically located above the inner base, a raised collector region located on the semiconductor substrate and laterally connected to the inner base, and a raised emitter region located on the semiconductor substrate and laterally connected to the inner base.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more specifically, to lateral bipolar transistors and methods of manufacturing them. Background Technology

[0002] Bipolar transistors can be vertical or horizontal. In a vertical bipolar transistor, charge carriers flow vertically. Because the collector region is formed deep from the wafer surface, the emitter-collector resistance increases, making the transistor unsuitable for high-speed operation. Furthermore, transistors require high-density buried layers, collector epitaxial layers, and deep trench isolation. Therefore, the number of process steps increases, leading to higher costs.

[0003] On the other hand, lateral bipolar transistors are structurally simpler than vertical bipolar transistors. Furthermore, in lateral bipolar transistors, the collector electrode can directly contact the collector region, which is beneficial for high-speed operation. However, current integration schemes can lead to high Ccb (parasitic capacitance) and high Rb, a problem in bipolar technology as it limits device scaling for improving fT / fMAX. Summary of the Invention

[0004] In one aspect of this disclosure, a structure includes: an inner base comprising semiconductor material located in a channel region of a semiconductor substrate; an outer base vertically positioned above the inner base; a raised collector region located on the semiconductor substrate and laterally connected to the inner base; and a raised emitter region located on the semiconductor substrate and laterally connected to the inner base.

[0005] In one aspect of this disclosure, a structure includes: a lateral heterojunction bipolar transistor located on a substrate material, the lateral heterojunction bipolar transistor including: an inner base region located in a channel region of the substrate material; an outer base region located above the inner base region; a raised collector region adjacent to the outer base region comprising an epitaxial semiconductor material; and a raised emitter region adjacent to the outer base region comprising the epitaxial semiconductor material; and a gate structure located on the substrate material, the gate structure including a gate material and a raised source / drain region comprising the epitaxial semiconductor material; and an isolation region that isolates the gate structure from the lateral heterojunction bipolar transistor.

[0006] In one aspect of this disclosure, a method includes: forming an inner base comprising a semiconductor material located in a channel region of a semiconductor substrate; forming an outer base vertically above the inner base; forming a raised collector region located on the semiconductor substrate and laterally connected to the inner base; and forming a raised emitter region located on the semiconductor substrate and laterally connected to the inner base. Attached Figure Description

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments thereof, with reference to the various accompanying drawings.

[0008] Figure 1 The substrate and gate structures, among other features, according to some aspects of this disclosure, and the corresponding manufacturing processes are shown.

[0009] Figure 2 The liner of the packaged gate structure and the corresponding manufacturing process are shown, among other features, according to some aspects of this disclosure.

[0010] Figure 3 The openings in a material stack formed above a hard mask, among other features, according to some aspects of this disclosure, and the corresponding manufacturing process are shown.

[0011] Figure 4 The material for the internal spacer formed within the opening, among other features, is shown according to some aspects of this disclosure, as well as the corresponding manufacturing process.

[0012] Figure 5 The present disclosure illustrates, among other features, smaller openings in a material stack and corresponding manufacturing processes according to some aspects of this disclosure.

[0013] Figure 6 The illustration shows an isolation region formed in a substrate through a small opening, among other features, according to some aspects of this disclosure, and the corresponding manufacturing process.

[0014] Figure 7 The following are shown, among other features, of an underlying substrate exposed in a smaller opening according to some aspects of this disclosure, and the corresponding manufacturing process.

[0015] Figure 8 The inner and outer base electrodes formed in a smaller opening, among other features, according to some aspects of this disclosure, and the corresponding manufacturing process are shown.

[0016] Figure 9The raised epitaxial regions located on the sides of the outer base and gate structures, among other features, according to some aspects of this disclosure, and the corresponding manufacturing process are shown.

[0017] Figure 10 The silicide and contacts to lateral bipolar transistors and CMOS transistors, among other features, are shown according to some aspects of this disclosure, as well as the corresponding manufacturing processes. Detailed Implementation

[0018] This disclosure relates to semiconductor structures, and more specifically, to lateral bipolar transistors and methods of fabrication. More specifically, the lateral bipolar transistor is formed from self-aligned trenches on a fully depleted semiconductor-on-insulator (FDSOI) substrate. Advantageously, the lateral bipolar transistor minimizes parasitic capacitance and provides tunability based on the base width, which is, for example, a base width (Wb) of <20 nm defined by a separate pattern that allows for tunability.

[0019] In an embodiment, the lateral bipolar transistor can be a lateral NPN heterojunction transistor, comprising a SiGe inner base laterally connected to the emitter and collector. Due to the smaller SiGe bandgap, the SiGe inner base provides improved Ft / Fmax. The lateral bipolar transistor also includes an outer base vertically positioned above the inner base. Spacers are formed on both sides of the outer base to provide isolation from the emitter and collector regions. Furthermore, a silicide, such as NiSi, can be formed on the outer base for improved base contact. The inner base can be SiGe, extending into a recess in the channel of the semiconductor-on-insulator (SOI) substrate, while allowing for maximum tuning freedom using an inner base width (<20 nm) without degrading the bipolar device. In an embodiment, the base width is much smaller than the CMOS gate width (Lg). Lateral bipolar transistors can be fabricated on the same chip as planar CMOS devices, particularly for RF SOC (>1 THz) applications.

[0020] The lateral bipolar transistors of this disclosure can be fabricated using a variety of different tools and in a variety of ways. However, typically, methods and tools are used to form structures with micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating the lateral bipolar transistors of this disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned on top of the wafer by means of a photolithography process. In particular, the fabrication of lateral bipolar transistors uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film onto the mask.

[0021] Figure 1The following diagram illustrates a substrate and gate structure, among other features, and a corresponding fabrication process according to some aspects of this disclosure. More specifically, structure 10 includes a substrate 12 and a gate structure 16 composed of a work function metal, a polysilicon material, and a gate dielectric material. In an embodiment, a cap layer 16a may be formed on the top surface of the gate structure 16, such as a polysilicon material. As a non-limiting exemplary example, the cap layer 16a may consist of an oxide liner and a nitride cap material located on the oxide liner. The gate dielectric material may be a high-k gate dielectric material, such as HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations of multilayers comprising the above materials.

[0022] While not critical to understanding this disclosure, the gate structure 16 can be fabricated using conventional CMOS processes. For example, the gate structure 16 can be fabricated using standard CMOS or alternative gate processes. In a standard CMOS process (e.g., a gate-first process), a gate material (e.g., a gate dielectric, a work function metal, or polysilicon) and a cap layer 16a are formed (e.g., deposited) on a substrate 12, followed by a patterning process. The patterning process can be a conventional etching process, such as reactive ion etching (RIE), to form a material stack including the gate structure 16.

[0023] Substrate 12 is preferably a fully depleted semiconductor-on-insulator (FDSOI) substrate. For example, substrate 12 includes a semiconductor processing substrate 12a, an insulating layer 12b, and a semiconductor layer 12c. In embodiments, the semiconductor processing substrate 12a and semiconductor layer 12c can be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other group III / V or II / VI compound semiconductors. Semiconductor processing substrate 12a can be a p-substrate. Semiconductor layer 12c can also include any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). Depending on the desired device performance, semiconductor layer 12c can be deposited to various thicknesses (Tsi), which will serve as the channel region for the subsequently formed device. Insulating layer 12b can include a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, or combinations thereof, and preferably includes a buried oxide layer (BOX) supported on semiconductor processing substrate 12a.

[0024] Still referencing Figure 1A shallow trench isolation structure 14 is formed in a semiconductor layer 12c, extending to an insulating layer 12b. The shallow trench isolation structure 14 can be formed using conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed on the semiconductor layer 12c is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., RIE) is used to transfer the pattern from the patterned resist layer to the semiconductor layer 12c to form one or more trenches in the semiconductor layer 12c through the openings in the resist. After the resist is removed by a conventional oxygen ashing process or other known stripping agent, an insulating material (e.g., an oxide-based material) can be deposited using any conventional deposition process, such as chemical vapor deposition (CVD). Any residual material on the surface of the semiconductor layer 12c can be removed by a conventional chemical mechanical polishing (CMP) process.

[0025] exist Figure 2 In this embodiment, a liner 18 is formed on the semiconductor layer 12c and over the gate structure 16. In this embodiment, the liner 18 encapsulates the gate structure 16. The liner 18 may be an oxide material that is blanket-deposited on the semiconductor layer 12c and the gate structure 16. A hard mask 20 may be formed over the liner 18. In this embodiment, the hard mask 20 may be blanket-deposited over the liner 18 using a conventional deposition process (e.g., CVD). The hard mask 20 may be, for example, SiCN.

[0026] like Figure 3 As further shown, a material stack 22 can be formed over a hard mask 20. The material stack 22 can include material stacks used in photolithography and etching processes. For example, the material stack 22 can include SOH 22a, SiON 22b, and an anti-reflective coating 22c (e.g., a bottom anti-reflective coating (BARC)). An opening 24 can be formed in the anti-reflective coating 22c and the material 22b using conventional photolithography and etching processes already described herein. In an embodiment, the opening 24 has an "x" cross-section. In an embodiment, the cross-section "x" can be a minimum critical dimension, for example, a width or diameter of approximately 20 nm to 50 nm. The opening 24 may also extend partially into the material 22a.

[0027] exist Figure 4In this process, the antireflective coating 22c can be removed using a known stripping agent. An internal spacer material 25 can be formed above the material 22b and within the opening 24. For example, the internal spacer material 25 can be an oxide material. The internal spacer material 25 can be deposited using a conventional deposition process such as CVD. Those skilled in the art will understand that the internal spacer material 24 will effectively reduce the cross-sectional area of ​​the opening to dimension “y”. In embodiments, dimension “y” can be adjusted based on the thickness of the internal spacer material 24. For example, a thicker internal spacer material 25 will reduce dimension “y”; while a thinner internal spacer material 25 will increase dimension “y”.

[0028] exist Figure 5 In this process, dimension "y" can be transferred to material 22a by an etching process that forms opening 26. In this process, the etching removes the horizontal surfaces of the internal spacer material 24 inside and outside the opening, extending the opening 26 into material 22a. In embodiments, opening 26 may also extend partially within hard mask 20. Dimension "y" can be approximately 20 nm or smaller; although this dimension can be adjusted to other cross-sectional dimensions, such as diameter or width. In other embodiments, dimension "y" is smaller than the gate length (Lg) of gate structure 16.

[0029] like Figure 6 As further shown, the opening 26 (and its dimension "y") can extend through the hard mask 20, thereby exposing the liner 18. Material 22b and the internal spacer material 25 can be removed by conventional etching or stripping processes. The underlying semiconductor substrate 12c can undergo an ion implantation process, as indicated by the arrow, to form an isolation region 28 within the channel region of the semiconductor substrate 12c. In this embodiment, the ion implantation is a lightly doped P+ implantation, such as BF2, into the underlying semiconductor substrate 12c using a conventional ion implantation process.

[0030] exist Figure 7 In this process, the exposed liner 18 within the opening 26 can be removed using a conventional etching process. The isolation region 28 can also be thinned or recessed to accommodate the inner base that will be formed above the isolation region 28 in subsequent manufacturing processes.

[0031] like Figure 8 As shown, a semiconductor material 30 (e.g., an inner base) can be formed within the opening 26, followed by a semiconductor material 32 (e.g., an outer base) and a cap material 34. In this embodiment, the opening 26 allows the semiconductor material 30 (e.g., the inner base), the semiconductor material 32 (e.g., the outer base), and the cap material 34 to self-align, each of which now has a dimension “y” of the opening 26.

[0032] Semiconductor material 30 (e.g., inner base) may be undoped SiGe material formed within a recessed portion of the channel region (i.e., above the isolation region 28 aligned with opening 26). Semiconductor material 32 (e.g., outer base) may be P+ doped Si material, which, as an example, is also formed in opening 26. Furthermore, both semiconductor material 30 (e.g., inner base) and semiconductor material 32 (e.g., outer base) may be epitaxially grown semiconductor materials, wherein, as an example, P+ doping of semiconductor material 32 is performed in situ. Cap material 34 is preferably the same material as the cap layer 16a of gate structure 16, such as oxide / nitride. CMP or non-selective etching processes may be performed to remove any excess cap material 34 on hard mask 20.

[0033] Those skilled in the art will understand that both the semiconductor material 30 (e.g., the inner base) and the semiconductor material 32 (e.g., the outer base) are adjustable by changing their width and / or thickness. For example, a larger opening 26 will result in a wider base width; while a smaller opening will result in a narrower base width. Similarly, the thickness of the isolation region 28 can be adjusted to provide more or less semiconductor material 30 (e.g., the inner base) and semiconductor material 32 (e.g., the outer base). For example, a thinner isolation region 28 in the channel region will result in a thicker inner base, while a thicker isolation region 28 will result in a thinner inner base.

[0034] like Figure 9 As further shown, conventional etching or stripping processes can be used to remove, for example, stripping, hard mask 20, and liner 18. In this way, the outer base material 28 (with cap material 32) and the gate structure 16 (with cap layer 16a) are exposed. Sidewall spacers 36 are formed on the sidewalls of the outer base material 28 and the gate structure 16. In an embodiment, the sidewall spacers 36 may be a low-k spacer material, i.e., an oxide, formed by a conventional blanket deposition process followed by an anisotropic etching process. Advantageously, the sidewall spacers 36 on the sidewalls of the outer base material 28 and the gate structure 16 can be formed in the same fabrication process.

[0035] The raised emitter region 38 and the raised collector region 40 can be formed on the sidewall spacer 36 of the outer base (e.g., semiconductor material 32) to form a lateral bipolar transistor 100. More specifically, the raised emitter region 38 and the raised collector region 40 can be N+ doped semiconductor material, thereby forming an NPN lateral heterojunction bipolar transistor 100. In an embodiment, the inner base 30 can be laterally connected to the raised emitter region 38 and the raised collector region 40.

[0036] Figure 9Further illustrated is an elevated source / drain region 42 formed on the sidewall spacer 36 of the gate structure 16 to form a planar CMOS transistor 200. In an embodiment, the elevated emitter region 38, the elevated collector region 40, and the elevated source / drain region 42 can be formed by an epitaxial growth process. For example, the elevated emitter region 38, the elevated collector region 40, and the elevated source / drain region 42 can be formed from Si material, and preferably from N+-doped Si material, using the same conventional selective epitaxial growth process.

[0037] exist Figure 10 In this process, the cap material 32 and cap layer 16a can be removed by a stripping process, such as a nitride hard mask stripping process known to those skilled in the art. In addition to the raised emitter region 38, the raised collector region 40, and the raised source / drain region 42, a silicide 44 can also be formed on the exposed semiconductor material 32 (e.g., the outer base) and the polysilicon gate material of the gate structure 16. In this embodiment, the silicide 44 provides improved base contact, thus providing lower base resistance compared to conventional structures.

[0038] Those skilled in the art will understand that the silicide process begins by depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor device (e.g., semiconductor material 32, polysilicon material, and raised epitaxial regions 38, 40, 42). After the material deposition, the structure is heated to cause the transition metal to react with exposed silicon (or other semiconductor materials described herein) in the active region of the device, thereby forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 44 in the active region of the device.

[0039] Still referencing Figure 10 Contacts 48a-48f are formed on silicide contact 44. In an embodiment, contacts 48a-48f are formed within interlayer dielectric material 46 using conventional photolithography, etching, and deposition processes. In an embodiment, interlayer dielectric material 46 may be a stack of materials such as oxides and nitrides.

[0040] As a more specific example, the interlayer dielectric material 46 can be deposited using a conventional CVD process, followed by the formation of trenches to expose the semiconductor material 32 (e.g., the outer base), emitter region 38, and silicide contacts 44 of the collector region 40 of the lateral bipolar transistor 100, as well as the epitaxial source / drain regions 42 and silicide contacts 44 of the polysilicon material of the gate structure 16 of the CMOS transistor 200. Conductive material (e.g., aluminum or tungsten) can be deposited within the trenches to form contacts 48a-48f to the respective regions 38, 32, 40, 33, 36. Any excess conductive material can be removed from the surface of the interlayer dielectric material 46 using a conventional CMP process.

[0041] Lateral bipolar transistors can be utilized in System-on-Chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, SoCs consume significantly less power and occupy a much smaller area compared to multi-chip designs with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0042] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0043] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: The inner base includes semiconductor material located in the channel region of the semiconductor substrate; The outer base electrode is vertically positioned above the inner base electrode; An elevated collector region, located on the semiconductor substrate and laterally connected to the inner base; An elevated emitter region, located on the semiconductor substrate and laterally connected to the inner base; as well as A gate structure located on the semiconductor substrate, wherein the width of the inner base is smaller than the gate length of the gate structure. The inner base comprises undoped SiGe, and the outer base comprises P+ doped Si.

2. The semiconductor structure according to claim 1, wherein, The inner base is recessed in the channel region of the semiconductor substrate.

3. The semiconductor structure according to claim 1, wherein, The semiconductor substrate includes a semiconductor-on-insulator material having a P+ isolation region located in the channel region.

4. The semiconductor structure according to claim 3, wherein, The P+ isolation region includes a recess, and the inner base is located within the recess.

5. The semiconductor structure according to claim 1, wherein, The width of the inner base is less than 20 nm.

6. The semiconductor structure according to claim 1, wherein, The gate structure includes epitaxially raised source / drain regions, which are made of the same material as the raised collector and the raised emitter regions.

7. The semiconductor structure according to claim 1, further comprising: Sidewall spacers located on the sidewall of the outer base isolate the outer base from both the raised collector region and the raised emitter region.

8. The semiconductor structure according to claim 1, wherein, The raised collector region and the raised emitter region comprise N+-doped semiconductor materials, and the outer base comprises P+-doped semiconductor materials, wherein the N+-doped semiconductor materials and the P+-doped semiconductor materials comprise a lateral NPN heterojunction transistor.

9. The semiconductor structure according to claim 1 further includes silicide located on the outer base.

10. A semiconductor structure comprising: A lateral heterojunction bipolar transistor located on a substrate material, the lateral heterojunction bipolar transistor comprising: The inner base region is located in the channel region of the substrate material; The outer base region is located above the inner base region; A raised collector region comprising epitaxial semiconductor material adjacent to the outer base; and A raised emitter region comprising the epitaxial semiconductor material adjacent to the outer base; and A gate structure located on the substrate material, the gate structure comprising a gate material and raised source / drain regions including the epitaxial semiconductor material; and An isolation region isolates the gate structure from the lateral heterojunction bipolar transistor. Wherein, the width of the inner base is smaller than the length of the gate structure. The inner base comprises undoped SiGe, and the outer base comprises P+ doped Si.

11. The semiconductor structure according to claim 10, wherein, The lateral heterojunction bipolar transistor includes an NPN lateral heterojunction bipolar transistor.

12. The semiconductor structure according to claim 11, wherein, The epitaxial semiconductor material of the raised emitter region and the raised collector region comprises an N+ doped semiconductor material, and the outer base comprises a P+ doped semiconductor material.

13. The semiconductor structure according to claim 12, wherein, The elevated source / drain regions comprise N+-doped semiconductor materials.

14. The semiconductor structure according to claim 10, wherein, The inner base region is laterally connected to the raised collector region and the raised emitter region.

15. The semiconductor structure according to claim 10, wherein, The outer base is isolated from the raised collector region and the raised emitter region by a sidewall spacer material located on the sidewall of the outer base.

16. The semiconductor structure of claim 10 further includes at least a silicide located on the outer base.

17. A method for manufacturing a semiconductor structure, comprising: An inner base is formed, the inner base comprising semiconductor material located in a channel region of a semiconductor substrate; An outer base is formed, which is vertically positioned above the inner base; A raised collector region is formed, the raised collector region being located on the semiconductor substrate and laterally connected to the inner base; as well as A raised emitter region is formed, which is located on the semiconductor substrate and laterally connected to the inner base. A gate structure is formed on the semiconductor substrate, wherein the width of the inner base is smaller than the gate length of the gate structure. The inner base comprises undoped SiGe, and the outer base comprises P+ doped Si.

Images