A radio frequency antenna packaging structure and a preparation method of the packaging structure

Abstract

This application relates to the field of semiconductor packaging technology, and provides a radio frequency (RF) antenna packaging structure and a method for fabricating the packaging structure. The RF antenna packaging structure includes: an IC substrate, an intermediate placement layer, an antenna cover plate, and an antenna structure. The lower surface of the IC substrate is covered with a metal layer, and an RF integrated circuit is fixed on the upper surface of the IC substrate. The IC substrate has metal through-holes extending vertically through the IC substrate. The intermediate placement layer is located on the upper surface of the IC substrate, and its upper surface is covered with a metal layer. The intermediate placement layer also has metal through-holes extending vertically through the intermediate placement layer. The antenna cover plate is located on the upper surface of the intermediate placement layer, and both its upper and lower surfaces are covered with metal layers. The antenna cover plate also has metal through-holes extending vertically through the antenna cover plate. The antenna structure is located on the upper surface of the antenna cover plate. This RF antenna packaging structure features the shortest antenna feed structure and low antenna dielectric loss, achieving a high-performance (AiP) RF antenna packaging structure with high radiation efficiency.

Description

Technical Field

[0001] This application belongs to the field of semiconductor packaging technology, and in particular relates to a radio frequency antenna packaging structure and a method for preparing the packaging structure. Background Technology

[0002] Conventional Watt phased array antennas employ an AoB (Antenna on Board) architecture. Transmitter and receiver (T / R) packaged devices are surface-mounted on the underside of the PCB (Printed Circuit Board) motherboard, while the antenna is located on the top side of the PCB motherboard. The PCB motherboard not only needs to handle low-frequency interconnect functions such as power supply and control for the T / R devices, but also needs to handle RF functions such as RF power divider / combiner networks, antenna feeding, and antenna functionality. The other side of the T / R soldering surface is covered with thermal grease or a thermal pad to achieve soft contact with the heat dissipation structure, allowing heat to dissipate downwards. The problems with the AoB architecture are: 1) The PCB is extremely complex, resulting in high design and manufacturing costs; 2) The interconnection path between the T / R and the antenna is long, requiring passage through many layers and a thick PCB motherboard, leading to high antenna feeding insertion loss; 3) The T / R's heat dissipation through a soft interface results in low heat dissipation efficiency; 4) With the antenna occupying the top side of the PCB motherboard and the T / R devices occupying the bottom side, the only way to surface-mount other power management and digital logic control devices is through horizontal expansion of the area, resulting in low area utilization.

[0003] To address the issues of the AoB architecture, existing technologies have proposed an AiP (Antenna in Package) watt-shaped phased array architecture, which offers several advantages over the AoB architecture. Several AiP implementation methods already exist. For example, AiP packages are fabricated using a fan-out multi-injection molding process, typically used for RFCMOS (Radio Frequency Complementary Metal Oxide Semiconductor) multi-channel amplitude-phase-multifunctional chip packaging. In the FaceUp active area upward method, the active surface of the chip is rewired and uses TMV (Through Molding Vias) technology to bring the power, control, and synthesis ports to the bottom pads. The antenna is implemented on top of the chip through re-injection molding and multi-layer metallization. This processing method is wafer-level processing, which is highly efficient, but it requires the selection of injection fillers with low dielectric loss. Since there are currently no injection fillers with loss characteristics comparable to those of PCBs, the antenna performance of this architecture is poor. Furthermore, injection molding is a non-hermetic packaging, which is not suitable for high-reliability applications.

[0004] It also features a double-sided lead-out packaging architecture. The main difference from the conventional single-sided lead-out packaging is that ball soldering is performed on the upper side of the cover plate before mounting the planar antenna. However, the antenna and the package are processed separately and then soldered together, resulting in poor overall stability. It is not a true AiP package. The antenna feed path is still relatively long, and the dielectric loss of the PCB material has a significant impact on the antenna, especially for high-frequency millimeter-wave applications. Furthermore, the BGA solder balls on the upper and lower layers of the package have a certain impact on the thermal gradient design and reworkability of the phased array system. Therefore, all existing AiP architectures suffer from poor antenna RF performance and low radiation efficiency due to high dielectric loss. Summary of the Invention

[0005] In view of this, the present application provides a radio frequency antenna packaging structure and a method for preparing the packaging structure, which reduces the dielectric loss of the antenna packaging structure and realizes an AiP radio frequency antenna packaging structure with strong radio frequency performance and high radiation efficiency.

[0006] This application is achieved through the following technical solution:

[0007] In a first aspect, embodiments of this application provide a radio frequency antenna packaging structure, including: an IC carrier board, an intermediate placement layer, an antenna cover plate, and an antenna structure; the lower surface of the IC carrier board is covered with a metal layer, and a radio frequency integrated circuit is fixed on the upper surface of the IC carrier board; the IC carrier board has metal through holes penetrating vertically; the intermediate placement layer is located on the upper surface of the IC carrier board, the upper surface of the intermediate placement layer is covered with a metal layer, and the intermediate placement layer has metal through holes penetrating vertically; the antenna cover plate is located on the upper surface of the intermediate placement layer, both the upper and lower surfaces of the antenna cover plate are covered with metal layers, and the antenna cover plate has metal through holes penetrating vertically; the antenna structure is located on the upper surface of the antenna cover plate.

[0008] Based on the first aspect, in some embodiments, an intermediate placement layer covers a predetermined position on the upper surface of the IC carrier board, and the position not covered by the intermediate placement layer forms a first sealed cavity, in which the radio frequency integrated circuit is located.

[0009] Based on the first aspect, in some embodiments, the IC substrate material is high-resistivity silicon, glass, HTCC, LTCC or Al2O3 ceramic material; the intermediate placement layer material is high-resistivity silicon, glass, HTCC, LTCC, Al2O3 ceramic material or metal material.

[0010] Based on the first aspect, in some embodiments, the antenna cover material is high-resistivity silicon, glass, HTCC, LTCC or Al2O3 ceramic material.

[0011] Based on the first aspect, in some embodiments, the antenna structure is made of an all-metal material or a non-metallic material with an external metal coating.

[0012] In this embodiment of the invention, the antenna made of metal or coated with metal can withstand high temperatures, which allows the encapsulation cover to be made of high-temperature welding materials such as AuSn and CuSn, without occupying the available thermal gradient of the phased array integration. The selection of solder for the bottom welding point is more flexible and the reworkability is stronger.

[0013] Based on the first aspect, in some embodiments, the lower surface of the IC substrate has solder joints in the form of BGA or QFN packages.

[0014] In a second aspect, embodiments of this application provide a method for fabricating a radio frequency antenna packaging structure, used to fabricate a radio frequency antenna packaging structure as described in any of the first aspects above, comprising: fabricating an intermediate placement layer on the upper surface of an IC substrate, wherein the intermediate placement layer covers a predetermined position on the upper surface of the IC substrate, and an opening is formed at the position not covered by the intermediate placement layer; fixing a radio frequency integrated circuit in the opening; fabricating an antenna structure on the upper surface of an antenna cover plate; fixing the lower surface of the antenna cover plate having the antenna structure to the upper surface of the intermediate placement layer; and fabricating solder joints on the lower surface of the IC substrate.

[0015] Based on the second aspect, in some embodiments, an intermediate placement layer is prepared on the upper surface of the IC substrate, including: preparing the intermediate placement layer at a predetermined position on the upper surface of the IC substrate using high-resistivity silicon, glass, HTCC, LTCC, Al2O3 ceramic or metal processes.

[0016] Based on the second aspect, in some embodiments, an antenna structure is fabricated on the upper surface of the antenna cover plate, including: fabricating an all-metal antenna structure on the upper surface of the antenna cover plate through multiple photolithography and plating processes; or, welding the all-metal antenna structure to the upper surface of the antenna cover plate through a welding process; or, fabricating a non-metallic antenna structure core on the upper surface of the antenna cover plate through a 3D printing process, and fabricating an antenna structure outside the non-metallic antenna structure core through a plating process.

[0017] Based on the second aspect, in some embodiments, fixing the lower surface of the antenna cover plate with the antenna structure to the upper surface of the intermediate placement layer includes: welding the lower surface of the antenna cover plate with the antenna structure to the upper surface of the intermediate placement layer by a welding process; or bonding the lower surface of the antenna cover plate with the antenna structure to the upper surface of the intermediate placement layer by a wafer-level bonding process.

[0018] The RF antenna packaging structure in this embodiment of the invention only needs to consider metal loss, with no (or very little) dielectric loss, enabling the antenna to achieve a wider bandwidth and higher radiation efficiency than conventional planar antennas such as LTCC, glass, and PCB. At the same time, it can still achieve highly reliable hermetically sealed packaging, and the choice of antenna cover material is more flexible, without affecting antenna performance. The above packaging structure has the shortest antenna feed path, which helps to minimize front-end feed loss.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the AoB tile phased array architecture provided in the embodiments of this application;

[0022] Figure 2 This is a schematic diagram of the AiP tile phased array architecture provided in the embodiments of this application;

[0023] Figure 3 This is a schematic diagram of the Fan-out encapsulated AiP architecture provided in the embodiments of this application;

[0024] Figure 4 This is a schematic diagram of the double-sided lead-out AiP packaging architecture provided in the embodiments of this application;

[0025] Figure 5 This is a schematic diagram of the single-sided AiP packaging architecture provided in the embodiments of this application;

[0026] Figure 6 This is a schematic diagram of the radio frequency antenna packaging structure provided in the embodiments of this application;

[0027] Figure 7 This is a schematic diagram of the fabrication method of the radio frequency antenna packaging structure provided in the embodiments of this application;

[0028] Figure 8 This is a process flow diagram of HTCC provided in the embodiments of this application;

[0029] Figure 9 This is a process flow diagram of the photolithography coating antenna structure provided in the embodiments of this application;

[0030] Figure 10 This is a three-dimensional structural diagram of the antenna cover and antenna structure provided in the embodiments of this application;

[0031] Figure 11 This is a flowchart illustrating the fabrication process of the radio frequency antenna packaging structure provided in this application. Detailed Implementation

[0032] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0033] Conventional tile-type phased array antennas employ an AoB (Antenna on Board) architecture, such as... Figure 1 As shown, the T / R (T / R transmitter and receiver) packaged device is surface-mounted on the underside of the PCB (Printed Circuit Board) motherboard, while the antenna is located on the top side of the PCB motherboard. The PCB motherboard not only needs to provide power and control for the T / R device (low-frequency interconnection functions), but also needs to handle RF functions such as RF power divider / combiner network, antenna feed, and antenna itself. The other side of the T / R soldering surface is covered with thermal grease or a thermal pad to achieve soft contact with the heat dissipation structure, allowing heat to dissipate downwards. The problems with the AoB architecture are: 1) The PCB is extremely complex, resulting in high design and manufacturing costs; 2) The interconnection path between the T / R and the antenna is long, requiring passage through a multi-layered and thick PCB motherboard, leading to high antenna feed insertion loss; 3) The T / R's heat dissipation through a soft interface results in low heat dissipation efficiency; 4) With the antenna occupying the top side of the PCB motherboard and the T / R device occupying the bottom side, the area can only be expanded horizontally to surface-mount other power management and digital logic control devices, resulting in low area utilization. The AoB architecture is suitable for low-frequency, low-cost applications. For example, the ground terminal of the Starlink low-Earth orbit internet constellation uses this AoB architecture. The chip is a mature plastic surface-mount package, which has low production cost and is conducive to large-scale production.

[0034] To address the issues of the AoB architecture, existing technologies propose an AiP (Antenna in Package) phased array architecture. The AiP architecture, which includes a PCB motherboard, offers the following advantages: it significantly shortens the feed path length from T / R to the antenna, substantially reducing antenna feed insertion loss; since the PCB motherboard no longer needs to handle antenna feed and antenna functions, its implementation difficulty is reduced; the PCB motherboard only needs to handle the power divider / combiner network RF functions, reducing the required RF layers and lowering costs; the simplified PCB functionality, reduced number of layers, and reduced thickness make it possible to function as a heat-conducting structure, and through proper design, good heat dissipation performance can be achieved through dense vias; the AiP module, PCB motherboard, and heat dissipation structure are all welded together, resulting in good structural strength and heat dissipation performance; since the AiP module only occupies the upper part of the PCB motherboard, completely freeing up the lower part, a larger contact area can be utilized for heat dissipation. Furthermore, where design allows, capacitors, power management devices, and other components can be surface-mounted on the lower part of the PCB motherboard (directly below the antenna), improving area utilization. The AiP architecture is better suited for high-performance applications with strict antenna aperture constraints.

[0035] Several AiP implementation methods already exist. For example... Figure 3 As shown, the Fan-out packaging process, involving multiple injection molding, is used to fabricate AiP packages. This is generally used for RFCMOS (Radio Frequency Complementary Metal Oxide Semiconductor) multi-channel amplitude-phase-multifunctional chip packaging. In the FaceUp method, the active side of the chip is routed through rewiring and TMV (Through Molding Vias) technology to bring the power, control, and synthesis ports to the bottom pads. The antenna is then implemented on top of the chip through re-injection molding and multi-layer metallization. This processing method is wafer-level fabrication and has high efficiency, but it requires the selection of low-loss injection fillers. Since there are currently no fillers with loss characteristics comparable to those of PCBs, antenna performance is compromised. Furthermore, injection molding packaging is not hermetically sealed, making it unsuitable for high-reliability applications.

[0036] For compound chip packaging, to avoid affecting radio frequency performance, it generally needs to be placed in an air cavity, and is usually hermetically sealed. For example... Figure 4 As shown, a double-sided lead-out package (AiP) with soldered antenna is suitable for packaging compound chips. The double-sided lead-out package comprises a carrier board and a cover plate. Figure 5The main difference between the conventional single-sided ceramic package shown is that the intermediate placement layer and the cover plate have vertical interconnect functionality. Ball-mount soldering is possible on both the upper side of the cover plate and the lower side of the carrier board. The cover plate is soldered to the antenna via a BGA (Ball Grid Array) package, and the antenna is a planar antenna. The lower side of the carrier board is soldered to the motherboard via a BGA. This method achieves a hermetically tight, high-reliability package of the compound chip with an air cavity. Simultaneously, the antenna can be designed using a low-dielectric material more suitable for antenna applications, and the choice of antenna material and process is not constrained by package reliability. However, since the antenna and package are processed separately and then soldered together, it is not a true AiP (Analog-to-Package) package.

[0037] like Figure 6 As shown, the present invention provides a radio frequency antenna packaging structure, including: an IC carrier board 1, an intermediate placement layer 2, an antenna cover plate 3, and an antenna structure 4.

[0038] The lower surface of IC carrier 1 is covered with a metal layer, and the upper surface of IC carrier 1 is fixed with radio frequency integrated circuit 5. IC carrier 1 has metal through holes that penetrate from top to bottom.

[0039] The intermediate placement layer 2 is located on the upper surface of the IC carrier board 1. The upper surface of the intermediate placement layer 2 is covered with a metal layer, and the intermediate placement layer 2 has metal through holes that penetrate the intermediate placement layer 2 vertically.

[0040] Antenna cover plate 3 is located on the upper surface of the intermediate placement layer 2. Both the upper and lower surfaces of antenna cover plate 3 are covered with a metal layer. Antenna cover plate 3 has metal through holes that penetrate vertically through the antenna cover plate 3.

[0041] Antenna structure 4 is located on the upper surface of antenna cover plate 3. Compared with planar antennas such as PCB and LTCC (Low Temperature Co-fired Ceramic), the three-dimensional antenna structure has greater design freedom, the shortest antenna feed path, and helps to minimize front-end feed loss. Due to the absence (or minimal) dielectric loss, the antenna can achieve a wider bandwidth and higher radiation efficiency than conventional planar antennas such as LTCC, glass, and PCB.

[0042] In some embodiments, the intermediate placement layer 2 covers a predetermined position on the upper surface of the IC carrier board 1, and the position not covered by the intermediate placement layer 2 forms a first sealed cavity, in which the radio frequency integrated circuit 5 is located.

[0043] Vertical interconnection is achieved through metal vias running vertically through the entire RF antenna package structure. This solves the interconnection problems of antenna feeding, power supply control, and other interfaces at the package level. Since the package level uses a higher-order processing technology than the component level, this vertical interconnection at the package level is a higher-integration, shorter-path, and higher-performance interconnection, thereby improving the overall integration and performance of the phased array device.

[0044] In some embodiments, the IC substrate 1 is made of high-resistivity silicon, glass, HTCC (High Temperature Co-fired Ceramic), LTCC, or Al2O3 ceramic. The intermediate placement layer 2 is made of high-resistivity silicon, glass, HTCC, LTCC, Al2O3 ceramic, or metal. The antenna cover 3 is made of high-resistivity silicon, glass, HTCC, LTCC, or Al2O3 ceramic.

[0045] In some embodiments, the antenna structure 4 is made of an all-metal material or a non-metal material with an external metal layer.

[0046] Antenna structures made of all-metal materials or non-metallic materials with an external metal coating can withstand high temperatures. Therefore, high-temperature welding materials such as AuSn and CuSn can be selected when packaging and sealing the antenna. This does not occupy the available thermal gradient of the phased array integration, making the selection of BGA solder more flexible and the reworkability stronger.

[0047] In some embodiments, the lower surface of the IC substrate 1 has solder points in the form of BGA (Ball Grid Array) or QFN (quad flat No-leads package).

[0048] This invention also provides a method for fabricating a radio frequency antenna packaging structure, used to fabricate the aforementioned radio frequency antenna packaging structure, such as... Figure 7 As shown, it includes steps 101 to 105.

[0049] Step 101: Prepare an intermediate placement layer 2 on the upper surface of IC carrier 1, wherein the intermediate placement layer 2 covers a predetermined position on the upper surface of IC carrier 1, and an opening is formed at the position where the intermediate placement layer 2 is not covered.

[0050] In some embodiments, an intermediate placement layer 2 can be fabricated at a predetermined position on the upper surface of the IC substrate 1 using an HTCC process. The HTCC process flow is as follows: Figure 8As shown, ceramic powder (e.g., Al2O3 or AlN) is first added to an organic binder and mixed evenly to form a paste-like slurry. Then, the slurry is scraped onto a base tape using a scraper to form a uniform film. After drying, a green ceramic tape of a certain thickness is formed. The green ceramic tape is peeled off from the base tape and rolled up for later use, which is the tape casting process. According to the design requirements, the material is sliced ​​(cut) and punched. Metal paste is used for filling holes and creating metal patterns using screen printing. Multi-layer green body lamination; cutting; high-temperature (1200-1500℃) sintering.

[0051] Step 102: Fix the radio frequency integrated circuit 5 in the opening.

[0052] Step 103: Prepare antenna structure 4 on the upper surface of antenna cover plate 3.

[0053] In some embodiments, the antenna structure 4 can be fabricated on the upper surface of the antenna cover plate 3 in any of the following three ways:

[0054] like Figure 9 As shown, an all-metal antenna structure 4 is fabricated on the upper surface of the antenna cover plate 3 through multiple photolithography and coating processes. The three-dimensional antenna is fabricated on a ceramic substrate by photolithography and coating. The processing generally requires multiple photolithography and coating processes. If necessary, planarization is performed at the end of one coating to make the surface smoother for subsequent processes and to correct height errors.

[0055] Antenna can be above Figure 9 The antenna can be processed sequentially in the middle, or it can be divided at a certain height of the antenna and the all-metal antenna structure 4 can be welded to the upper surface of the antenna cover plate 3 through welding process.

[0056] Alternatively, the antenna structure 4 can be fabricated on the upper surface of the antenna cover plate 3 using 3D printing technology, and the antenna structure 4 can be fabricated by coating the outer layer of the non-metallic antenna structure 4 core using a coating process.

[0057] The final three-dimensional structure diagram of the antenna structure on the surface of the antenna cover plate is shown below. Figure 10 As shown, in addition to the antenna structure, it also has a feed microstrip line and an auxiliary support structure.

[0058] The function of the feed microstrip line is as follows: the vertical interconnect vias are distributed near the edges, while the antenna feed point is located approximately at the center of 1 / 4 of the area. Therefore, a section of feed microstrip line is needed to connect the vertical vias to the antenna feed point.

[0059] The function of the auxiliary support structure is to protect the antenna structure without degrading its performance. The main pressure point during welding can be selected at the auxiliary support structure.

[0060] In addition, after the antenna structure is fabricated, surface treatment is required. The upper surface of the antenna cover plate and the surface of the antenna structure are plated with a thick layer of inert, high-conductivity metals such as gold or silver, or covered with a non-conductive thin film to prevent surface corrosion. At the same time, the thickness of the surface coating must ensure that the surface current is located inside the good conductor, so that the antenna structure has very little conductor loss and basically no dielectric loss.

[0061] Step 104: Fix the lower surface of the antenna cover plate 3 with antenna structure 4 to the upper surface of the intermediate placement layer 2.

[0062] In some embodiments, the lower surface of the antenna cover plate 3 having the antenna structure 4 can be welded to the upper surface of the intermediate placement layer 2 by a welding process.

[0063] Alternatively, the lower surface of the antenna cover plate 3 with antenna structure 4 can be bonded to the upper surface of the intermediate placement layer 2 using a wafer-level bonding process.

[0064] Step 105: Prepare solder joints on the lower surface of IC substrate 1.

[0065] Example 1

[0066] In such Figure 11 In the illustrated embodiment, the antenna cover plate 3 is first fabricated using HTCC technology, and the three-dimensional antenna structure 4 is prepared using a metal plating process. The IC carrier board 1 and the intermediate placement layer 2 are then fabricated using HTCC technology, and the radio frequency integrated circuit 5 is fixed to the upper surface of the IC carrier board 1. Then, AuSn is used as solder to fix the lower surface of the antenna cover plate 3 to the upper surface of the intermediate placement layer 2. Finally, balls are implanted on the lower surface of the IC carrier board 1 to prepare solder joints.

[0067] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0068] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0069] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0070] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0071] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0072] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A radio frequency antenna packaging structure, characterized in that, include: IC carrier board, intermediate placement layer, antenna cover plate and antenna structure; The lower surface of the IC carrier is covered with a metal layer, and an RF integrated circuit is fixed on the upper surface of the IC carrier. The IC carrier has metal through holes that penetrate the IC carrier from top to bottom. The intermediate placement layer is located on the upper surface of the IC carrier board. The upper surface of the intermediate placement layer is covered with a metal layer, and the intermediate placement layer has metal through holes that penetrate the intermediate placement layer from top to bottom. The antenna cover is located on the upper surface of the intermediate placement layer. Both the upper and lower surfaces of the antenna cover are covered with a metal layer. The antenna cover has metal through holes that penetrate the antenna cover from top to bottom. The antenna structure is a three-dimensional antenna structure, which is made of all-metal material or non-metal material with an external metal layer. The thickness of the external metal layer ensures that the surface current is located inside a good conductor. The antenna structure is located on the upper surface of the antenna cover plate. Vertical interconnection is achieved in the radio frequency antenna packaging structure through metal through holes running vertically.

2. The radio frequency antenna packaging structure as described in claim 1, characterized in that, The intermediate placement layer covers a predetermined position on the upper surface of the IC carrier board, and the position not covered by the intermediate placement layer forms a first sealed cavity, in which the radio frequency integrated circuit is located.

3. The radio frequency antenna packaging structure as described in claim 1, characterized in that, The IC carrier material is high-resistivity silicon, glass, HTCC, LTCC, or Al2O3 ceramic material; the intermediate placement layer material is high-resistivity silicon, glass, HTCC, LTCC, Al2O3 ceramic, or metal material.

4. The radio frequency antenna packaging structure as described in claim 1, characterized in that, The antenna cover material is high-resistivity silicon, glass, HTCC, LTCC or Al2O3 ceramic material.

5. The radio frequency antenna packaging structure as described in claim 1, characterized in that, The lower surface of the IC carrier board has solder joints in the form of BGA or QFN packages.

6. A method for fabricating a radio frequency antenna packaging structure, characterized in that, The method for fabricating a radio frequency antenna packaging structure as described in any one of claims 1 to 5, wherein vertical interconnection is achieved within the radio frequency antenna packaging structure through through-holes, comprises: An intermediate placement layer is prepared on the upper surface of an IC carrier board, wherein the intermediate placement layer covers a predetermined position on the upper surface of the IC carrier board, and an opening is formed at the position where the intermediate placement layer is not covered. A radio frequency integrated circuit is fixed in the opening; An antenna structure is fabricated on the upper surface of the antenna cover plate; The lower surface of the antenna cover plate having the antenna structure is fixed to the upper surface of the intermediate placement layer; Solder joints are prepared on the lower surface of the IC carrier board.

7. The method for fabricating the radio frequency antenna packaging structure as described in claim 6, characterized in that, The preparation of an intermediate placement layer on the upper surface of the IC carrier includes: The intermediate placement layer is prepared at a predetermined position on the upper surface of the IC substrate using high-resistivity silicon, glass, HTCC, LTCC, Al2O3 ceramic, or metal processes.

8. The method for fabricating the radio frequency antenna packaging structure as described in claim 6, characterized in that, The process of fabricating the antenna structure on the upper surface of the antenna cover plate includes: An all-metal antenna structure is fabricated on the upper surface of the antenna cover plate through multiple photolithography and coating processes. Alternatively, the antenna structure made of the all-metal material can be welded to the upper surface of the antenna cover plate using a welding process; Alternatively, the antenna structure core of the non-metallic material can be fabricated on the upper surface of the antenna cover plate using 3D printing technology, and the antenna structure can be fabricated on the outside of the antenna structure core of the non-metallic material using a coating process.

9. The method for fabricating the radio frequency antenna packaging structure as described in claim 6, characterized in that, The step of fixing the lower surface of the antenna cover plate having the antenna structure to the upper surface of the intermediate placement layer includes: The lower surface of the antenna cover plate having the antenna structure is welded to the upper surface of the intermediate placement layer using a welding process. Alternatively, the lower surface of the antenna cover plate having the antenna structure can be bonded to the upper surface of the intermediate placement layer using a wafer-level bonding process.

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