An audio automatic noise reduction circuit and control method

Abstract

This invention discloses an automatic noise reduction circuit for audio, including a processing module. The processing module comprises a first transistor, a second PMOS transistor, a first speaker, a first operational amplifier, a second operational amplifier, a first resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third polarized capacitor, a fourth polarized capacitor, and a first input terminal. The first input terminal is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the base of the first transistor. This invention solves the problem of audio signal asynchrony between the preceding and following stages when the signal source amplitude is too large.

Description

Technical Field

[0001] This invention relates to the field of audio technology, and in particular to an automatic noise reduction circuit and control method for audio equipment. Background Technology

[0002] In audio processing chip systems, the audio output signal is typically sent to an audio power amplifier as an input signal. The principle is to set a coupling capacitor between the audio signal output and the power amplifier input, amplify the signal, and then output it to the speaker. During this process, noise is filtered out by a filter. However, in existing technology, audio power amplifiers operate under high voltage and large signal conditions. When the amplitude of the signal source is too large, the subsequent stage and the received audio signal will become out of sync. Furthermore, when the reference voltage of the components at the front end of the amplifier changes, it exceeds the linear range of the amplifier's operation, resulting in distortion. Summary of the Invention

[0003] To address the aforementioned technical problems, the purpose of this invention is to provide an automatic noise reduction circuit for audio systems, including a processing module. The processing module includes a first transistor D1, a second PMOS transistor D2, a first speaker F1, a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third polarity capacitor C3, a fourth polarity capacitor C4, and a first input terminal IN1. The first input terminal IN1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the base of the first transistor D1. The collector of the first transistor D1 is connected to the inverting input of the first operational amplifier U1, one end of the eighth resistor R8, and one end of the ninth resistor R9. The emitter of the first transistor D1 is connected to ground. Operational amplifier U1 is connected to the non-inverting input of a first resistor R1 and one end of a second capacitor C2. The other end of the second capacitor C2 is connected to ground. The other end of the first resistor R1 is connected to the positive terminal of the third capacitor C3 and the drain of the second PMOS transistor D2. The source of the second PMOS transistor D2 is connected to the power supply. The gate of the second PMOS transistor D2 is connected to the output terminal of the first operational amplifier U1. The negative terminal of the third capacitor C3 is connected to the positive terminal of the fourth capacitor C4 and one end of the first speaker F1. The other end of the first speaker F1, the negative terminal of the fourth capacitor C4, and the ground are connected. The other end of the eighth resistor R8 is connected to the power supply. The other end of the ninth resistor R9 is connected to the non-inverting input of the second operational amplifier U2 and one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to ground.

[0004] Furthermore, the processing module also includes a third light-emitting diode D3, a fourth phototransistor D4, a fifth phototransistor D5, a sixth diode D6, a seventh phototransistor D7, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The third light-emitting diode D3 and the fourth phototransistor D4 are coupled and series-connected between the gate of the second PMOS transistor D2 and the output terminal of the first operational amplifier U1. The anode of the third light-emitting diode D3 is connected to the output terminal of the first operational amplifier U1, and the cathode of the third light-emitting diode D3 is connected to ground. The collector of the fourth phototransistor D4 is connected to the power supply, and the emitter of the fourth phototransistor D4 is connected to the gate of the second PMOS transistor D2. One end of the second resistor R2 is connected to the... One end of resistor R3 is connected to the power supply. The other end of resistor R2 is connected to the collector of transistor D5 and the output of operational amplifier U1. The base of transistor D5 is connected to one end of resistor R4. The other end of resistor R4 is connected to the other end of resistor R3, the anode of diode D6, and the collector of transistor D7. The cathode of diode D6 is connected to ground. The base of transistor D7 is connected to one end of resistor R5. The other end of resistor R5 is connected to the anode of diode D3. The emitter of transistor D7 is connected to ground. The output of operational amplifier U2 is connected to the collector of transistor D7. The inverting input of operational amplifier U2 is connected to one end of capacitor C2.

[0005] Furthermore, the processing module also includes a sixth resistor R6, a seventh resistor R7, and a fifth polarity capacitor C5. One end of the sixth resistor R6 is connected to the power supply, and the other end of the sixth resistor R6 is connected to one end of the first capacitor C1 and one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the ground terminal. One end of the fifth polarity capacitor C5 is connected to the ground terminal, and the other end of the fifth polarity capacitor C5 is connected to the emitter of the first transistor D1.

[0006] Furthermore, the processing module also includes an eleventh resistor R11, one end of which is connected to one end of the fifth polarity capacitor C5 and the emitter of the first transistor D1, and the other end of which is connected to the ground terminal.

[0007] Furthermore, the processing module also includes a twelfth resistor R12, which is connected in series between the collector of the fourth phototransistor D4 and the power supply.

[0008] Furthermore, the processing module also includes a thirteenth resistor R13, one end of which is connected to the gate of the second PMOS transistor D2 and the emitter of the fourth phototransistor D4, and the other end of which is connected to the ground terminal.

[0009] Furthermore, the processing module also includes a fourteenth resistor R14 and a first electret M1. One end of the fourteenth resistor R14 is connected to the power supply, and the other end is connected to one end of M1. The other end of M1 is connected to the ground terminal.

[0010] This application also provides a sound noise reduction control method, applied to an automatic sound noise reduction circuit as described in any of the above claims, comprising the following steps:

[0011] Step 1: Receive the audio signal through the audio receiver and isolate it through the coupling capacitor to obtain the coupled signal; Step 2: Amplify the coupled signal to obtain the amplified signal; Step 3: Filter and reduce the noise of the amplified signal to obtain the filtered signal; Step 4: Output the filtered signal to the speaker.

[0012] Furthermore, to prevent audio signal noise and asynchrony between the received audio signals from the preceding and following stages, when there is no audio signal or noise reduction signal at the first input terminal IN1, the first transistor D1 is in the low-range amplification state. The threshold signal is obtained by voltage division between the inverting input of the first operational amplifier U1 and the non-inverting input of the second operational amplifier U2 through the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10. The first operational amplifier U1 performs differential comparison between the non-inverting and non-inverting inputs. The signal reaches the second PMOS transistor D2 through the output terminal of the first operational amplifier U1, causing the gate-source potential of the second PMOS transistor D2 to reach a negative voltage difference for conduction. The second PMOS transistor D2 is turned on, and the power supply signal reaches the second capacitor C2 through the first resistor R1, raising the potential of the non-inverting input of the first operational amplifier U1. When the voltage level is raised, the voltage signal at the non-inverting input of the first operational amplifier U1 is greater than the voltage signal at its inverting input. The first operational amplifier U1 has no signal output. The power supply signal maintains the conduction state of the third LED D3 through the second resistor R2. Initially, the power supply signal reaches the second resistor R2 and the third resistor R3. The signal reaching the third resistor R3 forms a circuit through the third resistor R3 and the emitter of the fifth transistor D5, putting the fifth transistor D5 in an amplification state. At this time, the collector potential of the fifth transistor D5 is lower than the anode-to-cathode conduction potential of the sixth diode D6. The signal reaching the second resistor R2 passes through the fifth resistor R5 to the seventh transistor D7, putting the seventh transistor D7 in an amplification state. When the first operational amplifier U1 outputs a signal, the signal reaches the third LED. D3, via resistor R5, reaches transistor D7, saturating it. The collector junction of D7 is forward biased, making its base potential higher than the anode potential of LED D3. When operational amplifier U1 has no signal output, the signal reaches LED D3, turning it on. At this time, LED D3's potential is lower than the base potential of transistor D5. Therefore, when operational amplifier U1 has no signal output, the power signal forms a loop through resistor R2 and LED D3, keeping LED D3 on and PMOS transistor D2 off. When the potential of capacitor C2 is lower than the potential of the output terminal of operational amplifier U2... The output signal of the second operational amplifier U2 goes through three paths: one to the fourth resistor R4, one to the sixth diode D6, and one to the seventh transistor D7. After passing through the fourth resistor R4, the signal reaches the base of the fifth transistor D5, causing D5 to switch from amplification to saturation. The output signal of the second operational amplifier U2 then reaches the sixth diode D6, turning it on. At this point, the base potential of the fifth transistor D5 is greater than the anode-to-cathode potential of the sixth diode D6. This signal then reaches the seventh transistor D7, causing its collector junction to reverse bias, meaning the N-region potential is greater than the P-region potential. The third LED D3 is then cut off, and the second PMOS transistor D2 is turned on. The power signal then passes through the second PMOS transistor D2 and the first resistor R1 to reach the second capacitor C2.When an audio signal is present at the first input terminal IN1, the alternating signal is superimposed on the base signal of the first transistor D1. The first transistor D1 transitions from low-range amplification to high-range amplification, thus changing the voltage thresholds at the inverting input of the first operational amplifier U1 and the non-inverting input of the second operational amplifier U2. This increases the switching frequency of the output signals of both operational amplifiers U1 and U2. The signal is then coupled through the third polarity capacitor C3 and enters the first speaker F1, achieving synchronization between the subsequent stage and the preceding stage. The fourth polarity capacitor C4 filters out the high-frequency signal from the third polarity capacitor C3.

[0013] Furthermore, to prevent the base-emitter voltage of the first transistor D1 from being cut off due to fluctuations in the emitter signal, the power supply signal is first current-limited by the sixth resistor R6, and then enters the seventh resistor R7 for voltage division. The fifth polarity capacitor C5 compensates for the emitter signal of the first transistor D1, and the eleventh resistor R11 divides the voltage of the fifth polarity capacitor C5 to prevent the first transistor D1 from being cut off or increasing the amplification factor when the emitter reference voltage is too high or too low.

[0014] Furthermore, to prevent overcurrent after the fourth phototransistor D4 and the third light-emitting diode D3 are optically coupled, a twelfth resistor R12 is set to limit the current.

[0015] Furthermore, to prevent the parasitic capacitance of the gate of the second PMOS transistor D2 from failing to discharge and causing a malfunction in the second PMOS transistor D2, a thirteenth resistor R13 is set for discharge. At the same time, when the fourth phototransistor D4 is turned on, the power signal is pulled up through the gate of the second PMOS transistor D2.

[0016] Furthermore, considering that the audio signal can be provided by a microphone, a first electret M1 is set, and the power signal provides the working current to the internal thin film capacitor of the first electret M1 through the fourteenth resistor R14.

[0017] The advantages of this invention compared to the prior art are:

[0018] This solution addresses the issue of audio signal asynchrony between pre-amplifier and pre-amplifier stages when the signal source amplitude is too large, enabling synchronization between the pre-amplifier and pre-amplifier signals. It also resolves distortion issues caused by fluctuations in the power supply voltage of the pre-amplifier components, without requiring additional modules to expand the microphone input port. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the processing module structure of an automatic noise reduction circuit for audio equipment provided by the present invention. Detailed Implementation

[0021] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0022] Referring to the accompanying drawings, this invention is an automatic noise reduction circuit for audio equipment, including a processing module. The processing module includes a first transistor D1, a second PMOS transistor D2, a first speaker F1, a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, an eighth resistor R8, a ninth resistor R9, a first capacitor C1, a second capacitor C2, a third polarity capacitor C3, a fourth polarity capacitor C4, and a first input terminal IN1. The first input terminal IN1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the base of the first transistor D1. The collector of the first transistor D1 is connected to the inverting input of the first operational amplifier U1, one end of the eighth resistor R8, and one end of the ninth resistor R9. The emitter of the first transistor D1 is connected to ground. The first operational amplifier... The non-inverting input of amplifier U1 is connected to one end of the first resistor R1 and one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the ground terminal. The other end of the first resistor R1 is connected to the positive terminal of the third polarity capacitor C3 and the drain of the second PMOS transistor D2. The source of the second PMOS transistor D2 is connected to the power supply. The gate of the second PMOS transistor D2 is connected to the output terminal of the first operational amplifier U1. The negative terminal of the third polarity capacitor C3 is connected to the positive terminal of the fourth polarity capacitor C4 and one end of the first speaker F1. The other end of the first speaker F1, the negative terminal of the fourth polarity capacitor C4, and the ground terminal are connected. The other end of the eighth resistor R8 is connected to the power supply. The other end of the ninth resistor R9 is connected to the non-inverting input of the second operational amplifier U2 and one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to the ground terminal.

[0023] Specifically, the processing module further includes a third light-emitting diode D3, a fourth phototransistor D4, a fifth phototransistor D5, a sixth diode D6, a seventh phototransistor D7, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The third light-emitting diode D3 and the fourth phototransistor D4 are coupled and series-connected between the gate of the second PMOS transistor D2 and the output terminal of the first operational amplifier U1. The anode of the third light-emitting diode D3 is connected to the output terminal of the first operational amplifier U1, and the cathode of the third light-emitting diode D3 is connected to ground. The collector of the fourth phototransistor D4 is connected to the power supply, and the emitter of the fourth phototransistor D4 is connected to the gate of the second PMOS transistor D2. One end of the second resistor R2 is connected to the... One end of resistor R3 is connected to the power supply. The other end of resistor R2 is connected to the collector of transistor D5 and the output of operational amplifier U1. The base of transistor D5 is connected to one end of resistor R4. The other end of resistor R4 is connected to the other end of resistor R3, the anode of diode D6, and the collector of transistor D7. The cathode of diode D6 is connected to ground. The base of transistor D7 is connected to one end of resistor R5. The other end of resistor R5 is connected to the anode of diode D3. The emitter of transistor D7 is connected to ground. The output of operational amplifier U2 is connected to the collector of transistor D7. The inverting input of operational amplifier U2 is connected to one end of capacitor C2.

[0024] Specifically, the processing module further includes a sixth resistor R6, a seventh resistor R7, and a fifth polarity capacitor C5. One end of the sixth resistor R6 is connected to the power supply, and the other end of the sixth resistor R6 is connected to one end of the first capacitor C1 and one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the ground terminal. One end of the fifth polarity capacitor C5 is connected to the ground terminal, and the other end of the fifth polarity capacitor C5 is connected to the emitter of the first transistor D1.

[0025] Specifically, the processing module further includes an eleventh resistor R11, one end of which is connected to one end of the fifth polarity capacitor C5 and the emitter of the first transistor D1, and the other end of which is connected to the ground terminal.

[0026] Specifically, the processing module also includes a twelfth resistor R12, which is connected in series between the collector of the fourth phototransistor D4 and the power supply.

[0027] Specifically, the processing module further includes a thirteenth resistor R13, one end of which is connected to the gate of the second PMOS transistor D2 and the emitter of the fourth phototransistor D4, and the other end of which is connected to the ground terminal.

[0028] Specifically, the processing module also includes a fourteenth resistor R14 and a first electret M1. One end of the fourteenth resistor R14 is connected to the power supply, and the other end is connected to one end of MI. The other end of MI is connected to the ground terminal.

[0029] This application also provides a sound noise reduction control method, applied to an automatic sound noise reduction circuit as described in any of the above claims, comprising the following steps:

[0030] Step 1: Receive the audio signal through the audio receiver and isolate it through the coupling capacitor to obtain the coupled signal; Step 2: Amplify the coupled signal to obtain the amplified signal; Step 3: Filter and reduce the noise of the amplified signal to obtain the filtered signal; Step 4: Output the filtered signal to the speaker.

[0031] The working principle of this invention is as follows: To prevent audio signal noise and asynchrony between the audio signals received by the subsequent stage and the preceding stage, when there is no audio signal or noise reduction signal at the first input terminal IN1, the first transistor D1 is in the low-range amplification state. The threshold signal is obtained by voltage division between the inverting input of the first operational amplifier U1 and the non-inverting input of the second operational amplifier U2 through the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10. The first operational amplifier U1 performs differential comparison between the non-inverting input and the non-inverting input. The signal reaches the second PMOS transistor D2 through the output terminal of the first operational amplifier U1, causing the gate-source potential of the second PMOS transistor D2 to reach a negative voltage difference for conduction. The second PMOS transistor D2 is turned on, and the power supply signal reaches the second capacitor C2 through the first resistor R1, raising the potential of the non-inverting input of the first operational amplifier U1. As the potential increases, the voltage signal at the non-inverting input of the first operational amplifier U1 is greater than the voltage signal at its inverting input, resulting in no signal output from the first operational amplifier U1. The power supply signal maintains the conduction state of the third light-emitting diode D3 through the second resistor R2. Initially, the power supply signal reaches the second resistor R2 and the third resistor R3. The signal reaching the third resistor R3 forms a circuit through the third resistor R3 and the emitter of the fifth transistor D5, putting the fifth transistor D5 in an amplification state. At this time, the collector potential of the fifth transistor D5 is lower than the anode-to-cathode conduction potential of the sixth diode D6. The signal reaching the second resistor R2 reaches the seventh transistor D7 through the fifth resistor R5, putting the seventh transistor D7 in an amplification state. When the first operational amplifier U1 outputs a signal, the signal reaches the third light-emitting diode D3 in one path. Another path from transistor D3 leads to transistor D7 via resistor R5, saturating transistor D7. The forward bias of transistor D7's collector junction causes its base potential to be higher than the anode potential of diode D3. When operational amplifier U1 has no signal output, the signal reaches diode D3, turning it on. At this time, diode D3's potential is lower than the base potential of transistor D5. Therefore, when operational amplifier U1 has no signal output, the power signal forms a loop through resistor R2 and diode D3, keeping diode D3 on and PMOS transistor D2 off. When the potential of capacitor C2 is lower than the voltage across the terminal of operational amplifier U2... When the second operational amplifier U2 is in operation, the output signal goes through three paths: one to the fourth resistor R4, one to the sixth diode D6, and one to the seventh transistor D7. After passing through the fourth resistor R4, the signal reaches the base of the fifth transistor D5, causing D5 to switch from amplification to saturation. The output signal from the second operational amplifier U2 then reaches the sixth diode D6, turning it on. At this point, the base potential of the fifth transistor D5 is greater than the anode-to-cathode potential of the sixth diode D6. This signal then reaches the seventh transistor D7, causing its collector junction to reverse bias, meaning the N-region potential is greater than the P-region potential. The third LED D3 is then off, and the second PMOS transistor D2 is on. The power signal then passes through the second PMOS transistor D2 and the first resistor R1 to reach the second capacitor C2.When an audio signal is present at the first input terminal IN1, the alternating signal is superimposed on the base signal of the first transistor D1. The first transistor D1 transitions from low-range amplification to high-range amplification, thus changing the voltage thresholds at the inverting input of the first operational amplifier U1 and the non-inverting input of the second operational amplifier U2. This increases the switching frequency of the output signals of both operational amplifiers U1 and U2. The signal is then coupled through the third polarity capacitor C3 and enters the first speaker F1, achieving synchronization between the subsequent stage and the preceding stage. The fourth polarity capacitor C4 filters out the high-frequency signal from the third polarity capacitor C3.

[0032] Specifically, to prevent the base-emitter voltage of the first transistor D1 from being cut off due to fluctuations in the emitter signal, the power supply signal is first current-limited by the sixth resistor R6, and then enters the seventh resistor R7 for voltage division. The fifth polarity capacitor C5 compensates for the emitter signal of the first transistor D1, and the eleventh resistor R11 divides the voltage of the fifth polarity capacitor C5 to prevent the first transistor D1 from being cut off or increasing the amplification factor when the emitter reference voltage is too high or too low.

[0033] Specifically, to prevent overcurrent after the fourth phototransistor D4 and the third light-emitting diode D3 are optically coupled, a twelfth resistor R12 is set to limit the current.

[0034] Specifically, to prevent the parasitic capacitance of the gate of the second PMOS transistor D2 from failing to discharge and causing the second PMOS transistor D2 to malfunction, a thirteenth resistor R13 is set to discharge the load. At the same time, when the fourth phototransistor D4 is turned on, the power signal is pulled up through the gate of the second PMOS transistor D2.

[0035] Specifically, considering that the audio signal can be provided by a microphone, a first electret M1 is set, and the power signal provides the working current to the internal thin film capacitor of the first electret M1 through the fourteenth resistor R14.

Claims

1. An automatic noise reduction circuit for audio systems, comprising a processing module, characterized in that, The processing module includes a first transistor, a second PMOS transistor, a first speaker, a first operational amplifier, a second operational amplifier, a first resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third polarized capacitor, a fourth polarized capacitor, a first input terminal, a third light-emitting diode, a fourth phototransistor, a fifth transistor, a sixth diode, a seventh transistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The first input terminal is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the base of the first transistor. The collector of the first transistor is opposite to the first operational amplifier. The phase input, one end of the eighth resistor, and one end of the ninth resistor are connected. The emitter of the first transistor is connected to ground. The non-inverting input of the first operational amplifier is connected to one end of the first resistor and one end of the second capacitor. The other end of the second capacitor is connected to ground. The other end of the first resistor is connected to the positive terminal of the third capacitor and the drain of the second PMOS transistor. The source of the second PMOS transistor is connected to the power supply. The gate of the second PMOS transistor is connected to the output of the first operational amplifier. The negative terminal of the third capacitor, the positive terminal of the fourth capacitor, and one end of the first speaker are connected. The other end of the first speaker, the negative terminal of the fourth capacitor, and ground are connected. The other end of the eighth resistor is connected to the power supply; the other end of the ninth resistor is connected to the non-inverting input of the second operational amplifier and one end of the tenth resistor; the other end of the tenth resistor is connected to the ground terminal. The third light-emitting diode and the fourth phototransistor are coupled and connected in series between the gate of the second PMOS transistor and the output terminal of the first operational amplifier. The anode of the third light-emitting diode is connected to the output terminal of the first operational amplifier, and the cathode of the third light-emitting diode is connected to the ground terminal. The collector of the fourth phototransistor is connected to the power supply, and the emitter of the fourth phototransistor is connected to the gate of the second PMOS transistor. One end of the second resistor is connected to one end of the third resistor and the power supply. The other end of the second resistor is connected to the collector of the fifth phototransistor and the output terminal of the first operational amplifier. The base of the fifth phototransistor is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to the other end of the third resistor, the anode of the sixth diode, and the collector of the seventh phototransistor. The cathode of the sixth diode is connected to the ground terminal. The base of the seventh phototransistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the anode of the third light-emitting diode. The emitter of the seventh phototransistor is connected to the ground terminal. The output terminal of the second operational amplifier is connected to the collector of the seventh phototransistor. The inverting input of the second operational amplifier is connected to one end of the second capacitor.

2. The automatic noise reduction circuit for audio equipment according to claim 1, characterized in that, The processing module also includes a sixth resistor, a seventh resistor, and a fifth polarity capacitor. One end of the sixth resistor is connected to the power supply, and the other end of the sixth resistor is connected to one end of the first capacitor and one end of the seventh resistor. The other end of the seventh resistor is connected to the ground terminal. One end of the fifth polarity capacitor is connected to the ground terminal, and the other end of the fifth polarity capacitor is connected to the emitter of the first transistor.

3. The automatic noise reduction circuit for audio systems according to claim 2, characterized in that, The processing module also includes an eleventh resistor, one end of which is connected to one end of the fifth polarity capacitor and the emitter of the first transistor, and the other end of which is connected to the ground terminal.

4. The automatic noise reduction circuit for audio systems according to claim 1, characterized in that, The processing module also includes a twelfth resistor, which is connected in series between the collector of the fourth phototransistor and the power supply.

5. The automatic noise reduction circuit for audio systems according to claim 1, characterized in that, The processing module also includes a thirteenth resistor, one end of which is connected to the gate of the second PMOS transistor and the emitter of the fourth phototransistor, and the other end of which is connected to the ground terminal.

6. The automatic noise reduction circuit for audio equipment according to claim 1, characterized in that, The processing module further includes a fourteenth resistor and a first electret. One end of the fourteenth resistor is connected to a power supply, and the other end is connected to one end of the first electret. The other end of the first electret is connected to a ground terminal.

7. A method for controlling audio noise reduction, applied to an automatic audio noise reduction circuit as described in any one of claims 1-6, characterized in that, The steps are as follows: Step 1: Receive the audio signal through the audio receiver and isolate it through the coupling capacitor to obtain the coupled signal; Step 2: Amplify the coupled signal to obtain the amplified signal; Step 3: Filter and reduce noise on the amplified signal to obtain the filtered signal; Step 4: Output the filtered signal to the speaker.

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