Configurable storage granularity for video / image recording

Abstract

Embodiments of the present application relate to configurable storage granularity for video / image recording. A memory system is disclosed having multiple address tables for translating logical addresses to physical addresses at different levels of granularity. For example, a first address table is associated with translating logical addresses for accessing system files and application files at a first block size; and a second address table is associated with translating logical addresses for storing and / or retrieving data from an image sensor of a surveillance camera at a second block size. A user interface can be used to access configuration options to specify the second block size; and a user can indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size, and thus configure the second address table for a partition used to record the image or video file.

Description

Technical Field

[0001] At least some of the embodiments disclosed herein relate generally to memory systems, and more specifically to, but not limited to, techniques for controlling write operations in memory systems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One embodiment of this disclosure provides an apparatus comprising: a memory cell; an interface configured to receive a write request to write data to the memory cell; and a flash memory translation layer. The flash memory translation layer includes: a first address table associated with a first block size for converting logical addresses specified in a first portion of the write request to physical addresses; a second address table associated with a second block size for converting logical addresses specified in a second portion of the write request to physical addresses; and a processing means configured to perform address translation using the first address table and the second address table, respectively, according to the first block size and the second block size.

[0004] Another embodiment of this disclosure provides a digital camera including: an image sensor; a microprocessor; and a storage device. The storage device has: a memory cell; a host interface configured to receive from the microprocessor a write request to record image data into the memory cell; a first address table configured to translate logical addresses to physical addresses according to a first block size; a second address table configured to translate logical addresses to physical addresses according to a second block size; and a controller configured to perform address translation using the second address table for requests associated with second data generated by the image sensor, and to perform address translation using the first address table for requests associated with first data.

[0005] Another embodiment of this disclosure provides a non-transitory computer storage device that stores instructions that, when executed by a computing device, cause the computing device to perform a method. The method includes: receiving at a host interface of the storage device a request to access a memory cell in the storage device to store or retrieve data, the request including a write request to store data generated by an image sensor; converting a logical address to a physical address using a first address table according to a first block size in response to a first request not associated with the data generated by the image sensor; and converting the logical address to a physical address using a second address table according to a second block size in response to a second request associated with the data generated by the image sensor. Attached Figure Description

[0006] The embodiments are illustrated by way of example rather than limitation in the accompanying drawings, in which similar reference numerals indicate similar elements.

[0007] Figure 1 A technique for customizing storage granularity when recording data from an image sensor, according to one embodiment, is illustrated.

[0008] Figure 2 A digital camera with a storage device according to one embodiment is shown, the storage device having customizable storage granularity for media files.

[0009] Figure 3 A method for customizing storage granularity according to one embodiment is shown.

[0010] Figure 4 An example computing system with a memory subsystem according to some embodiments of the present disclosure is shown.

[0011] Figure 5 An integrated circuit memory device configured according to one embodiment is shown.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0013] At least some aspects of this disclosure relate to a memory subsystem utilizing a technique for controlling the granularity of write operations in a portion of a memory subsystem for recording image or video data from an image sensor of a digital camera, independent of the granularity of other types of data, based on user-configurable options.

[0014] Conventional storage devices can read or write data blocks according to a predetermined granularity or size. The host system of the storage device sends a read or write request for a data block to the storage device according to the predetermined granularity or block size. The block size corresponds to the minimum amount of data that can be addressed by the host system in the read or write request. In response to a write request from the host system, the storage device can perform a series of write operations to write the block-sized data to a non-volatile storage medium, such as a memory cell formed on an integrated circuit die. The write request is considered successful when the entire block-sized data block has been written, programmed, or committed to the non-volatile storage medium. The write request is considered incomplete or has failed when any part of the block of said size fails to be committed to the non-volatile storage medium. The host system uses the logical address of the data block to specify the location of the block. The storage device uses a logic-to-physical address table to translate the logical address specified in the read or write request into the physical address of the memory cell, at which the read or write operation is performed. The logic-to-physical address table translates the logical address of the data block of the predetermined granularity or block size. Block sizes are typically configured with a granularity between 512B and 1KB. This granularity for writing data to storage devices works well for system files and application software. However, for video / image files that are typically larger than 1MB, this granularity is not very effective. When large amounts of data are divided into multiple blocks according to relatively small granularity or block size, the data can be written to storage devices via a set of write requests, which may appear as random writes of unrelated data during the execution of the write requests. When write requests are executed for unrelated data, the write requests result in data blocks being written to random memory cells. When surveillance cameras frequently write new images or videos to storage space previously used for recorded images and videos, random writes can lead to high write amplification and reduced durability of the storage media.

[0015] At least some aspects of this disclosure address the aforementioned and other deficiencies and / or challenges by configuring the storage device to perform logical-to-physical address translation (LDRT) with different granularities for different types of data. For example, users can be provided with configurable options for setting memory regions, partitions, or namespaces used to record video and / or image data from image sensors of security cameras. Configurable options can be used to indicate the typical file size of the recorded video and / or images. The storage device is configured to use information to set the granularity of the LRT performed for storing and accessing video and / or images from image sensors. Configurable options specified for recording video and / or images do not change the granularity of the LRT used for storing and accessing other types of data such as firmware, applications, activity logs, etc. Optionally, the configuration options can be one-time programmable options. For example, once the configuration options are specified when security cameras are initially deployed or images / videos are initially recorded into the storage device, they cannot be further changed or adjusted. Alternatively, the granularity option for recording video / image data can be adjusted after initial setup. For example, after erasing previously recorded video / image content from a partition or namespace, the partition or namespace can be reconfigured for video / image recording using a different, adjusted granularity for subsequent recordings. In one embodiment, the storage device is initially configured with a default logical-to-physical address table at a default granularity (e.g., between 512B and 1KB). When the user specifies a different granularity for recording video and / or image data, the storage device generates additional logical-to-physical address tables (e.g., for individual partitions or namespaces) to track the storage of video / image files at a granularity much larger than that used in the default logical-to-physical address table. Both tables can be used for different types of data simultaneously. Optionally, the storage device can monitor storage usage patterns using image sensors in security cameras to determine the optimal block size for video / images and reconfigure the granularity of video / image partitions to optimize performance, write amplification, and / or durability. For example, the storage device can automatically create a new namespace with the new granularity, migrate data from the old namespace to the new namespace, and replace the old namespace with the new namespace.

[0016] The following combination Figure 4 This describes examples of storage devices and memory modules as a memory subsystem. Typically, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0017] Figure 1 A technique for customizing storage granularity when recording data from an image sensor, according to one embodiment, is illustrated.

[0018] exist Figure 1 In this embodiment, image sensor 159 is configured to generate image files and / or video files 155. Image files and / or video files 155 are stored according to address table 109 having block size 105. The same device may store system files and / or application files 151 according to another address table 107 having a different block size 103.

[0019] A user interface 101 is provided to specify a block size 105. For example, the user interface 101 may request the user to identify the typical size of an image file or video file 155 generated by the image sensor 159. Based on the typical file size identified in the user interface 101, the block size 105 can be calculated using a predetermined formula to reduce random writes and write amplification associated with frequent writes and rewrites of image files or video files in the storage device.

[0020] Address table 109 contains data specifying the mapping between logical blocks (e.g., 131, 133, ..., or 135) and physical blocks (e.g., 141, 143, ..., 145). Image sensor 159 can specify the address of a logical block (e.g., 131) used to store data blocks of image or video files 155. Address table 109 specifies the addresses of physical blocks of memory (e.g., 141) to store data blocks of block size 105.

[0021] For example, the memory of a storage device can be formed as an integrated circuit memory device (e.g., Figure 5 Memory cells on a memory device (e.g., 419). Memory cells on a memory device (e.g., 419) can be configured with a structure of pages and blocks, wherein a single-page memory cell is the smallest unit of memory cells that can be programmed in a single operation, and a block of multi-page memory cells is the smallest unit of memory cells that can be erased without erasing other memory cells. Therefore, physical block 141 can contain multiple pages that can be in multiple blocks. A mapping from logical block 131 to physical block 141 can be constructed to reduce the erasure of data not in physical block 141, thereby reducing write amplification.

[0022] Address table 107 maps logical blocks (e.g., 111, 113, ..., 115) to physical blocks (121, 123, ..., 125) according to different block sizes 103. Typically, the block size 105 of image files and / or video files 155 is configured to be larger than the block size 103 of system files 151 and / or application files 151.

[0023] In some implementations, the image sensor 159 includes logic circuitry for generating write requests to an image file or video file 155 having a logical address configured according to block size 105.

[0024] Alternatively, image sensor 159 can provide data / content of image file or video file 155 to processing device 153, which acts as a storage device (e.g., Figure 4 The host system of the memory subsystem 407 generates a write request based on the block size 105.

[0025] The processing device 153 can be configured to perform operations, such as processing image files and / or video files 155, operating the image sensor 159, and transmitting image files or video files 155 to a remote server via the communication interface 157, through instructions contained in the system file 151 and / or application file. Figure 2 As shown.

[0026] Figure 2 A digital camera 201 with a storage device 203 according to one embodiment is shown, the storage device having customizable storage granularity for media files.

[0027] exist Figure 2 In this configuration, storage device 203 is configured to have two regions, 207 and 209. For example, each region (207 and 209) can be configured as a partition or namespace of the storage capacity of storage device 203. Physical blocks (e.g., 141, 143, ..., 145; or 121, 123, ..., 125) specify the location of the memory cell corresponding to the region (e.g., 207 or 209).

[0028] For example, region 209 with a relatively large block size 105 can be used to store media file 255 containing data generated by image sensor 159. Region 207 with a relatively small block size 103 can be used to store other files, such as firmware 251, system files, and / or application files 151.

[0029] As in Figure 1 In this context, address table 109 has a granularity corresponding to block size 105; and address table 107 has a granularity corresponding to block size 103.

[0030] The storage device 203 has a controller 213 that is configured (e.g., via firmware and / or logic circuitry) to perform address translation using different address tables 107 and 109 with different block sizes 103 and 105.

[0031] The digital camera 201 may include a lens 205, a microprocessor 223, a network interface 221, and a storage device 203. The microprocessor 223 can be configured via instructions in system files and / or application files 151 stored in area 207; and image files and / or video files 155 generated by the image sensor 159 and / or the microprocessor 223 are written to area 209.

[0032] When the controller 213 determines that the write request has a logical address in region 209, the controller 213 uses address table 109 to perform a translation to a physical address based on block size 105.

[0033] Similarly, when controller 213 determines that a write request has a logical address in region 207, controller 213 uses address table 107 to perform a translation to a physical address based on block size 103.

[0034] System files and / or application files 151 stored in region 207 may contain instructions that can be executed by microprocessor 223 to present user interface 101 to specify block size 105.

[0035] For example, in some implementations, the user interface 101 can be accessed via the network interface 221 of the digital camera 201 to receive an indication of block size 105, such as the typical size of an image file or video file 155 recorded to storage device 203. Alternatively, another interface, such as a Universal Serial Bus (USB) interface, can be used to connect the digital camera 201 to a computer to present the user interface 101.

[0036] In some implementations, storage device 203 is a removable storage device 203. Storage device 203 can be connected to a computer to set block size 105 (e.g., using an application running on the computer) before being connected to digital camera 201 (e.g., by configuring a media slot on digital camera 201).

[0037] Digital camera 201 can connect to server 231 via Internet 225 (or local area network or intranet) to implement surveillance applications.

[0038] For example, server 231 may include security application 253 to retrieve media file 255 from storage device 203 in response to certain conditions detected at digital camera 201 and / or other devices. Media file 255 may contain image file or video file 155 stored in region 209 having a block size 105.

[0039] Optionally, server 231 can monitor the media files 255 stored in region 209, such as the typical file size of image files and / or video files generated from data provided by image sensor 159. Based on the typical file size, server 231 can select block size 105 and instruct storage device 203 to switch to using a different block size to record media files 255.

[0040] For example, after erasing files in region 209, microprocessor 223 and / or controller 213 can reconfigure address table 109 with an alternative block size.

[0041] In another instance, microprocessor 223 and / or controller 213 may create a separate address table for the new block size and generate a mapping between the logical addresses associated with address table 109 for the old block size 105 and the logical addresses associated with the new block size. This mapping table allows the use of both the old block size 105 and the new block size during the migration to the new block size. Upon completion of the migration, the mapping table and address table 109 containing the old block size 105 may be deleted.

[0042] Figure 3 A method for customizing storage granularity according to one embodiment is illustrated. The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software / firmware (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is at least partially comprised of… Figure 4 Controller 409 Figure 5 The processing logic and / or memory device 419 Figure 4 The processing device 403 of the host system 401 executes the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0043] For example, Figure 3 The method can be achieved through Figure 2 The storage manager (e.g., 413) in the digital camera 201 and / or its storage device 203 utilizes Figure 1 It is implemented using address mapping technology.

[0044] At frame 301, storage device 203 receives a request at host interface 211 to access memory cells in storage device 203 to store or retrieve data.

[0045] For example, the data may include firmware 251 for operating the digital camera 201, system files and / or application files 151 in the digital camera 201, etc. Furthermore, the data may include media files 255 that record image files and / or video files 155 created by the image sensor 159 of the digital camera 201.

[0046] At block 303, storage device 203, in response to a first request associated with system files and application files 151, uses a first address table 107 to translate logical addresses into physical addresses based on a first block size 103. Such files typically have a smaller size compared to image files and video files 155 generated using image sensor 159.

[0047] At box 305, an option is presented to specify a second block size 105 for recording data generated by image sensor 159.

[0048] For example, configuration options can be presented through user interface 101 when setting up digital camera 201 for monitoring the area of ​​interest. Optionally, user interface 101 can be accessed via a network connection made through network interface 221 of digital camera 201 and / or by connecting digital camera 201 and / or storage device 203 to a computer.

[0049] At box 307, the storage manager (e.g., 413) receives an indication of the file size of the data to be recorded by the image sensor 159. The file size may depend on the monitoring operation of the digital camera 201 and / or the configuration of the security application 253 in the server 231 using the digital camera 201. The file size may be a function of the resolution of the image file, the duration of video clip recording, etc.

[0050] At box 309, the storage manager (e.g., 413) determines the size of the second block 105 based on the file size.

[0051] At box 311, the storage manager (e.g., 413) generates partitions for recording data generated by the image sensor.

[0052] At block 313, storage device 203, in response to a second request associated with data generated by an image sensor, uses a second address table to translate a logical address into a physical address according to a second block size 105.

[0053] In one implementation, storage device 203 is initially configured to record media files in the same partition or namespace (e.g., region 207) as firmware 251. When a second block size 105 is determined (e.g., via a user interface and / or configuration options), a separate partition or namespace (e.g., region 209) is created for recording media files 255 containing data from image sensor 159. A first address table and / or a second address table may be configured in the flash memory translation layer of storage device 203.

[0054] Alternatively, storage device 203 is initially configured to have separate partitions or namespaces for different types of files (e.g., regions 207 and 209); and region 209 for recording media file 255 may have a default block size 105. When configuration options cause the block size 105 for recording data from image sensor 159 to be different, address table 109 can be reconfigured for new records recorded using the old block size 105 (e.g., after erasing old media file 255).

[0055] Optionally, the storage manager (e.g., 413) can monitor the size of the media file 255 and determine the optimal block size 105. After determining the optimal block size 105, the storage manager (e.g., 413) can reconfigure the region 209 to use the new address table 109 based on the optimal block size 105.

[0056] Once address table 109 is set to use block size 105 to access region 209, storage device 203 can instruct microprocessor 223 to use the logical address configured according to block size 105 to access media file 255 in region 209.

[0057] Figure 4 An example computing system 400 including a memory subsystem 407 is illustrated according to some embodiments of the present disclosure. The memory subsystem 407 may include media such as one or more volatile memory devices (e.g., memory device 417), one or more non-volatile memory devices (e.g., memory device 419), or a combination of such memory devices.

[0058] The memory subsystem 407 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0059] The computing system 400 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0060] The computing system 400 may include a host system 401 coupled to one or more memory subsystems 407. Figure 4 An example of a host system 401 coupled to a memory subsystem 407 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0061] The host system 401 may include a processor chipset (e.g., processing device 403) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 405) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 401 uses the memory subsystem 407, for example, writing data to and reading data from the memory subsystem 407.

[0062] Host system 401 can be coupled to storage subsystem 407 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Connected SCSI (SAS) interfaces, Dual Data Rate (DDR) Memory Bus interfaces, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting DDR), Open NAND Flash Interface (ONFI), DDR interfaces, Low Power DDR (LPDDR) interfaces, or any other interfaces. The physical host interface can be used to transfer data between host system 401 and storage subsystem 407. When storage subsystem 407 is coupled to host system 401 via a PCIe interface, host system 401 can further utilize an NVM Fast (NVMe) interface to access components (e.g., storage device 419). The physical host interface can provide an interface for passing control, address, data and other signals between the memory subsystem 407 and the host system 401. Figure 4 Memory subsystem 407 is shown as an example. Typically, host system 401 can access multiple memory subsystems through the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0063] The processing device 403 of the host system 401 may be, for example, a microprocessor, a central processing unit (CPU), a processor core, an execution unit, a system-on-a-chip (SoC), etc. In some cases, the controller 405 may be referred to as a memory controller, a memory management unit, and / or a starter. In one example, the controller 405 controls communication via a bus coupled between the host system 401 and the memory subsystem 407. Typically, the controller 405 may send commands or requests to the memory subsystem 407 to perform desired access to memory devices 419, 417. The controller 405 may further include an interface circuitry for communicating with the memory subsystem 407. The interface circuitry can translate responses received from the memory subsystem 407 into information for the host system 401.

[0064] The controller 405 of the host system 401 can communicate with the controller 409 of the memory subsystem 407 to perform operations such as reading data, writing data, or erasing data at memory devices 419, 417, and other such operations. In some cases, the controller 405 is integrated within the same package as the processing device 403. In other cases, the controller 405 is packaged separately from the processing device 403. The controller 405 and / or the processing device 403 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or combinations thereof. The controller 405 and / or the processing device 403 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0065] Memory devices 419 and 417 may contain different types of non-volatile memory components and / or any combination of volatile memory components. Volatile memory devices (e.g., memory device 417) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0066] Some examples of non-volatile memory components include NAND flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without previously erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0067] Each memory device in memory device 419 may contain one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each memory device in memory device 419 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination of such memory cells. In some embodiments, a particular memory device may contain an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of a memory cell. The memory cells of memory device 419 may be grouped into pages, which may refer to logical units of a memory device used for storing data. Using some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0068] Although non-volatile memory devices such as 3D crosspoint type and NAND type memory (e.g. 2D NAND, 3D NAND) are described, memory device 419 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0069] The memory subsystem controller 409 (or, for simplicity, controller 409) can communicate with the memory device 419 to perform operations at the memory device 419 such as reading data, writing data, or erasing data, as well as other such operations (e.g., in response to commands scheduled on the command bus by controller 405). Controller 409 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (e.g., hard-coded) logic to perform the operations described herein. Controller 409 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0070] The controller 409 may include a processing means 415 (e.g., a processor) configured to execute instructions stored in local memory 411. In the example shown, the local memory 411 of the controller 409 includes embedded memory configured to store instructions for performing operations of the control memory subsystem 407 (including handling communication between the memory subsystem 407 and the host system 401).

[0071] In some embodiments, local memory 411 may include memory registers storing memory pointers, acquired data, etc. Local memory 411 may also include read-only memory (ROM) for storing microcode. Although Figure 4 The example memory subsystem 407 is shown to include a controller 409, but in another embodiment of this disclosure, the memory subsystem 407 does not include a controller 409 and may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0072] Typically, controller 409 can receive commands or operations from host system 401 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory device 419. Controller 409 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 419. Controller 409 may further include host interface circuitry for communicating with host system 401 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing memory device 419 and responses associated with memory device 419 into information for host system 401.

[0073] The memory subsystem 407 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 407 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the controller 409 and decode the addresses to access the memory device 419.

[0074] In some embodiments, memory device 419 includes a local media controller 421 that operates in conjunction with a memory subsystem controller 409 to perform operations on one or more memory cells of memory device 419. An external controller (e.g., memory subsystem controller 409) may externally manage memory device 419 (e.g., perform media management operations on memory device 419). In some embodiments, memory device 419 is a managed memory device, which is a raw memory device that is combined with a local controller (e.g., local media controller 421) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0075] Controller 409 and / or memory device 419 may include a memory manager 413 configured to customize memory granularity. In some embodiments, controller 409 in memory subsystem 407 and / or controller 421 in memory device 419 may include at least a portion of memory manager 413. In some embodiments or combinations, controller 405 and / or processing device 403 in host system 401 include at least a portion of memory manager 413. For example, controller 409, controller 405, and / or processing device 403 may include a logic circuitry system implementing memory manager 413. For example, controller 409 or processing device 403 (e.g., processor) of host system 401 may be configured to execute instructions stored in memory to perform the operation of memory manager 413 as described herein. In some embodiments, memory manager 413 is implemented in an integrated circuit chip disposed in memory subsystem 407. In other embodiments, memory manager 413 may be part of firmware of memory subsystem 407, host system 401's operating system, device driver, or application, or any combination thereof.

[0076] For example, the memory manager 413 implemented in controller 409 and / or controller 421 can be configured via instructions and / or logic circuitry to customize the memory granularity.

[0077] Figure 5 An integrated circuit memory device configured according to one embodiment is shown. For example, Figure 4 The memory device 419 in the memory subsystem 407 can be used Figure 5 The integrated circuit memory device 419 is used for implementation.

[0078] The integrated circuit memory device 419 can be encapsulated in a single integrated circuit package. The integrated circuit memory device 419 includes multiple memory cell groups 431, ..., 433 that can be formed in one or more integrated circuit dies. Typical memory cells in group 431 (or group 433) can be programmed to store one or more data bits.

[0079] Some memory cells in integrated circuit memory device 419 can be configured to operate together for specific types of operations. For example, memory cells on an integrated circuit die can be organized in planes, blocks, and pages. A plane contains multiple blocks; a block contains multiple pages; and a page can have multiple strings of memory cells. For example, an integrated circuit die can be the smallest unit that can independently execute commands or report status; the same parallel operations can be performed in parallel on multiple planes of the integrated circuit die; a block can be the smallest unit that performs an erase operation; and a page can be the smallest unit that performs data program operations (for writing data to memory cells). Each string has memory cells connected to a common bit line; and control gates for memory cells located at the same position in a string within a block or page are connected to a common word line. Control signals can be applied to word lines and bit lines to address individual memory cells.

[0080] Integrated circuit memory device 419 has a communication interface 447 for receiving a command with address 437 from controller 409 of memory subsystem 407, retrieving memory data 445 from a memory cell identified by memory address 437, and providing at least the memory data 445 as part of a response to the command. Optionally, memory device 419 can decode memory data 445 (e.g., using error correction code (ECC) technology) and provide the decoded data as part of a response to the command. Address decoder 435 of integrated circuit memory device 419 translates address 437 into a control signal to select a group of memory cells in integrated circuit memory device 419; and read / write circuitry 441 of integrated circuit memory device 419 performs an operation to determine the memory data 445 stored in the memory cell at address 437.

[0081] The integrated circuit memory device 419 has a set of latches 443 or buffers to temporarily hold memory data 445 while the read / write circuit 441 programs the threshold voltage of the memory cell group (e.g., 431 or 433) to store data, or evaluates the threshold voltage of the memory cell group (e.g., 433 or 431) to retrieve data.

[0082] Figure 6An example machine is shown as a computer system 460, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 460 may correspond to a host system (e.g., Figure 4 The host system 401 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 4 The memory subsystem 407) or can be used to perform operations of the memory manager 413 (e.g., execute instructions to perform reference). Figures 1 to 5 (The described operation corresponds to storage manager 413). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0083] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying the actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set of instructions (or more sets of instructions) to perform any or more of the methods discussed herein.

[0084] Example computer system 460 includes processing devices 467 that communicate with each other via bus 471 (which may include multiple buses), main memory 465 (e.g., read-only memory (ROM); flash memory; dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and data storage system 473.

[0085] Processing device 467 may be one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 467 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations thereof. Processing device 467 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 467 is configured to execute instructions 469 for performing the operations and steps discussed herein. Computer system 460 may further include network interface device 463 for communication via network 461.

[0086] Data storage system 473 may include machine-readable medium 475 (also referred to as computer-readable medium) on which one or more instruction sets 469 or software embodying any one or more methods or functions described herein are stored. Instructions 469 may also reside wholly or at least partially within main memory 465 and / or processing device 467 during execution by computer system 460, which also constitute machine-readable storage medium. Machine-readable medium 475, data storage system 473, and / or main memory 465 may correspond to... Figure 4 The memory subsystem 407.

[0087] In one embodiment, instruction 469 includes instructions for implementing storage manager 413 (e.g., reference 413). Figures 1 to 5 The instructions corresponding to the functions of the described storage manager 413. Although the machine-readable medium 475 shown in the example embodiment is a single medium, the term "machine-readable storage medium" should be considered as including a single medium or multiple media storing the one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding a set of instructions for use by a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0088] Parts of the description described above have been presented in the form of algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical manipulation of physical quantities. Typically, though not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily for general reasons.

[0089] However, it should be remembered that all terms in these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the operation and process of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the registers and memories of the computer system and transforms it into other data represented as physical quantities in a similar manner in the memory or registers or other such information storage systems of the computer system.

[0090] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically configured for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices for performing the methods described herein. The structures for various such systems will be shown as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0092] This disclosure may be provided in the form of a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0093] In this specification, various functions and operations may be described as being executed or caused by computer instructions for the sake of simplicity. However, those skilled in the art will recognize that such expressions mean that the function is produced by one or more controllers or processors, such as microprocessors, executing computer instructions. Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems, such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), with or without software instructions. Embodiments may be implemented using hard-wired circuit systems without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any specific combination of hardware circuit systems and software, nor to any particular source of instructions executed by a data processing system.

[0094] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific exemplary examples. It will be apparent that various modifications can be made to the embodiments without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Therefore, the specification and drawings are to be considered illustrative in nature and not restrictive.

Claims

1. An apparatus comprising: Memory cell; An interface configured to receive write requests to write data to the memory cell; Flash conversion layer, the flash conversion layer comprising: A first address table, configured to translate logical addresses specified in the first part of the write request into physical addresses based on a first block size; A second address table, configured to translate logical addresses specified in the second part of the write request into physical addresses according to a second block size; and A processing apparatus configured to perform address translation using the first address table and the second address table, respectively, based on the first block size and the second block size.

2. The apparatus according to claim 1, further comprising: An image sensor configured to generate data to be written to the memory cell according to the second block size, wherein instructions executed by the processing device perform access according to the first block size; The instructions, when executed by the processing device, are configured to present a user interface to specify the second block size.

3. The apparatus of claim 2, wherein the user interface is configured to receive an indication of a representative file size recorded by the image sensor into the memory cell; and the processing apparatus is configured to determine the second block size based on the representative file size.

4. The apparatus of claim 2, wherein the first address table is configured for logical addresses associated with a first region of the memory cell; and the second address table is configured for logical addresses associated with a second region of the memory cell; The first partition identifies the first region; The second partition identifies the second region; and the logical address in the write request is specified by combining the identifiers of the first partition and the second partition; and Each of the first partition and the second partition is a namespace configured on the storage capacity of the memory cell.

5. The apparatus according to claim 1, further comprising: An image sensor configured to generate data to be written to the memory cell according to the second block size, wherein instructions executed by the processing device perform access according to the first block size; The instructions are further configured to instruct the processing device to determine the average size of the files recorded by the image sensor into the memory cells, calculate the second block size, and generate the second address table for logical addresses specified for partitions used to record data from the image sensor.

6. A digital camera, comprising: Image sensor; microprocessor; as well as Storage device, the storage device having: Memory cell; A host interface configured to receive from the microprocessor a write request to record image data into the memory cell; A first address table, configured to translate logical addresses into physical addresses based on a first block size; A second address table, configured to translate logical addresses into physical addresses based on a second block size; A controller configured to perform address translation using the second address table for requests associated with second data generated by the image sensor, and to perform address translation using the first address table for requests associated with first data.

7. The digital camera of claim 6, wherein the first data is identified by a logical address associated with a first partition; and the second data is identified by a logical address associated with a second partition created for recording data from the image sensor; and Each of the first partition and the second partition is a namespace allocated over the storage capacity of the memory cell of the storage device.

8. The digital camera according to claim 7, wherein the first data includes system files and application files.

9. The digital camera of claim 7, wherein the first data includes instructions that, when executed by the microprocessor, cause a user interface to be rendered to specify the second block size; and the digital camera further comprises: A network interface, wherein the user interface can be accessed through the network interface.

10. The digital camera of claim 7, wherein the first data includes instructions that, when executed by the microprocessor, cause the microprocessor to determine the average size of a data file generated by the image sensor and recorded in the memory cell, calculate the second block size, create the second partition, and generate the second address table for a logical address specified in the second partition for recording data generated by the image sensor.

11. A non-transitory computer storage device that stores instructions, which, when executed by a computing device, cause the computing device to perform a method, the method comprising: At the host interface of the storage device, a request is received to access a memory cell in the storage device to store or retrieve data, the request including a write request to store data generated by the image sensor; In response to a first request not associated with data generated by the image sensor, the logical address is converted to a physical address using a first address table according to a first block size; as well as In response to a second request associated with data generated by the image sensor, the logical address is converted to a physical address using a second address table according to the second block size.

12. The non-transitory computer storage device of claim 11, wherein the method further comprises: Presents options for specifying the size of the second block; Receive an indication of the file size of the data recorded by the image sensor; as well as The size of the second block is determined based on the file size.

13. The non-transitory computer storage device of claim 12, wherein the options are presented in the user interface via a communication connection via a network; and the method further comprises: Connect to a remote server to implement a monitoring application using the image sensor.

14. The non-transitory computer storage device of claim 12, wherein the method further comprises, in response to the determination of the file size: A second partition is created to host the data generated by the image sensor, wherein a logical address specified in a request to read or write the data generated by the image sensor is identified as being located within that partition; and A second address table is generated for the second partition, wherein the first partition in the storage device is configured to store system files and application files of the digital camera having the image sensor.

15. The non-transitory computer storage device of claim 11, wherein the method further comprises: Determine the average size of the data files generated by the image sensor and recorded in the memory cells; Calculate the size of the second block; Create a partition for recording the data generated by the image sensor; as well as Generate the second address table for the logical addresses specified in the partition.

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