Utilizing a suspend operation of a data transfer to a host system

Abstract

This disclosure relates to a suspend operation utilizing a data transfer to a host system. A host system can transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) that instructs the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a reduced power consumption). Herein, the memory system can transmit an image of the memory system stored in a volatile memory to the host system and transition to the second mode. Additionally, the host system can transmit a write command to the memory system operating in the second mode that includes the image and instructs the memory system to transition to the first mode. Herein, the memory system can write the image to the volatile memory and transition to the first mode.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 649,268, filed January 28, 2022, entitled “Suspend Operation with Data Transfer to Host System”, and U.S. Provisional Patent Application No. 63 / 238,008, filed August 27, 2021, entitled “Suspend Operation with Data Transfer to Host System”, each of which is assigned to the assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to a suspend operation utilizing data transmission to a host system. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, not-or (NOR), and not-and (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] A device is described. The device may include: a memory device including volatile memory cells; and a controller coupled to the memory device and configured to cause the device to: receive from a host system a read command associated with switching the device to a second operating mode associated with a second power consumption lower than the first power consumption when operating the device according to a first operating mode associated with a first power consumption; transmit an image of the device stored in the memory device, at least in part based on the receipt of the read command, to the host system based on the transmission of the image of the device according to the first operating mode; and operate the device according to the second operating mode in response to the receipt of the read command and at least in part based on the transmission of the image of the device.

[0007] Describe a device. The device may include: a memory device including volatile memory cells; and a controller coupled to the memory device and configured to cause the device to: receive from a host system a write command associated with switching the device to a second operating mode associated with a second power consumption greater than the first power consumption when operating the device according to a first operating mode associated with a first power consumption, the write command including an image of the device associated with operating the device according to the second operating mode; write the image of the device to the memory device at least in part based on receiving the write command; and operate the device according to the second operating mode in response to receiving the write command and at least in part based on writing the image of the device to the memory device.

[0008] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include: instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive from a host system a read command associated with switching the electronic device to a second operating mode associated with a second power consumption lower than the first power consumption, while operating the electronic device according to a first operating mode associated with a first power consumption; transmit, at least in part, an image of the electronic device stored in volatile memory based on the receipt of the read command, at least in part based on the transmission of the image of the electronic device operating according to the first operating mode, to the host system; and operate the electronic device according to the second operating mode in response to the receipt of the read command and at least in part based on the transmission of the image of the electronic device. Attached Figure Description

[0009] Figure 1 This document describes instances of systems that support suspend operations using data transfer to the host system, based on the examples disclosed herein.

[0010] Figure 2This document describes instances of systems that support suspend operations using data transfer to the host system, based on the examples disclosed herein.

[0011] Figure 3 This document describes an example of a process flow that supports suspending operations using data transfer to a host system, based on the examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system that supports suspend operations using data transfer to a host system, based on the examples disclosed herein.

[0013] Figure 5 and 6 The flowchart illustrates one or more methods for supporting suspend operations using data transfer to the host system, based on the examples disclosed herein. Detailed Implementation

[0014] The memory system can operate according to more than one operating mode. For example, the memory system can operate in a first operating mode associated with a first power consumption (e.g., nominal power consumption), and alternatively in a second operating mode associated with a second reduced power consumption. In some instances, the first operating mode may correspond to a standard operating mode, and the second operating mode may correspond to a lower power mode compared to the standard operating mode (e.g., suspend mode, sleep mode, hibernation mode). If operating in the first mode, the memory system can supply power to both volatile and non-volatile memory devices within the memory system. To reduce the power consumption of the memory system when operating in the second mode, the memory system can reduce the amount of power supplied to one or more volatile memory devices within the memory system (e.g., compared to the amount of power supplied to one or more volatile memory devices in the first operating mode), which may cause one or more volatile memory devices not to retain data.

[0015] To avoid data loss in one or more volatile memory devices when the memory system operates according to a second mode (e.g., a low-power mode), the memory system may write images stored in volatile memory (e.g., in at least one of the volatile memory devices) to one or more non-volatile memory devices before switching the memory system from a first mode to a second lower-power mode. Therefore, if the memory system switches back to the first operating mode (e.g., and the amount of power supplied to the volatile memory increases), the memory system can write images from the non-volatile memory back to the volatile memory, thus preventing data loss due to operating the memory system in the lower-power mode. However, in some cases, the process of writing images from the volatile memory to the non-volatile memory and writing data from the non-volatile memory back to the volatile memory devices can degrade the performance of the memory system. That is, storing images in the non-volatile memory can temporarily increase the power consumption on the memory system (e.g., due to the current consumed to hold the data in the volatile memory). Furthermore, performing access operations on volatile memory (e.g., writing an image to non-volatile memory, or reading an image from non-volatile memory) can reduce the reliability of non-volatile memory over time. Additionally, writing and reading images from non-volatile memory can introduce latency into the memory system.

[0016] In some cases, before operating the memory system in a second lower power mode, the memory system may additionally or alternatively transfer an image (or an indication of an image) to the host system (e.g., to avoid or reduce the size of the image written to non-volatile memory). For example, the host system may transfer a read command instructing the memory system to transfer an image of the memory system stored in volatile memory and instructing the memory system to operate in a lower power mode. In response to receiving the read command, the memory system may transfer an image of the memory system (or an indication of one or more aspects of the image of the memory system) to the host system and may switch from operating the memory system in a first mode to operating the memory system in a second lower power mode. If the memory system operates in the second lower power mode, then the host system may transfer a write command containing an image of the memory system stored in volatile memory and instructing the memory system to operate in a first mode (e.g., corresponding to nominal power consumption). In response to receiving the write command, the memory system may write the image to volatile memory and switch from operating the memory system in the second lower power mode to operating in the second nominal power mode. Therefore, the memory system can retain data stored in volatile memory while operating in a lower power mode without relying on writing images to and from volatile memory. In some cases, this reduces latency associated with the memory system, decreases power consumption at the memory system during transitions between the first and second operating modes, and improves the reliability of the non-volatile memory over time, among other advantages.

[0017] Original Reference Figures 1 to 3 The features of this disclosure are described in the context of system and process flows. These and other features of this disclosure are illustrated by reference to... Figures 4 to 6 The context of the device diagrams and flowcharts involving the suspension operation of data transmission to the host system is further explained and described.

[0018] Figure 1 This document describes an example of system 100 that supports suspend operations using data transfer to a host system, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0021] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The image shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). For example, memory device 130-a may be or include volatile memory (e.g., may include volatile memory cells), and memory device 130-b may be or include non-volatile memory (e.g., may include non-volatile memory cells). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include: volatile memory, such as static random access memory (SRAM); or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may include volatile memory to act as a cache for the memory system controller 115. For example, data read from or written to memory device 130 may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be alternatively performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions categorized herein as belonging to memory system controller 115. For example, such as Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 180, wherein each block 180 may include a set of corresponding pages 185, and each page 185 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, a three-level cell (TLC) when configured to store three bits of information, a four-level cell (QLC) when configured to store four bits of information, or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 180, and in some cases, parallel operations can be performed within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 180, as long as the different blocks 180 are in different planes 165. In some cases, individual blocks 180 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 180 within which parallel operations can occur. For example, parallel operations can be performed on blocks 180-a, 180-b, 180-c, and 180-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 180-a, 180-b, 180-c, and 180-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 180 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 180 within a virtual block may have the same block address within their respective planes 165 (e.g., block 180-a may be “block 0” of plane 165-a, block 180-b may be “block 0” of plane 165-b, etc.). In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 185 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 180 may contain memory cells organized in rows (page 185) and columns (e.g., strings, not shown). For example, memory cells in the same page 185 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 185 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 180 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 185 may not be updated until the entire block 180 containing page 185 has been erased.

[0036] System 100 may include any number of non-transitory computer-readable media that support suspend operations utilizing data transfers to a host system. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0037] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system 110, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system 110 is a managed NAND (MNAND) system.

[0038] The memory system 110 can operate according to more than one mode, each associated with a different level of power consumption. For example, the memory system 110 can operate in a first operating mode associated with a first power consumption (e.g., nominal power consumption) and alternatively in a second operating mode associated with a second reduced power consumption. Herein, the first operating mode may correspond to a standard operating mode, and the second operating mode may correspond to a lower power mode compared to the standard operating mode (e.g., suspend mode, sleep mode, hibernation mode). If operating in the first mode, the memory system 110 can supply power to both the volatile memory devices 130 (e.g., memory device 130-a, local memory 120) and the non-volatile memory devices 130 (e.g., memory device 130-b) within the memory system 110. To reduce the power consumption of the memory system 110 when operating in the second mode, the memory system 110 may reduce the amount of power supplied to the volatile memory devices 130 (e.g., memory device 130-a, local memory 120) within the memory system 110 (e.g., compared to the amount of power supplied to the volatile memory devices 130-a and local memory 120 in the first operating mode), which may cause the volatile memory devices 130-a and local memory 120 not to retain data.

[0039] To avoid losing data stored in volatile memory device 130-a when memory system 110 operates according to a second mode (e.g., low power mode), memory system 110 may write images of memory system 110 stored in volatile memory device 130-a (e.g., and in some cases, other volatile memory in memory system 110, such as local memory 120, in cases where local memory 120 contains volatile memory such as cache) to non-volatile memory device 130-b before switching memory system 110 from the first mode to the second low power mode. The image may contain data stored in volatile memory device 130-a (e.g., the state of NAND memory device 130-a), data associated with local controller 135-a of volatile memory device 130-a (e.g., the state of NAND local controller 135-a), data stored in other volatile memories of memory system 110 (e.g., data stored in SRAM or cache of local memory 120), data associated with firmware table of memory system 110, configuration details associated with memory system 110, or a combination thereof.

[0040] If the memory system 110 switches back to the first operating mode (e.g., and increases the amount of power supplied to the volatile memory device 130-a), then the memory system 110 can write images from the non-volatile memory device 130-b back to the volatile memory device 130-a, thus preventing data loss due to operating the memory system 110 in a lower power mode. In some cases, the process of writing images stored in the volatile memory device 130-a to the non-volatile memory device 130-b and writing data from the non-volatile memory device 130-b back to the volatile memory device 130-a can degrade the performance of the memory system 110. That is, storing images in the non-volatile memory device 130-b can temporarily increase the power consumption on the memory system 110 (e.g., due to the current consumed to hold the data in the volatile memory device 130-a). Furthermore, performing access operations on the volatile memory device 130-a (e.g., writing an image to the non-volatile memory device 130-b, or reading an image from the non-volatile memory device 130-b) can reduce the reliability of the non-volatile memory device 130-b over time. Additionally, writing and reading images from the non-volatile memory device 130-b can introduce latency into the memory system 110.

[0041] Alternatively, before operating the memory system 110 in a second or lower power mode, the memory system 110 may transfer the image to the host system 105 (e.g., to avoid or reduce the size of the image written to the non-volatile memory device 130-b, thereby reducing latency associated with switching between operating modes). In one case, the memory system 110 may transfer the image to the host system 105 and avoid writing the image to the non-volatile memory device 130-b. In some other cases, the memory system 110 may transfer the image to the host system 105, except for writing the image to the non-volatile memory device 130-b.

[0042] Memory system 110 may transfer images stored in volatile memory in response to a request received from host system 105 to switch memory system 110 to a lower power mode. For example, host system 105 may transfer a read command instructing memory system 110 to transfer images stored in volatile memory device 130-a and instructing memory system 110 to operate in a lower power mode. That is, host system 105 may transfer a start / stop unit (SSUM) read command with memory instructing memory system 110 to reduce the power consumption of memory system 110 (e.g., instructing memory system 110 to enter a power-down or sleep mode). In response to receiving a read command (e.g., an SSUM read command), memory system 110 may transfer images of memory system 110 to host system 105. The image of the memory system 110 stored in volatile memory may include data stored in volatile memory device 130-a (e.g., the state of NAND memory device 130-a), data associated with the local controller 135-a of volatile memory device 130-a (e.g., the state of NAND local controller 135-a), data stored in other volatile memories of the memory system 110 (e.g., data stored in SRAM or cache of local memory 120), data associated with the firmware table of the memory system 110, configuration details associated with the memory system 110, or a combination thereof.

[0043] Additionally, the memory system 110 may switch from operating in a first mode to operating in a second lower power mode in response to receiving a read command (e.g., an SSUM read command). For example, the memory system 110 may reduce the amount of power supplied to one or more volatile memory devices 130 (e.g., volatile memory device 130-a, one or more caches in the memory system 110, SRAM at the memory system).

[0044] If memory system 110 operates in a second lower power mode, then host system 105 may transmit a write command containing an image of memory system 110 stored in volatile memory device 130-a and instructing memory system 110 to operate in a first mode (e.g., corresponding to nominal power consumption). That is, host system 105 may transmit an SSUM write command instructing memory system 110 to increase power consumption (e.g., the amount of power supplied to volatile memory in memory system 110, an indication for memory system 110 to exit a lower power mode, such as sleep or hibernation). In response to receiving the write command, memory system 110 may write an image to volatile memory device 130-a and switch from operating in the second lower power mode to operating in the second nominal power mode. For example, in response to receiving a write command (e.g., an SSUM write command) from host system 105, memory system 110 may increase the amount of power supplied to volatile memory device 130-a and any other volatile memory device 130 or volatile memory (e.g., cache or SRAM) in memory system 110.

[0045] Therefore, the memory system 110 can operate in a lower power mode while retaining the data stored in the volatile memory device 130-a without relying on writing images to and from the volatile memory device 130-a. In some cases, this can reduce the latency associated with the memory system 110, reduce power consumption at the memory system 110 during transitions between the first and second operating modes, and improve the reliability of the non-volatile memory device 130-b over time.

[0046] In some cases, the memory system 110 may indicate to the host system 105 its ability to enter and exit lower power modes of operation in response to read and write commands (e.g., SSUM read and SSUM write commands). Herein, the host system 105 may transmit SSUM read and SSUM write commands in response to the memory system 110's indication of capability (e.g., relative to transmitting other commands to cause the memory system 110 to switch between operating modes not associated with the transfer of images between the memory system 110 and the host system 105).

[0047] In one example, memory system 110 may indicate its capabilities via register 170 at memory system 110. Herein, memory system 110 may set register 170 (e.g., SSUM_Capability register 170) associated with such capability information to a value indicating that memory system 110 can enter and exit lower power modes in response to read and write commands, and host system 105 may identify the capabilities of memory system 110 by polling or reading register 170. In another example, memory system 110 may indicate its capabilities via flag 175. Herein, memory system 110 may set flag 175 to indicate its ability to perform SSUM read and write commands, and host system 105 may poll memory system 110 (e.g., the memory system 110's storage location, memory system 110's register 170), the memory system 110 may include the flag to determine its capabilities. In another instance, the memory system 110 may indicate its capability by transmitting signaling to the host system 105 that indicates its ability to enter and exit a lower power mode in response to read and write commands (e.g., SSUM read and SSUM write commands).

[0048] Memory system 110 may indicate to host system 105 a threshold size for images of memory system 110 transferred between host system 105 and memory system 110 during the execution of read and write commands (e.g., SSUM read and write commands). For example, memory system 110 may indicate a maximum size of an image transferred to host system 105 in response to a read command. The threshold size indicated by memory system 110 may be an integer multiple (e.g., 4 kilobytes) of the data size (e.g., which may have granularity) of the data exchanged between host system 105 and memory system 110. In some cases, host system 105 may indicate the size of the image in a read command (e.g., in an SSUM read command). If memory system 110 indicates a threshold size for an image to host system 105, then the indicated size of the image in the read command may be less than or equal to the threshold size indicated by memory system 110.

[0049] In one example, the memory system 110 may indicate the threshold size via register 170 at the memory system 110. Herein, the memory system 110 may set register 170, associated with this threshold size information, to a value indicating the threshold size, and the host system 105 may identify the threshold size by polling or reading register 170. In another example, the memory system 110 may indicate the threshold size by transmitting signaling indicating the threshold size to the host system 105.

[0050] Figure 2 This document describes an example of system 200 that supports suspend operations using data transfer to the host system, based on the examples disclosed herein. System 200 may be used as a reference. Figure 1 The described system 100 is an example or aspect thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may be implemented with reference to Figure 1 The various aspects of the system 100 described. For example, the memory system 210 and the host system 205 may be instances of the memory system 110 and the host system 105, respectively.

[0051] Memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205, as described herein. Memory device 240 may include references Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0052] Memory system 210 may include memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. Memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, such as different memory controllers 230 for each type of memory device 240. In some cases, memory controller 230 may implement a reference... Figure 1 The local controller 135 is described in various aspects.

[0053] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data for transferring data between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to convert data between the host system 205 and the memory device 240, for example as shown by the data path 250, and may be collectively referred to as the data path components.

[0054] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, buffered data can be stored or transmitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0055] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 can be a non-cached buffer. That is, host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without performing an operation to match the address with an address already existing in buffer 225 (e.g., no cached address matching or lookup operation).

[0056] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0057] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 269) can be used to control the processing of access commands and the movement of corresponding data. For example, this can be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 269 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) can be located anywhere within the memory system 210.

[0058] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0059] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, interface 220 can add each command to command queue 260 to transmit the command to memory system controller 215.

[0060] The memory system controller 215 may determine whether an access command has been received based on or in response to communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After the command has been retrieved from the command queue 260, for example by the memory system controller 215, the command may be removed from the command queue 260. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example via the bus 235.

[0061] Once it is determined that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0062] In either case, the memory system controller 215 may use the buffer 225 to temporarily store data received from or sent to the host system 205, and for other purposes. The buffer 225 can be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0063] To process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0064] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205, and at least some portions of the access commands can be processed in parallel.

[0065] If buffer 225 has sufficient space to store the write data, then memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location within buffer 225 for storing data from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0066] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0067] In some cases, memory queue 269 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 269 for processing. Memory queue 269 may contain an entry for each access command. In some instances, memory queue 269 may additionally contain: a buffer pointer (e.g., an address) indicating where the data associated with the command is stored in buffer 225; and a memory pointer (e.g., an address) indicating the location of the data associated with the data in memory device 240. In some cases, memory controller 230 can obtain the location of data to be retrieved from buffer 225 from buffer 225, buffer queue 265, or memory queue 269. Memory controller 230 can manage the location of stored data in memory device 240 (e.g., perform wear leveling, garbage collection, etc.). Entries can be added to memory queue 269, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 269, for example, via the storage controller 230 or the memory system controller 215.

[0068] To process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0069] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, then memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, whether the data transfer to buffer 225 has been completed.

[0070] In some cases, the storage queue 269 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 269 for processing. In some cases, the storage controller 230 can obtain the location within the memory device 240 from which data is retrieved from, either from the buffer 225 or the storage queue 269. In some cases, the storage controller 230 can obtain the location within the buffer 225 used to store data from the buffer queue 265. In some cases, the storage controller 230 can obtain the location within the buffer 225 used to store data from the storage queue 269. In some cases, the memory system controller 215 can move a command processed by the storage queue 269 back to the command queue 260.

[0071] Once data has been stored in buffer 225 by storage controller 230, it can be transferred from buffer 225 to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 is complete.

[0072] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. When the data is moved into and stored in buffer 225, the command may remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), then the command may be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, then the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0073] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or instead of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0074] The memory system 210 can operate according to more than one mode, each associated with a different level of power consumption. For example, the memory system 210 can operate in a first operating mode associated with a first power consumption (e.g., nominal power consumption) and alternatively in a second operating mode associated with a second reduced power consumption. Herein, the first operating mode may correspond to a standard operating mode, and the second operating mode may correspond to a lower power mode compared to the standard operating mode (e.g., suspend mode, sleep mode, hibernation mode). If operating in the first mode, the memory system 210 can supply power to both the volatile memory device 240 and the non-volatile memory device 240 within the memory system 210. To reduce the power consumption of the memory system 210 when operating in the second mode, the memory system 210 can reduce the amount of power supplied to the volatile memory device within the memory system 210 (e.g., compared to the amount of power supplied to the volatile memory device 240 in the first operating mode), which may cause the volatile memory device 240 to not retain data.

[0075] To avoid losing data stored in the volatile memory device 240 when the memory system 210 operates according to a second mode (e.g., a low-power mode), the memory system 210 may write an image of the memory system 210 stored in the volatile memory device 240 (and in some cases, other volatile memories in the memory system 210 (e.g., buffer queue 265, buffer 225, command queue 260, storage queue 269)) to the non-volatile memory device 240 before switching the memory system 210 from the first mode to the second low-power mode. The image may include data stored in the volatile memory device 240 (e.g., the state of the NAND memory device 240), data associated with the local controller of the volatile memory device 240 (e.g., the state of the NAND local controller associated with the volatile memory device 240), data stored in other volatile memories of the memory system 210 (e.g., data stored in SRAM or cache), data associated with the firmware table of the memory system 210, configuration details associated with the memory system 210, or a combination thereof.

[0076] If memory system 210 switches back to the first operating mode (e.g., and increases the amount of power supplied to volatile memory device 240), then memory system 210 can write images from non-volatile memory device 240 back to volatile memory device 240, thus preventing data loss due to operating memory system 210 in a lower power mode. In some cases, the process of writing images stored in volatile memory device 240 to non-volatile memory device 240 and writing data from non-volatile memory device 240 back to volatile memory device 240 can degrade the performance of memory system 210. That is, storing images in non-volatile memory device 240 can temporarily increase power consumption on memory system 210 (e.g., due to current consumption to hold data in volatile memory device 240). Furthermore, performing access operations on the volatile memory device 240 (e.g., writing an image to the non-volatile memory device 240, or reading an image from the non-volatile memory device 240) can reduce the reliability of the non-volatile memory device 240 over time. Additionally, writing and reading images from the non-volatile memory device 240 can introduce latency into the memory system 210.

[0077] Alternatively, before operating the memory system 210 in a second or lower power mode, the memory system 210 may transfer the image to the host system 205 (e.g., to avoid or reduce the size of the image written to the non-volatile memory device 240, thereby reducing latency associated with switching between operating modes). In one case, the memory system 210 may transfer the image to the host system 205 and avoid writing the image to the volatile memory device 240. In some other cases, the memory system 210 may transfer the image to the host system 205, except for writing the image to the volatile memory device 240.

[0078] Memory system 210 may transfer images stored in volatile memory in response to a request received from host system 205 via interface 220 to switch memory system 210 to a lower power mode. For example, host system 205 may transmit a read command instructing memory system 210 to transfer images stored in volatile memory device 240 and instructing memory system 210 to operate in a lower power mode. That is, host system 205 may transmit a start / stop unit (SSUM) read command with memory instructing memory system 210 to reduce the power consumption of memory system 210 (e.g., instructing memory system 210 to enter a power-down or sleep mode). In response to receiving a read command (e.g., an SSUM read command) via interface 220, memory system 210 may transfer images of memory system 210 to host system 205 via interface 220. The image of memory system 210 stored in volatile memory may include data stored in volatile memory device 240 (e.g., the state of NAND memory device 240), data associated with the local controller of volatile memory device 240 (e.g., the state of the NAND local controller of volatile memory device 240), data stored in other volatile memories of memory system 210 (e.g., data stored in volatile memories at memory system controller 215, data in buffer queue 265, data in storage queue 269, data in command queue 260), data associated with firmware table of memory system 210, configuration details associated with memory system 210, or a combination thereof.

[0079] Additionally, memory system 210 may switch from operating in a first mode to operating in a second lower power mode in response to receiving a read command (e.g., an SSUM read command). For example, memory system 210 may reduce the amount of power supplied to one or more volatile memory devices 240 (e.g., volatile memory devices 240, one or more caches in memory system 210, SRAM at memory system).

[0080] If memory system 210 operates in a second lower power mode, then host system 205 can transmit a write command containing an image of memory system 210 stored in volatile memory device 240 and instructing memory system 210 to operate in a first mode (e.g., corresponding to nominal power consumption). That is, host system 205 can transmit an SSUM write command instructing memory system 210 to increase power consumption (e.g., the amount of power supplied to volatile memory in memory system 210, an indication for memory system 210 to exit a lower power mode, such as sleep or hibernation). In response to receiving the write command via interface 220, memory system 210 can write an image to volatile memory device 240 and switch from operating in the second lower power mode to operating in the second nominal power mode. For example, in response to receiving a write command (e.g., an SSUM write command) from the host system 205 via interface 220, memory system 210 may increase the amount of power supplied to volatile memory device 240 and any other volatile memory device 240 or volatile memory (e.g., cache or SRAM) in memory system 210.

[0081] Therefore, memory system 210 can retain data stored in volatile memory device 240 while operating in a lower power mode without relying on writing images to and from volatile memory device 240. In some cases, this can reduce latency associated with memory system 210, reduce power consumption at memory system 210 during transitions between the first and second operating modes, and improve the reliability of non-volatile memory device 240 over time.

[0082] In some cases, the memory system 210 may indicate to the host system 205 its ability to enter and exit a lower power mode of operation in response to read and write commands (e.g., SSUM read and SSUM write commands). Herein, the host system 205 may transmit SSUM read and SSUM write commands in response to the memory system 210's indication of capability (e.g., relative to transmitting other commands to cause the memory system 210 to switch between operating modes not associated with the transfer of images between the memory system 210 and the host system 205).

[0083] In one example, memory system 210 may indicate its capabilities via register 270 at memory system 210. Herein, memory system 210 may set register 270 (e.g., SSUM_Capability register 270) associated with such capability information to a value indicating that memory system 210 can enter and exit lower power modes in response to read and write commands, and host system 205 may identify the capabilities of memory system 210 by polling or reading register 270. In another example, memory system 210 may indicate its capabilities via flag 275. Herein, memory system 210 may set flag 275 to indicate its ability to perform SSUM read and write commands, and host system 205 may poll memory system 210 (e.g., the memory system 210's storage location, memory system 210's register 270), the memory system 210 may include the flag to determine its capabilities. In another instance, the memory system 210 may indicate its capability by transmitting signaling via interface 220 to host system 205 that indicates the memory system 210’s ability to enter and exit a lower power mode in response to read and write commands (e.g., SSUM read and SSUM write commands).

[0084] Memory system 210 may indicate to host system 205 a threshold size for images of memory system 210 transferred between host system 205 and memory system 210 during the execution of read and write commands (e.g., SSUM read and write commands). For example, memory system 210 may indicate a maximum size of an image transferred to host system 205 in response to a read command. The threshold size indicated by memory system 210 may be an integer multiple (e.g., 4 kilobytes) of the data size (e.g., which may have granularity) of the data exchanged between host system 205 and memory system 210. In some cases, host system 205 may indicate the size of the image in a read command (e.g., in an SSUM read command). If memory system 210 indicates a threshold size for an image to host system 205, then the indicated size of the image in the read command may be less than or equal to the threshold size indicated by memory system 210.

[0085] In one example, the memory system 210 may indicate the threshold size via register 270 at the memory system 210. Herein, the memory system 210 may set register 270, associated with this threshold size information, to a value indicating the threshold size, and the host system 205 may identify the threshold size by polling or reading register 270. In another example, the memory system 210 may indicate the threshold size by transmitting signaling indicating the threshold size to the host system 205 via interface 220.

[0086] Figure 3 This document describes an example of process flow 300 that supports a suspend operation using data transfer to a host system, based on the examples disclosed herein. In some instances, the process flow may implement various aspects of systems 100 and 200. For example, process flow 300 may include host system 305 and memory system 310, which may be referenced... Figure 1 and 2 Examples of host systems and memory systems described. Process flow 300 can illustrate an example of a memory system switching between operating in a first operating mode associated with nominal power consumption and operating in a second, lower power mode associated with reduced power consumption. Alternative examples of the following may be implemented, where some steps are performed in a different order than described or not at all. In some cases, steps may include additional features not mentioned below, or other steps may be added.

[0087] Various aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system controller). For example, when executed by a controller (e.g., memory system controller 115 or 215), the instructions may cause the controller to perform the operation of process flow 300.

[0088] At 315, the memory system 310 may operate according to a first mode associated with a first power consumption (e.g., nominal power consumption). That is, the memory system 310 may be powered to operate both the volatile and non-volatile memory devices of the memory system 310.

[0089] At 320, capability information may optionally be indicated to the host system 305. That is, the memory system 310 may indicate to the host system 305 its ability to execute read and write commands (e.g., SSUM read and write commands) associated with entering and exiting lower power modes of operation. For example, the memory system 310 may indicate to the host system 305 its ability to execute read commands (e.g., SSUM read commands) associated with switching the memory system 310 to a lower power mode of operation.

[0090] In one example, the memory system 310 may indicate its capabilities via registers (e.g., the SSUM_Capability register) at the memory system 310. For instance, the memory system 310 may set the register to a value indicating that it is capable of entering and exiting a lower power mode in response to read and write commands received from the host system 305. Alternatively, the host system 305 may identify the capabilities of the memory system 310 by polling or reading the register. In another example, the memory system 310 may indicate its capabilities via flags. Hereinafter, the memory system 310 may set flags to indicate its capability to perform SSUM read and write commands, and the host system 305 may poll the memory system 310 (e.g., its storage location, its registers) to determine its capabilities. In another instance, the memory system 310 may indicate its capability by transmitting signaling to the host system 305 that indicates its ability to enter and exit a lower power mode in response to read and write commands (e.g., SSUM read and SSUM write commands).

[0091] At 325, an image size threshold may optionally be indicated to the host system 305. For example, the memory system 310 may indicate a threshold size for the image of the memory system 310 to the host system 305. That is, the memory system 310 may support the transfer of an image of the memory system 310 stored in volatile memory at the memory system 310 to the host system 305 in response to receiving a read command when the memory system 310 is operating according to a first operating mode. The image of the memory system 310 stored in volatile memory may include data stored in the volatile memory of the memory system 310, data associated with a local controller associated with the volatile memory (e.g., the state of the NAND local controller), data stored in other volatile memories of the memory system 310 (e.g., data stored in SRAM or a cache such as an L2P cache), data associated with the firmware table of the memory system 310, configuration details associated with the memory system 310, or a combination thereof.

[0092] Therefore, at 325, the memory system 310 may optionally indicate a threshold size of the image to the host system 305, wherein the memory system 310 may be configured to transmit an image smaller than or equal to the threshold size. The threshold size indicated by the memory system 310 may be an integer multiple (e.g., 4 kilobytes) of the data size (e.g., which may have granularity) of the data exchanged between the host system 305 and the memory system 310.

[0093] In one instance, the memory system 310 may indicate the threshold size via a register at the memory system 310. In this document, the memory system 310 may set a register associated with this threshold size information to a value indicating the threshold size, and the host system 305 may identify the threshold size by polling or reading the register. In another instance, the memory system 310 may indicate the threshold size by transmitting signaling indicating the threshold size to the host system 305.

[0094] At 330, a read command may be transmitted by the host system 305 and received by the memory system 310. For example, the host system 305 may transmit a read command instructing the memory system 310 to transfer an image stored in the volatile memory device 130-a and instructing the memory system 310 to switch to a second lower power mode of operation. In some cases, the read command may be an SSUM read command, which instructs the memory system 310 to reduce its power consumption (e.g., by switching the memory system 310 to a power-down mode, a hibernation mode, a suspend mode, or a sleep mode). The read command may include an indication of the size of the image to be transferred to the host system 305 in response to the read command. For example, the read command may indicate the number of pages associated with the image to be transferred by the memory system 310 in response to the read command (e.g., each having a size associated with the interface between the memory system 310 and the host system 305).

[0095] In response to receiving a read command, the firmware at memory system 310 may facilitate the reading of one or more portions of volatile memory in memory system 310 to identify a dataset. Additionally, if memory system 310 operates according to a first mode, the firmware may locate (e.g., package) and align data to generate an image associated with memory system 310 stored in volatile memory.

[0096] In some cases, in response to receiving a read command from the host system 305, the memory system 310 may generate error control information. For example, the memory system 310 may generate error control information corresponding to an image (e.g., an image checksum, error correction information associated with the image). In this case, the firmware at the memory system 310 may additionally append error control information to the image based on the generated error control information.

[0097] At 335, the image stored in the volatile memory of the memory system 310 may optionally be stored in the non-volatile memory of the memory system 310. That is, the memory system 310 may write the image to the non-volatile memory in response to receiving a read command at 330. In some cases, writing the image of the memory system 310 to the non-volatile memory may further increase the reliability of the memory system 310 if switching to a lower power mode. That is, the memory system 310 may retain the image even if the host system 305 fails to retain the image (e.g., due to power loss).

[0098] At 340, mapping information associated with the image may be stored at memory system 310. The mapping information indicates where data in the image will be stored in the volatile memory of memory system 310 (e.g., after switching back from a second lower power mode). Memory system 310 may store the mapping information in non-volatile memory (e.g., ROM) that retains the mapping information while memory system 310 operates in the second lower power mode. Alternatively, memory system 310 may store the mapping information in volatile memory (e.g., SRAM) that receives the amount of power necessary to retain the mapping information during operation in the second low power mode. For example, memory system 310 may optionally store information indicating the positioning (e.g., packaging) or alignment of the image in the volatile memory of memory system 310. In the event that memory system 310 generates error control information associated with the image at 330, memory system 310 may additionally store the error control information at memory system 310 at 340. For example, memory system 310 may store error control information in non-volatile or volatile memory that receives the amount of power necessary to retain the mapping information during operation of memory system 310 in a second low-power mode.

[0099] At 345, the memory system 310 can transfer an image stored in volatile memory to the host system 305. That is, a read command received by the memory system 310 at 330 can instruct the memory system 310 to transfer the image to the host system 305. Therefore, in response to receiving a read command at 330, the memory system 310 can transfer an image stored in volatile memory to the host system 305. In some cases, the size of the image transferred to the host system 305 at 345 may be less than or equal to a threshold size associated with the image indicated by the memory system at 325. Additionally, the image may have a granularity (e.g., four kilobytes) associated with the data transferred between the host system 305 and the memory system 310.

[0100] In some cases, the memory system 310 may additionally transmit mapping information to the host system 305 at location 345. For example, if the memory system 310 does not store mapping information at location 340, it may transmit the mapping information to the host system 305. In some cases, the memory system 310 may transmit mapping information from the header associated with the image to the host system 305 at location 345. Additionally, the memory system may transmit error control information corresponding to the image to the host system 305 at location 345.

[0101] In response to receiving an image (and optionally, mapping information) from the memory system 310, the host system 305 may store the image, and in some cases, store the mapping information, error control information, or both (e.g., in DRAM at the host system 305).

[0102] At 350, the memory system 310 can be operated according to a second mode. That is, the memory system 310 can switch from operating according to a first mode to operating according to a second mode. In some cases, the memory system 310 can reduce the amount of power supplied to one or more portions of the volatile memory when operating according to a second lower power mode (e.g., compared to the amount of power supplied to one or more portions of the volatile memory when operating according to the first mode).

[0103] In some cases, the memory system 310 may be able to operate according to more than one lower power mode. For example, the memory system 310 may be configured to operate according to one lower power mode, wherein in this lower power mode, the memory system 310 does not supply power to the volatile memory. Alternatively, the memory system 310 may be configured to operate according to another lower power mode, wherein in this lower power mode, the memory system 310 supplies power to the volatile memory, but the power is less than the amount supplied in the first mode. When the memory system 310 is capable of operating according to more than one lower power mode, the host system 305 may indicate a specific lower power mode within a read command at 330. Hereinafter, the memory system 310 may operate according to the lower power mode indicated within the read command.

[0104] At point 355, a write command may be received by memory system 310. That is, memory system 310 may receive a write command from host system 305 while operating in a second lower power mode. The write command is associated with switching memory system 310 to operate in a first operating mode (e.g., it could be an SSUM write command). For example, the write command may instruct memory system 310 to switch from the second operating mode to the first mode and may additionally include an image (e.g., transmitted from memory system 310 to host system 305 at point 345). Additionally, the write command may additionally include mapping information if memory system 310 transmits mapping information associated with the image to host system 305 at point 345.

[0105] Additionally, when the memory system 310 transmits error control information corresponding to the image to the host system 305 at 345, the write command may further include error control information. In these cases, the memory system 310 may perform error control operations on the image of the memory system 310 included in the write command. For example, the error control information may include a checksum associated with the image of the memory system 310. Herein, the memory system 310 may perform error control operations by comparing the image with the checksum included in the write command to identify (e.g., verify) the integrity of the image included in the write command. Alternatively or additionally, the memory system 310 may perform error control operations by detecting and, in some cases, correcting one or more errors in the image of the memory system 310 included in the write operation.

[0106] At 360, an image from memory system 310 can be written to volatile memory within memory system 310. That is, in response to receiving a write command, memory system 310 can write the image to volatile memory based on mapping information (e.g., received within the write command, read from non-volatile memory in memory system 310). For example, firmware associated with memory system 310 can receive the image and facilitate the writing of data within the image based on or in response to mapping information associated with the image. Therefore, memory system 310 can restore the volatile memory within memory system 310 to a state associated with operating memory system 310 according to a first operating mode. For example, memory system 310 can restore a cache (e.g., L2P cache) associated with memory system 310 based on or in response to data within the image. Additionally, memory system 310 can write data to other volatile memory devices, controllers associated with volatile memory devices, firmware associated with memory system 310, or combinations thereof.

[0107] At 365, the memory system 310 can be operated according to a first mode. For example, in response to receiving a write command from the host system 305 at 355, the memory system 310 can switch from operating according to a second lower power mode to operating according to the first mode. In this document, the memory system 310 can supply more power to the volatile memory in the memory system 310 compared to the amount of power supplied when operating the memory system 310 according to the second lower power mode.

[0108] Figure 4 A block diagram 400 illustrates a memory system 420 that supports suspend operations using data transfer to a host system, based on the examples disclosed herein. The memory system 420 may be a reference... Figures 1 to 3 Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of components for performing various aspects of the suspend operation as described herein, utilizing data transfer to a host system. For example, memory system 420 may include a read command receiver 425, an image transmitter 430, a mode operation manager 435, a write command receiver 440, an image write manager 445, a capability indicator 450, an image size indicator 455, an image mapping manager 460, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0109] The read command receiver 425 may be configured or otherwise support components for receiving, from the host system, a read command associated with switching the memory system to a second operating mode associated with a second power consumption lower than the first power consumption when operating the memory system according to a first operating mode associated with a first power consumption. The image transmitter 430 may be configured or otherwise support components for transmitting, at least in part, an image of the memory system stored in volatile memory based on the memory system operating according to the first operating mode, to the host system based on receiving the read command. The mode operation manager 435 may be configured or otherwise support components for operating the memory system according to a second operating mode in response to receiving the read command and at least in part based on transmitting the image of the memory system.

[0110] In some instances, the capability indicator 450 may be configured or otherwise support components for: instructing the host system on the capability of the memory system to execute read commands associated with converting the memory system to operation according to a second operating mode, wherein receiving read commands is at least in part based on the indication.

[0111] In some instances, to support the indication of the memory system's capabilities, the capability indicator 450 may be configured or otherwise supported to store, at a register, a value indicating the memory system's ability to execute read commands associated with converting the memory system to operation according to a second operating mode.

[0112] In some instances, to support the capability of indicating the memory system, the capability indicator 450 may be configured or otherwise support the transmission of signaling to the host system indicating the capability of the memory system to execute read commands associated with converting the memory system to operation according to a second operating mode.

[0113] In some instances, the image size indicator 455 may be configured or otherwise supported for indicating to the host system a threshold size of an image transferred to the host system in response to one or more read commands associated with converting the memory system to operation according to a second operating mode, wherein receiving the read command is at least in part based on the indicated threshold size.

[0114] In some instances, to support a threshold size for an image indicative of the memory system, the image size indicator 455 may be configured or otherwise support a component for storing a value indicating the threshold size of the image at a register, wherein the indication is at least in part based on storing the value at the register.

[0115] In some instances, to support the indication of a threshold size of an image to the memory system, the image size indicator 455 may be configured or otherwise support the transmission of signaling indicating the threshold size of an image to the host system.

[0116] In some instances, the read command includes a field indicating the threshold size of the image to be transferred to the host system's memory system in response to the read command.

[0117] In some instances, the write command receiver 440 may be configured or otherwise support components for receiving, when operating the memory system according to a second operating mode, a write command associated with switching the memory system to operation according to a first operating mode, the write command containing an image of the memory system. In some instances, the image write manager 445 may be configured or otherwise support components for writing an image of the memory system to volatile memory, at least in part based on receiving a write command. In some instances, the mode operation manager 435 may be configured or otherwise support components for operating the memory system according to a first operating mode in response to receiving a write command and at least in part based on writing an image of the memory system to volatile memory.

[0118] In some instances, the read command receiver 425 may be configured or otherwise support components for generating error control information corresponding to an image of the memory system, at least in part based on receiving a read command. In this document, transferring an image of the memory system to a host system may further include transferring error control information to the host system. In some instances, the image write manager 445 may be configured or otherwise support components for performing error control operations on an image of the memory system using error control information, at least in part based on receiving a write command that further includes error control information, wherein writing an image of the memory system to volatile memory is at least in part based on performing error control operations.

[0119] In some instances, the image mapping manager 460 may be configured or otherwise support components for storing data indicating the mapping between an image of the memory system and volatile memory in non-volatile memory, at least in part based on receiving a read command, so that the memory system can write the image of the memory system to volatile memory after operating the memory system according to a second operating mode.

[0120] In some instances, the image mapping manager 460 may be configured or otherwise support the transmission of signaling associated with the image in the memory system, indicating the mapping between the image in the memory system and the volatile memory, to the host system, at least in part based on receiving a read command.

[0121] In some instances, the mode operation manager 435 may be configured or otherwise support components for storing an image of the memory system in non-volatile memory, at least in part based on receiving a read command, wherein the memory system is operated according to a second operation mode at least in part based on said storage.

[0122] In some instances, an image may contain data stored in volatile memory based on or in response to a read command received by the memory system, data associated with a controller of the volatile memory based on or in response to a read command received by the memory system, data stored in the logical-physical mapping table of the memory system based on or in response to a read command received by the memory system, data associated with the configuration of the volatile memory based on or in response to a read command received by the memory system, or any combination thereof.

[0123] Write command receiver 440 may be configured or otherwise support components for: receiving from a host system a write command associated with switching the memory system to a second operating mode associated with a second power consumption greater than the first power consumption when operating the memory system according to a first operating mode associated with a first power consumption, the write command containing an image of the memory system associated with operating the memory system according to the second operating mode. Image write manager 445 may be configured or otherwise support components for: writing an image of the memory system to volatile memory in the memory system at least in part based on receiving a write command. In some instances, mode operation manager 435 may be configured or otherwise support components for: operating the memory system according to a second operating mode in response to receiving a write command and at least in part based on writing an image of the memory system to volatile memory.

[0124] In some instances, the image mapping manager 460 may be configured or otherwise support components for reading data indicating a mapping between an image in the memory system and volatile memory from non-volatile memory in the memory system, wherein an image written to the memory system is at least partially based on the read.

[0125] In some instances, the image mapping manager 460 may be configured or otherwise support components for receiving, from the host system, signaling associated with the image in the memory system that indicates a mapping between the image in the memory system and volatile memory.

[0126] In some instances, the image includes data stored in volatile memory for operating the memory system according to the second operating mode, data associated with a controller of the volatile memory for operating the memory system according to the second operating mode, data stored in the logical-physical mapping table of the memory system for operating the memory system according to the second operating mode, data associated with the configuration of the volatile memory for operating the memory system according to the second operating mode, or any combination thereof.

[0127] In some instances, the read command receiver 425 may be configured or otherwise support components for receiving read commands from the host system associated with switching the memory system to operation according to a first operating mode when operating the memory system according to a second operating mode. In some instances, the image transmitter 430 may be configured or otherwise support components for transmitting images of the memory system to the host system, at least in part based on receiving a read command. In some instances, the mode operation manager 435 may be configured or otherwise support components for operating the memory system according to a first operating mode in response to receiving a read command and at least in part based on transmitting images of the memory system, wherein receiving write commands is at least in part based on operating the memory system according to the first operating mode.

[0128] Figure 5 The flowchart illustrates a method 500 that supports a suspend operation using data transfer to a host system, based on the examples disclosed herein. The operation of method 500 can be implemented by a memory system or its components as described herein. For example, the operation of method 500 can be implemented by a reference... Figures 1 to 4 The described memory system performs the functions. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0129] At 505, the method may include: when operating the memory system according to a first operating mode associated with a first power consumption, receiving from a host system a read command associated with switching the memory system to operation according to a second operating mode associated with a second power consumption lower than the first power consumption. The operation of 505 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 505 may be derived from references... Figure 4 The described read command is executed by receiver 425.

[0130] At 510, the method may include: transferring an image of a memory system stored in volatile memory, at least partially based on a memory system operating according to a first operating mode, to a host system, at least in part based on receiving a read command. The operation of 510 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 510 may be derived from references... Figure 4 The image transmitter 430 described is executed.

[0131] At 515, the method may include: operating the memory system according to a second operating mode in response to receiving a read command and based at least in part on an image of the transfer memory system. The operation at 515 may be performed according to the examples disclosed herein. In some examples, aspects of the operation at 515 may be derived from references... Figure 4 The described mode operation manager 435 is executed.

[0132] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving from a host system a read command associated with switching the memory system to operation according to a second operating mode associated with a second power consumption lower than the first power consumption when operating the memory system according to a first operating mode associated with a first power consumption; transferring an image of the memory system stored in volatile memory, at least partially based on the receipt of the read command, to the host system based on the receipt of the read command; and operating the memory system according to the second operating mode in response to the receipt of the read command and at least partially based on the transfer of the image of the memory system.

[0133] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for instructing a host system to enable a memory system to execute a read command associated with converting the memory system to operation according to a second operating mode, wherein receiving the read command may be based at least in part on the instruction.

[0134] In some instances of the method 500 and apparatus described herein, the capability of an indication of a memory system may include operations, features, circuitry, logic, components, or instructions for storing values ​​at a register indicating the capability of the memory system to execute read commands associated with converting the memory system into operation according to a second operating mode.

[0135] In some instances of the method 500 and apparatus described herein, the capability of indicative memory system may include operations, features, circuitry, logic, components, or instructions for transmitting signaling to a host system indicative of the memory system's ability to execute read commands associated with converting the memory system into operation according to a second operating mode.

[0136] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: instructing a host system to indicate a threshold size of an image of the memory system transmitted to the host system in response to one or more read commands associated with converting the memory system to operation according to a second operating mode, wherein receiving the read command may be based at least in part on the indicated threshold size.

[0137] In some instances of the method 500 and apparatus described herein, the threshold size of an image indicating a memory system may include operations, features, circuitry, logic, components, or instructions for storing a value indicating the threshold size of the image at a register, wherein the indication may be based at least in part on storing the value at the register.

[0138] In some instances of the method 500 and apparatus described herein, the threshold size of an image indicating the memory system may include operations, features, circuitry, logic, components, or instructions for transmitting signaling indicating the threshold size of the image to the host system.

[0139] In some instances of the method 500 and device described herein, the read command includes a field indicating a threshold size of the image to be transferred to the host system's memory system in response to the read command.

[0140] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for: receiving from a host system a write command associated with switching the memory system to operation according to a first operating mode when operating the memory system according to a second operating mode, the write command containing an image of the memory system; writing the image of the memory system to volatile memory at least in part based on receiving the write command; and operating the memory system according to the first operating mode in response to receiving the write command and at least in part based on writing the image of the memory system to volatile memory.

[0141] Some instances of the method 500 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for: generating error control information corresponding to an image of the device based at least in part on receiving a read command, wherein transmitting the image of the device to a host system further includes transmitting the error control information to the host system; and performing an error control operation on the image of the device using the error control information based at least in part on receiving a write command that further includes the error control information, wherein writing the image of the device to a memory device is based at least in part on performing the error control operation.

[0142] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for storing data indicating a mapping between an image of a memory system and volatile memory in non-volatile memory, at least in part based on receiving a read command, such that the memory system can write an image of the memory system to volatile memory after operating the memory system according to a second operating mode.

[0143] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting, at least in part, signaling associated with the image of the memory system, indicating a mapping between the image of the memory system and volatile memory, to the host system based on receiving a read command.

[0144] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for storing an image of a memory system in non-volatile memory, at least in part based on receiving a read command, wherein operating the memory system according to a second operating mode may be at least in part based on said storage.

[0145] In some instances of the method 500 and apparatus described herein, the image includes data stored in volatile memory based on or in response to a read command received by the memory system, data associated with a controller of the volatile memory based on or in response to a read command received by the memory system, data stored in a logical-physical mapping table of the memory system based on or in response to a read command received by the memory system, data associated with a configuration of the volatile memory based on or in response to a read command received by the memory system, or any combination thereof.

[0146] Figure 6 The flowchart illustrates a method 600 that supports a suspend operation using data transfer to a host system, based on the examples disclosed herein. The operation of method 600 can be implemented by a memory system or its components as described herein. For example, the operation of method 600 can be implemented by a reference... Figures 1 to 4The described memory system performs the functions. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0147] At 605, the method may include: when operating the memory system according to a first operating mode associated with a first power consumption, receiving from a host system a write command associated with switching the memory system to operate according to a second operating mode associated with a second power consumption greater than the first power consumption, the write command containing an image of the memory system associated with operating the memory system according to the second operating mode. The operation of 605 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 605 may be referenced from... Figure 4 The described write command is executed by receiver 440.

[0148] At 610, the method may include: writing an image of the memory system to volatile memory in the memory system, at least in part based on receiving a write command. The operation of 610 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 610 may be derived from references... Figure 4 The image writing manager 445 is executed as described.

[0149] At 615, the method may include: operating the memory system according to a second operating mode in response to receiving a write command and based at least in part on writing an image of the memory system to volatile memory. The operation of 615 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 615 may be derived from references... Figure 4 The described mode operation manager 435 is executed.

[0150] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving from a host system a write command associated with switching the memory system to operation according to a second operating mode associated with a second power consumption greater than the first power consumption, the write command including an image of the memory system associated with operating the memory system according to the second operating mode; writing the image of the memory system to volatile memory in the memory system at least in part based on receiving the write command; and operating the memory system according to the second operating mode in response to receiving the write command and at least in part based on writing the image of the memory system to volatile memory.

[0151] In some instances of the method 600 and apparatus described herein, data indicating a mapping between an image in the memory system and volatile memory is read from non-volatile memory in the memory system, wherein the image written to the memory system may be at least partially based on the read.

[0152] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving, from a host system, signaling associated with the image of the memory system indicating a mapping between the image of the memory system and volatile memory.

[0153] In some instances of the method 600 and apparatus described herein, the image includes data stored in volatile memory for operating the memory system according to a second operating mode, data associated with a controller of the volatile memory for operating the memory system according to the second operating mode, data stored in the logical-physical mapping table of the memory system for operating the memory system according to the second operating mode, data associated with the configuration of the volatile memory for operating the memory system according to the second operating mode, or any combination thereof.

[0154] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: receiving a read command from a host system associated with switching the memory system to operation according to a first operating mode when operating the memory system according to a second operating mode; transferring an image of the memory system to the host system based at least in part on receiving the read command; and operating the memory system according to the first operating mode in response to receiving the read command and based at least in part on transferring the image of the memory system, wherein receiving a write command may be based at least in part on operating the memory system according to the first operating mode.

[0155] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0156] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, a signal may represent a bus of signals, which may have various bit widths.

[0157] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between electronically connected (or electrically contacting, connected, or coupled) components can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0158] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0159] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, then the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0160] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process, then the terms are interchangeable.

[0161] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0162] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" such other condition or action.

[0163] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0164] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor can be "off" or "deactivated."

[0165] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0166] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0167] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0168] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0169] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0170] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0171] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory device including volatile memory cells; as well as A controller, coupled to the memory device and configured to cause the device to perform the following operations: Transmit capability information to the host system, the capability information indicating the device's ability to switch between operating modes based at least in part on a read command; While operating the device according to a first operating mode associated with a first power consumption, the controller receives a read command from the host system at least in part based on the capability information, the read command instructing the controller to switch the device to operate according to a second operating mode associated with a second power consumption lower than the first power consumption, wherein the read command includes a request for an image of the device; The image of the device, stored in the memory device and based at least in part on the device being operated according to the first operating mode, is transmitted to the host system based at least in part on receiving the read command; as well as The device is operated according to the second operating mode in response to receiving the read command and based at least in part on the transmission of the image of the device.

2. The device according to claim 1, wherein, for transmitting the capability information, the controller is further configured to cause the device to perform the following operations: The register stores a value indicating the ability of the device to execute the read command associated with converting the device to operate according to the second operating mode.

3. The device according to claim 1, wherein, for transmitting the capability information, the controller is further configured to cause the device to perform the following operations: The host system is transmitted signaling including the capability information, which instructs the device to execute the capability associated with the read command that converts the device to operation according to the second operating mode.

4. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The host system is instructed with a threshold size for the image of the device transmitted in response to one or more read commands associated with converting the device to operation according to the second operating mode, wherein receiving the read command is at least in part based on indicative of the threshold size.

5. The device of claim 4, wherein, in order to indicate the threshold size of the image of the device, the controller is further configured to cause the device to perform the following operations: A value indicating the threshold size of the image is stored in a register, wherein the indication is based at least in part on storing the value in the register.

6. The device of claim 4, wherein, in order to indicate the threshold size of the image of the device, the controller is further configured to cause the device to perform the following operations: The signaling indicating the threshold size of the image is transmitted to the host system.

7. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: When operating the device according to the second operating mode, a write command associated with switching the device to operate according to the first operating mode is received from the host system, the write command including the image of the device; The image of the device is written to the memory device, at least in part, based on receiving the write command; as well as The device is operated in the first operating mode in response to receiving the write command and based at least in part on writing the image of the device to the memory device.

8. The device of claim 7, wherein the controller is further configured to cause the device to perform the following operations: At least in part, error control information corresponding to the image of the device is generated based on receiving the read command, wherein transmitting the image of the device further includes transmitting the error control information to the host system; and Error control operations are performed on the image of the device using the error control information, at least in part, based on receiving the write command that further includes the error control information, wherein writing the image of the device to the memory device is at least in part based on performing the error control operations.

9. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: At least in part based on receiving the read command, data indicating the mapping between the image of the device and the memory device is stored in the memory device, so that the device can write the image of the device to the memory device after operating the device according to the second operating mode.

10. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The signaling associated with the image of the device, indicating the mapping between the image of the device and the memory device, is transmitted to the host system at least in part based on receiving the read command.

11. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The image of the device is stored in non-volatile memory at least in part based on receiving the read command, wherein the device is operated according to the second operating mode at least in part based on the storage.

12. The device of claim 1, wherein the image comprises data stored in the memory device when the device receives the read command.

13. The device of claim 1, wherein the image includes data associated with a second controller of the memory device when the device receives the read command.

14. The device of claim 1, wherein the image includes data stored in the logical-physical mapping table of the device when the device receives the read command.

15. The device of claim 1, wherein the image includes data associated with the configuration of the memory device when the device receives the read command.

16. An apparatus comprising: A memory device including volatile memory cells; as well as A controller, coupled to the memory device and configured to cause the device to perform the following operations: Indicate to the host system the threshold size of the image of the device transmitted to the host system in response to one or more read commands associated with converting the device to operation according to a second operating mode; When the device is operated according to a first operating mode associated with a first power consumption, a read command is received from the host system that is associated with switching the device to operate according to a second operating mode associated with a second power consumption lower than the first power consumption, wherein receiving the read command is based at least in part on an indication of the threshold size; An image of the device stored in the memory device, which is at least partially based on the device being operated according to the first operating mode, is transferred to the host system based at least in part on receiving the read command, wherein the read command includes a field indicating the threshold size of the image of the device transferred in response to the read command; as well as The device is operated according to the second operating mode in response to receiving the read command and based at least in part on the transmission of the image of the device.

17. An apparatus comprising: A memory device including volatile memory cells; as well as A controller, coupled to the memory device and configured to cause the device to perform the following operations: Transmit capability information to the host system, the capability information indicating the device's ability to switch between operating modes based at least in part on write commands; While operating the device according to a first operating mode associated with a first power consumption, the controller receives a write command from the host system at least in part based on the capability information. The write command instructs the controller to switch the device to operate according to a second operating mode associated with a second power consumption greater than the first power consumption. The write command includes an image of the device associated with operating the device according to the second operating mode. The image of the device is written to the memory device, at least in part, based on receiving the write command; as well as The device is operated according to the second operating mode in response to receiving the write command and based at least in part on writing the image of the device to the memory device.

18. The device of claim 17, wherein the controller is further configured to cause the device to perform the following operations: Data indicating the mapping between the image of the device and the memory device is read from the memory device, wherein the image written to the device is at least partially based on the read.

19. The device of claim 17, wherein the controller is further configured to cause the device to perform the following operations: The host system receives signaling associated with the image of the device, indicating the mapping between the image of the device and the memory device.

20. The device of claim 17, wherein the image includes data stored in the memory device for operating the device according to the second operating mode.

21. The device of claim 17, wherein the image includes data associated with a second controller of the memory device for operating the device according to the second operating mode.

22. The device of claim 17, wherein the image includes data stored in the logical-physical mapping table of the device for operating the device according to the second operating mode.

23. The device of claim 17, wherein the image includes data associated with the configuration of the memory device for operating the device according to the second operating mode.

24. The device of claim 17, wherein the controller is further configured to cause the device to perform the following operations: When operating the device according to the second operating mode, a read command associated with switching the device to operate according to the first operating mode is received from the host system; The image from the device is transmitted to the host system, at least in part, based on receiving the read command; as well as The device is operated in accordance with the first operating mode in response to receiving the read command and at least in part based on transmitting the image of the device, wherein the write command is received at least in part based on operating the device in accordance with the first operating mode.

25. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Transmit capability information to the host system, the capability information indicating the electronic device's ability to switch between operating modes based at least in part on a read command; While operating the electronic device according to a first operating mode associated with a first power consumption, the processor receives a read command from the host system at least in part based on the capability information. The read command instructs the processor to switch the electronic device to operate according to a second operating mode associated with a second power consumption lower than the first power consumption, wherein the read command includes a request for an image of the electronic device. The image of the electronic device, stored in volatile memory and based at least in part on the electronic device being operated according to the first operating mode, is transmitted to the host system based at least in part on receiving the read command; as well as The electronic device is operated according to the second operating mode in response to receiving the read command and based at least in part on the transmission of the image of the electronic device.

26. The non-transitory computer-readable medium of claim 25, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The host system is instructed a threshold size for the image of the electronic device transmitted to the host system in response to one or more read commands associated with converting the electronic device to operation according to the second operating mode, wherein receiving the read command is at least in part based on indicative of the threshold size.

27. The non-transitory computer-readable medium of claim 25, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: When the electronic device is operated according to the second operating mode, a write command associated with switching the electronic device to operate according to the first operating mode is received from the host system, the write command including the image of the electronic device; The image of the electronic device is written to the volatile memory, at least in part based on receiving the write command; as well as The electronic device is operated according to the first operating mode in response to receiving the write command and based at least in part on writing the image of the electronic device to the volatile memory.

28. The non-transitory computer-readable medium of claim 25, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: At least in part based on receiving the read command, data indicating the mapping between the image of the electronic device and the volatile memory is stored in the non-volatile memory, so that the electronic device can write the image of the electronic device to the volatile memory after operating the electronic device according to the second operating mode.

29. The non-transitory computer-readable medium of claim 25, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The signaling associated with the image of the electronic device, indicating the mapping between the image of the electronic device and the volatile memory, is transmitted to the host system at least in part based on receiving the read command.

Images