A superscalar microprocessor method of out-of-order data instruction early commit

Abstract

The application relates to a method for early submission of a non-equal data storage instruction of a superscalar microprocessor, which comprises the following steps: obtaining a memory access instruction from an instruction sequence, wherein the memory access instruction comprises a load instruction and a store instruction; decomposing the store instruction into an address calculation microinstruction and a store data microinstruction; the address calculation microinstruction and the store data microinstruction enter a launch queue together and are launched and executed independently; the address calculation microinstruction is launched preferentially, executes memory address calculation, virtual-real address conversion and accesses a storage subsystem; if the address calculation microinstruction hits a level-1 data cache and obtains writable permission, and the store instruction has become the oldest instruction in the instruction sequence, the store instruction is submitted regardless of whether the store data microinstruction has been launched and executed or not. The application can significantly improve the performance of a superscalar processor.

Description

Technical Field

[0001] This invention relates to the field of superscalar microprocessor microarchitecture design optimization technology, and in particular to a method for pre-submitting data with unequal storage instructions in a superscalar microprocessor. Background Technology

[0002] Current superscalar microprocessors support out-of-order issue, out-of-order execution, speculative execution, and sequential commit, such as Figure 1 As shown, an instruction pipeline typically includes several basic pipeline stages: fetch, decode, register renaming, issue, execute, and retire. A full instruction reordering buffer (ROB) is set up on the instruction pipeline to control the submission of all instructions in program order. Instructions submitted first in program order are called older instructions, and those submitted later are called younger instructions.

[0003] As a crucial metric for processor performance, the number of instructions executed per clock cycle (IPC) is closely related to the instruction pipeline's fetch, decode, issue width, and instruction execution and commit speeds. In Reduced Instruction Set Computing (RISC) systems, instructions can be broadly categorized into two types: arithmetic instructions, whose operands are stored in the processor's internal registers, and whose execution time is fixed; and memory access instructions, whose access data may reside in different levels of the processor's cache or in external main memory, and whose execution time is variable, ranging from a few clock cycles to hundreds of clock cycles. Therefore, memory access instructions are often the primary culprit limiting instruction commit speed.

[0004] Memory access instructions are divided into load instructions and store instructions. To control out-of-order execution of memory access instructions, the processor has a dedicated memory access queue to cache in-flight memory access instructions. Physically, the memory access queue can be a single merged queue (MQ) that stores both load and store instructions; or it can be two separate queues that store load instructions (LQ) and store instructions (SQ) respectively.

[0005] like Figure 2As shown, for a load instruction, after reading data from the Level 1 Data Cache (DCache) or main memory and writing it to a register, it can report completion to the ROB, and then the ROB submits the load instruction in instruction order. For a store instruction, it first accesses the DCache or main memory to obtain writable permissions for the data and the latest copy of the data. Then, it waits for the ROB to notify it that it has become the oldest instruction in the instruction sequence before writing the data to the DCache or sending it to main memory, and reporting the instruction's completion to the ROB. Then, the ROB submits the store instruction in instruction order. Therefore, there is a dependency between the SQ and the ROB, resulting in the store instruction submission speed being slower than the load instruction.

[0006] To ensure the correctness of program execution results, any memory consistency model requires that when a younger load instruction and an older store instruction access the same address, the load instruction must read the data written by the store instruction. In superscalar microprocessors, register renaming and scoreboard techniques are typically used to implement out-of-order instruction issuance and execution, thereby improving the processor core's IPC. The register number carried in the instruction is a logical register number, and the number of logical registers is limited due to instruction encoding (usually 32). However, the processor internally sets up more physical registers and uses register renaming techniques to allow more register-independent instructions to execute in parallel.

[0007] At the instruction issue station, the readiness of all source registers for the instruction is first checked. Then, arbitration is performed between the register write port and the issue port, and other issue conditions are determined. Load instructions contain only one source register, specifying the main memory address to be loaded (read). Store instructions contain two source registers: one specifying the main memory address to be stored (written), and the other specifying the data to be stored (written). For load and store instructions accessing the same main memory address, the source register specifying the main memory address is usually the same register. When the source register specifying the main memory address is readable, the load instruction may be issued before the store instruction because the store instruction needs to additionally check whether the source register for the stored data is ready. After the store instruction is issued to the memory access unit, the load instruction and subsequent instructions are invalidated, and the instruction pipeline is notified to restart instruction fetching and execution from the load instruction. This process directly introduces pipeline bubbles, affecting processor performance and wasting power. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a method for pre-committing data when storage instructions are not equal in a superscalar microprocessor. This method correctly implements the storage instruction function without changing the original memory order model. By reducing the conditions for storage instruction submission, it speeds up the execution of the instruction pipeline and significantly improves the performance of the superscalar processor.

[0009] The technical solution adopted by the present invention to solve its technical problem is: to provide a method for early submission of storage instructions and unequal data in a superscalar microprocessor, comprising: obtaining a memory access instruction from an instruction sequence, wherein the memory access instruction includes a load instruction and a store instruction; decomposing the store instruction into an address calculation microinstruction and a store data microinstruction, wherein the address calculation microinstruction and the store data microinstruction enter the issue queue together and are issued and executed independently;

[0010] The address calculation microinstruction is issued first to perform memory access address calculation, virtual-physical address substitution, and access to the storage subsystem. If the address calculation microinstruction hits the first-level data cache and obtains write permission, and the storage instruction has become the oldest instruction in the instruction sequence, then the storage instruction is committed regardless of whether the storage data microinstruction has been issued and executed.

[0011] When the address calculation microinstruction and the data storage microinstruction enter the launch queue together:

[0012] If an exception occurs during virtual-to-physical address substitution or an access permission error occurs, the exception is registered in the SQ queue, and the system enters the "waiting for exception handling" state after reporting the exception to the full instruction reordering buffer ROB.

[0013] If the virtual address substitution is completed normally and the access permissions are normal, but the copy in the DCache is not hit or the write permission is not obtained, the write request will be suspended and enter the "waiting for a writeable copy to be obtained in the DCache" state.

[0014] If the virtual and physical address substitution is completed normally, the access permissions are normal, the DCache copy is hit and write permissions are obtained, but the full instruction reordering buffer ROB does not allow the storage instruction to be committed, then the SQ entry enters the "waiting for ROB to allow commit" state.

[0015] If the virtual-to-physical address swapping is completed normally, access permissions are normal, the DCache copy is hit and write permissions are obtained, and the full instruction reordering buffer ROB allows the storage instruction to be committed, then the SQ entry enters the "ready to report completion to ROB" state.

[0016] The SQ entries in the SQ queue are in the "waiting for exception handling" state, waiting for the stored instruction to become the oldest instruction in the full instruction reordering buffer (ROB). Specifically, if the stored instruction is not the oldest instruction in the full instruction reordering buffer (ROB), it remains in the current state; when the stored instruction becomes the oldest instruction in the full instruction reordering buffer (ROB), the SQ entry is deleted and exception handling is performed.

[0017] The SQ entries in the SQ queue wait to obtain a data copy and write permissions from the next-level cache or main memory in the "Waiting for a writable copy to be obtained in DCache" state. Specifically: if a writable copy is not obtained in DCache, the entry remains in the current state; when a writable copy is obtained in DCache, the entry further determines whether the full instruction reordering buffer (ROB) allows the commit of storage instructions. If the ROB does not allow the commit of storage instructions, the entry jumps to the "Waiting for ROB to allow commit" state; if the ROB allows the commit, the entry jumps to the "Preparing to report completion to ROB" state.

[0018] The SQ entries in the SQ queue wait for the ROB to give a commit signal in the "Waiting for ROB to allow commit" state. Specifically, if no commit signal is received from the full instruction reordering buffer ROB, the entry remains in the current state; once the commit signal is received from the full instruction reordering buffer ROB, the entry jumps to "Preparing to report completion status to ROB".

[0019] The SQ entries in the SQ queue request to report completion to the full instruction reordering buffer ROB when they are in the "preparing to report completion to ROB" state. If they fail to report completion to the full instruction reordering buffer ROB, they remain in the current state and continue to request to report completion to the full instruction reordering buffer ROB. If they successfully report completion to the full instruction reordering buffer ROB in the current state, they further determine whether they have received the stored data. If they have not received the stored data, they jump to the "waiting for stored data" state. If they have received the stored data, they jump to the "preparing to write to DCache" state.

[0020] The SQ entries in the SQ queue wait for the storage data microinstruction to be issued to the memory access unit and register the SQ entries in the "waiting for storage data" state. If no storage data is received, the entries remain in this state. When storage data is received, the SQ entries jump to the "ready to write to DCache" state.

[0021] The SQ entries in the SQ queue request to write to the DCache in the "ready to write to DCache" state. If the write to DCache operation is not completed, the entry remains in the state and continues to request to write to the DCache. If the stored data is successfully written to the DCache, the SQ entry is released.

[0022] After submission, the storage instruction enters the buffer to wait. When the storage data microinstruction meets the conditions, it is issued, the storage data is read from the register file, enters the buffer and merges with the address calculation microinstruction, and the storage data is written into the first-level data cache. After that, the storage data becomes visible to the memory model.

[0023] When the reallocated physical register number is equal to the physical source register number of the stored data microinstruction, register renaming of the current instruction is prevented until the stored data microinstruction is issued.

[0024] When a consistency request address from outside the kernel is the same as the address of the storage instruction, the consistency request must be prevented from being executed until the storage instruction writes the data into the first-level data cache.

[0025] The cache line in the Level 1 data cache accessed by the storage instruction cannot be evicted by other younger memory access instructions until the storage instruction writes the data into the Level 1 data cache.

[0026] Beneficial effects

[0027] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: When determining whether a storage instruction can report completion to the ROB, the present invention only depends on whether the ROB allows the storage instruction to be submitted, and whether the address calculation micro-instruction decomposed from the instruction has been issued to the memory access unit and completed the virtual-physical address substitution and permission check, hit the writable copy in the DCache, etc. It does not need to pay attention to whether the decomposed storage data micro-instruction has read the data to be stored from the register file and issued to the memory access unit, and whether it has been written to the SQ entry, etc. On the one hand, fewer conditions are required for a single memory instruction to become committable, allowing for earlier release of resources such as the corresponding ROB entry, accelerating the entry of subsequent instructions into the out-of-order execution window. On the other hand, to support the parallel issuance and execution of multiple memory instructions, multiple sets of pipeline resources are needed for address computation microinstructions, while fewer pipeline resources are needed for memory data microinstructions. This is because the execution speed of memory data microinstructions is decoupled from the execution speed of memory instructions. Therefore, this resource configuration will not affect performance in most cases, while reducing hardware overhead and physical implementation difficulty, which is very beneficial for improving the chip's performance-to-power ratio. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the instruction pipeline in the background technology of this invention;

[0029] Figure 2 This is a schematic diagram illustrating the out-of-order execution of load and store instructions in the background technology of this invention;

[0030] Figure 3 This is a schematic diagram of SQ entry management according to an embodiment of the present invention. Detailed Implementation

[0031] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0032] Embodiments of the present invention relate to a method for pre-committing data with instruction inequality in a superscalar microprocessor, comprising:

[0033] Obtain memory access instructions from the instruction sequence, the memory access instructions including load instructions and store instructions;

[0034] The storage instruction is decomposed into address calculation microinstructions and storage data microinstructions. The address calculation microinstructions and storage data microinstructions enter the launch queue together and are launched and executed independently.

[0035] The address calculation microinstruction is issued first to perform memory access address calculation, virtual-physical address substitution, and access to the storage subsystem. If the address calculation microinstruction hits the first-level data cache and obtains write permission, and the storage instruction has become the oldest instruction in the instruction sequence, then the storage instruction is committed regardless of whether the storage data microinstruction has been issued and executed.

[0036] Furthermore, the submitted store instruction enters a specific buffer to wait. Once the storage data microinstruction meets the conditions, it is issued, reads the storage data from the register file, enters the buffer, merges with the address calculation microinstruction, and writes the storage data into the first-level data cache. After that, the storage data becomes visible to the memory model.

[0037] Furthermore, in order to ensure that the stored data microinstruction can still read the stored data in the source register normally after its stored instruction is submitted, the register renaming logic must be subject to additional control. That is, when the reallocated physical register number is equal to the physical source register number of the stored data microinstruction, the current instruction is prevented from renaming the register until the stored data microinstruction is issued.

[0038] Furthermore, a storage instruction that has been submitted but has not yet received the stored data cannot be rolled back or made visible to the memory model. Therefore, when a consistency request address from outside the kernel is the same as the address of the storage instruction (the address comparison is performed at the smallest granularity of the Cache consistency protocol), the consistency request must be prevented from executing until the storage instruction writes the data into the first-level data cache.

[0039] Furthermore, a storage instruction that has been submitted but has not yet received the stored data cannot be rolled back or made visible to the memory model. Therefore, the cache line in the Level 1 data cache accessed by the storage instruction cannot be evicted by other younger memory access instructions until the storage instruction writes the data into the Level 1 data cache.

[0040] Furthermore, the committed storage instruction can release instruction pipeline resources, such as the full instruction reorder buffer (ROB), allowing subsequent younger instructions to continue committing.

[0041] Furthermore, storage instructions that have been submitted but have not yet received the stored data can wait in a separate buffer or continue to wait in the storage instruction reordering buffer (SQ), but a special flag needs to be set to distinguish them from unsubmitted storage instructions.

[0042] The following is a detailed description of this implementation method:

[0043] Assume the assembly instruction format of a store instruction is: st r1, disp(r2), where r1 is the logical source register 1, storing the data to be stored; r2 is the logical source register 2, storing the memory base address; disp represents the address offset relative to the memory base address; the memory address accessed by this store instruction is equal to the memory base address in register r2 plus the address offset.

[0044] After register renaming, the store instruction has the format: st p1, disp(p2), where p1 is the physical source register 1, storing the data to be stored; p2 is the physical source register 2, storing the memory base address. This store instruction is decomposed into the following two micro-instructions:

[0045] (1) Address calculation microinstruction: st_addr disp(p2);

[0046] (2) Data storage micro-instruction: st_datap1.

[0047] Two microinstructions enter the issue queue together and are then issued and executed independently. Like other instructions, these two microinstructions undergo issue condition checks, including checking if the source register is ready and competing for the issue port and register file read port. To simplify the control complexity of the Store-to-Reorder Queue (SQ), it is agreed that, based on the microinstruction's own issue conditions being met, the address computation microinstruction is issued first, followed by the store-to-data microinstruction.

[0048] After the address calculation microinstruction (st_addr disp(p2)) is issued to the memory access unit, the memory access base address is read from the physical register p2, added to the address offset (disp), and used as the actual virtual memory address (VAddr). The subsequent processing of the memory instruction is determined based on the virtual-to-physical address substitution, permission checks (whether there are any anomalies, whether the DCache copy has been hit and write access has been obtained, whether the ROB allows the memory instruction to be committed, and whether memory data has been received). Figure 3 As shown, SQ entries can be managed using a state machine, as detailed below:

[0049] (1) After the memory access instruction is sent to the memory access unit, if there is an error in the virtual-physical address substitution or the access permission is incorrect, the abnormal situation is registered in SQ and the "waiting for abnormal handling" state is entered after the abnormality is reported to ROB.

[0050] (2) After the memory access instruction is sent to the memory access unit, if the virtual and physical address substitution is completed normally and the access permission is normal, but the copy in the DCache is not hit or the write permission is not obtained, the write request is suspended and enters the "waiting for the DCache to obtain a writeable copy" state.

[0051] (3) After the memory access instruction is sent to the memory access unit, if the virtual and physical address substitution is completed normally, the access permissions are normal, the DCache copy is hit and write permissions are obtained, but the ROB does not allow the storage instruction to be submitted, then the SQ entry enters the "waiting for ROB to allow submission" state.

[0052] (4) After the memory access instruction is sent to the memory access unit, if the virtual and physical address substitution is completed normally, the access permissions are normal, the DCache copy is hit and write permissions are obtained, and the ROB allows the memory instruction to be submitted, then the SQ entry enters the "preparing to report completion to the ROB" state.

[0053] (5) The SQ entry waits in the "Waiting for exception handling" state for the stored instruction to become the oldest instruction in the ROB. If the stored instruction is not the oldest instruction in the ROB, it remains in this state; when the stored instruction becomes the oldest instruction in the ROB, the SQ entry is deleted and exception handling is performed;

[0054] (6) SQ entries wait in the "Waiting for a writable copy to be obtained in DCache" state to obtain a data copy and writable permissions from the next level cache or main memory. If a writable copy is not obtained in DCache, it remains in this state; when a writable copy is obtained in DCache, it further determines whether ROB allows the storage instruction to be committed. If ROB does not allow the storage instruction to be committed, it jumps to the "Waiting for ROB to allow commit" state; if ROB allows the commit, it jumps to the "Preparing to report to ROB" state.

[0055] (7) The SQ entry waits for the ROB to give a signal to allow submission in the "Waiting for ROB to allow submission" state. If no signal to allow submission is received from the ROB, it remains in this state; when the signal to allow submission is received from the ROB, it jumps to "Preparing to report the completion status to the ROB";

[0056] (8) When an SQ entry is in the "Preparing to report completion to ROB" state, it requests to report completion to ROB. If it fails to report completion to ROB, it remains in the same state and continues to request to report completion to ROB. After successfully reporting completion to ROB in this state, it further determines whether the stored data has been received. If the stored data has not been received, it jumps to the "Waiting for stored data" state. If the stored data has been received, it jumps to the "Preparing to write to DCache" state.

[0057] (9) The SQ entry waits in the "Waiting for stored data" state for the stored data microinstruction to be issued to the memory access unit and for the SQ entry to be registered. If no stored data is received, it remains in this state; when stored data is received, the SQ entry jumps to the "Ready to write to DCache" state;

[0058] (10) When an SQ entry requests to write to the DCache in the "ready to write to DCache" state, if the write operation to the DCache is not completed, it remains in the state and continues to request to write to the DCache; if the stored data is successfully written to the DCache, the SQ entry is released.

[0059] Meanwhile, when the ROB recognizes that the store instruction is the oldest instruction in the instruction sequence, it notifies the SQ to allow its commit. At this time, the store data microinstruction (st_datap1) may still be waiting in the issue queue, may be reading the register file, or may have been issued to the memory access unit and merged with the address calculation microinstruction in the SQ. If the address calculation microinstruction in the SQ has an exception and has reported an abnormal completion to the ROB, the store instruction is removed from the ROB header, and the SQ is notified to delete the corresponding entry. The instruction pipeline deletes any store data microinstructions that may not have been issued, as well as all instructions younger than the store instruction, and then enters the exception handler for execution. If the address calculation microinstruction of the store instruction has reported normal completion to the ROB, the store instruction is removed from the ROB header regardless of whether the store data microinstruction has reached the SQ.

[0060] To ensure this optimization does not alter the processor's memory coherence model, all committed memory instructions must write the data to the DCache sequentially. Memory instructions committed but not yet receiving data cannot execute DCache write operations until the data is received. Therefore, all committed memory instructions, regardless of whether data has been received, need to enter a First-In-First-Out (FIFO) queue to wait. Once the conditions for writing to the DCache are met, the data is written to the DCache sequentially. In practice, an additional FIFO queue can be used to cache committed memory instructions, or the SQ queue can continue to be used. When using the SQ queue to cache committed memory instructions, the time a memory instruction occupies an SQ entry increases, and the probability of the instruction pipeline blocking due to insufficient SQ entries to hold subsequent memory instructions issued to the memory access unit increases. Therefore, the number of SQ entries needs to be appropriately increased to mitigate the additional impact of this optimization.

[0061] For ease of control, committed storage instructions that have not yet been written to the DCache continue to wait in the SQ (Storage Queues), with separate head and tail pointers and status indicators. Committed storage instructions are evaluated sequentially in the order of the instructions. If the stored data has been received, the write to the DCache is executed; otherwise, this instruction and subsequent committed storage instructions continue to wait.

[0062] For the storage consistency model, storage instructions that have been committed by the ROB but have not yet written storage data to the DCache need to be visible to other cores. Therefore, in a multi-core architecture, if a core receives a consistency request address that is the same as the storage address accessed by such a storage instruction, the processing of the consistency request needs to be blocked until the storage instruction writes the storage data to the DCache. It's important to note that in a multi-core architecture, the smallest data granularity processed by the cache consistency protocol is generally a cache line. Therefore, the addresses accessed by the consistency request and the addresses accessed by the storage instruction are compared in units of cache line addresses. Since the storage data instructions decomposed from the storage instruction only access one source register, and the committed storage instruction is certainly the oldest instruction in the instruction sequence, the storage data instruction will not be unable to be issued indefinitely due to the source register not being ready. It will only be temporarily blocked due to conflicts in the issue port or register read port. Therefore, the consistency request will not be blocked indefinitely because it is the same as the address of a committed storage instruction that has not yet been written to the DCache, i.e., it will not cause a system deadlock problem. Assuming the cache line size is 128 bytes in this processor, the lowest 7 bits are ignored when comparing the address accessed by a consistency request with the address accessed by a memory instruction.

[0063] Since a committed memory access instruction that has not yet written the data to the DCache cannot be rolled back, and the instruction had already obtained write permission for the accessed DCache line before committing, the accessed DCache line cannot be evicted by other younger memory access instructions before the data is written to the DCache. When a younger load or store instruction is received, if it misses the DCache and the accessed DCache line needs to be evicted, the younger memory access instruction enters the LQ or SQ waiting state. When a younger flush or evict instruction is received, it must also enter the LQ or SQ waiting state. Only after the corresponding memory access instruction writes the data to the DCache will these younger memory access instructions be re-executed.

[0064] In the instruction pipeline, after a store instruction is committed, the pipeline resources occupied by that store instruction are released (e.g., ROB entries). Instructions targeting register P1 are likely executed and committed before the store instruction, and P1 becomes an idle physical register, theoretically ready to be allocated to new instructions at any time. However, if a store data microinstruction (st_datap1) is still waiting in the issue queue, since its execution requires reading source register P1, register renaming must be stopped during register renaming if it is detected that P1 is about to be reassigned to another logical register, thus blocking the instruction pipeline until the store data microinstruction (st_datap1) is issued.

[0065] In the above optimization, determining whether a storage instruction can report completion to the ROB depends only on whether the ROB allows the storage instruction to be committed, and whether the address calculation micro-instructions decomposed from the instruction have been issued to the memory access unit and completed virtual-to-physical address substitution, permission checks, and hit writable copies in the DCache. It does not require consideration of whether the decomposed storage data micro-instructions have read the data to be stored from the register file and issued to the memory access unit, or whether they have been written to the SQ entry. On one hand, fewer conditions are required for a single storage instruction to become committable, allowing for earlier release of resources such as the corresponding ROB entry, accelerating the entry of subsequent instructions into the out-of-order execution window. On the other hand, to support the parallel issuance and execution of multiple storage instructions, multiple sets of pipeline resources supporting address calculation micro-instructions are needed, while fewer pipeline resources are required for storage data micro-instructions. This is because the execution speed of storage data micro-instructions is decoupled from the execution speed of storage instructions. Therefore, this resource configuration does not affect performance in most cases, while reducing hardware overhead and physical implementation difficulty, which is highly beneficial for improving the chip's performance-to-power ratio.

[0066] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A method for pre-committing data inequalities in storage instructions in a superscalar microprocessor, characterized in that, include: Obtain memory access instructions from the instruction sequence, the memory access instructions including load instructions and store instructions; The storage instruction is decomposed into address calculation microinstructions and storage data microinstructions. The address calculation microinstructions and storage data microinstructions enter the launch queue together and are launched and executed independently. The address calculation microinstruction is issued first to perform memory access address calculation, virtual-physical address substitution, and access to the storage subsystem. If the address calculation microinstruction hits the first-level data cache and obtains write permission, and the storage instruction has become the oldest instruction in the instruction sequence, then the storage instruction is committed regardless of whether the storage data microinstruction has been issued and executed.

2. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 1, characterized in that, When the address calculation microinstruction and the data storage microinstruction enter the launch queue together: If an exception occurs during virtual-to-physical address substitution or an access permission error occurs, the exception is registered in the SQ queue, and the system enters the "waiting for exception handling" state after reporting the exception to the full instruction reordering buffer ROB. If the virtual address substitution is completed normally and the access permissions are normal, but the copy in the DCache is not hit or the write permission is not obtained, the write request will be suspended and enter the "waiting for a writeable copy to be obtained in the DCache" state. If the virtual and physical address substitution is completed normally, the access permissions are normal, the DCache copy is hit and write permissions are obtained, but the full instruction reordering buffer ROB does not allow the storage instruction to be committed, then the SQ entry enters the "waiting for ROB to allow commit" state. If the virtual-to-physical address swapping is completed normally, access permissions are normal, the DCache copy is hit and write permissions are obtained, and the full instruction reordering buffer ROB allows the storage instruction to be committed, then the SQ entry enters the "ready to report completion to ROB" state.

3. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 2, characterized in that, The SQ entries in the SQ queue are in the "Waiting for Exception Handling" state, waiting for the stored instruction to become the oldest instruction in the full instruction reordering buffer (ROB). Specifically, if the stored instruction is not the oldest instruction in the full instruction reordering buffer (ROB), it remains in the current state; when the stored instruction becomes the oldest instruction in the full instruction reordering buffer (ROB), the SQ entry is deleted and exception handling is performed.

4. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 2, characterized in that, The SQ entries in the SQ queue wait to obtain a data copy and write permissions from the next level cache or main memory in the "waiting for a writable copy to be obtained in DCache" state. Specifically: if a writable copy is not obtained in DCache, the current state is maintained; when a writable copy is obtained in DCache, it is further determined whether the full instruction reordering buffer ROB allows the commit of storage instructions. If the full instruction reordering buffer ROB does not allow the commit of storage instructions, the process jumps to the "waiting for ROB to allow commit" state. If the full instruction reordering buffer ROB allows commits, then jump to the "Ready to report completion to ROB" state.

5. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 2, characterized in that, The SQ entries in the SQ queue wait for the ROB to give a commit signal in the "Waiting for ROB to allow commit" state. Specifically, if no commit signal is received from the full instruction reordering buffer ROB, the entry remains in the current state; when a commit signal is received from the full instruction reordering buffer ROB, the entry jumps to the "Preparing to report completion to ROB" state.

6. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 2, characterized in that, The SQ entries in the SQ queue request to report completion to the full instruction reordering buffer ROB when they are in the "preparing to report completion to ROB" state. If they fail to report completion to the full instruction reordering buffer ROB, they remain in the current state and continue to request to report completion to the full instruction reordering buffer ROB. If they successfully report completion to the full instruction reordering buffer ROB in the current state, they further determine whether they have received the stored data. If they have not received the stored data, they jump to the "waiting for stored data" state. If the stored data has been received, proceed to the "Ready to write to DCache" state.

7. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 6, characterized in that, The SQ entries in the SQ queue wait for the storage data microinstruction to be issued to the memory access unit and register the SQ entries in the "waiting for storage data" state. If no storage data is received, the entries remain in this state. When storage data is received, the SQ entries jump to the "ready to write to DCache" state. The SQ entries in the SQ queue request to write to the DCache when they are in the "Ready to Write to DCache" state. If the write to DCache operation is not completed, they remain in this state and continue to request to write to the DCache. If the stored data is successfully written to the DCache, the SQ entries are released.

8. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 1, characterized in that, After submission, the storage instruction enters the buffer to wait. When the storage data microinstruction meets the conditions, it is issued, the storage data is read from the register file, enters the buffer and merges with the address calculation microinstruction, and the storage data is written into the first-level data cache. After that, the storage data becomes visible to the memory model.

9. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 1, characterized in that, When the reallocated physical register number is equal to the physical source register number of the stored data microinstruction, register renaming of the current instruction is prevented until the stored data microinstruction is issued.

10. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 1, characterized in that, When a consistency request address from outside the kernel is the same as the address of the storage instruction, the consistency request must be prevented from being executed until the storage instruction writes the data into the first-level data cache.

11. The method for pre-submitting data with unequal storage instructions in a superscalar microprocessor according to claim 1, characterized in that, The cache line in the Level 1 data cache accessed by the storage instruction cannot be evicted by other younger memory access instructions until the storage instruction writes the data into the Level 1 data cache.

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