Information processing method and apparatus, device, equipment, storage medium

Abstract

The application discloses an information processing method and device, a device, equipment and a storage medium. The method comprises the following steps: starting timing when a first task is started; and adding a first IO request belonging to the first task and generated within a first time length to a first queue reserved by a controller, so that the controller can preferentially process the IO request in the first queue.

Description

Technical Field

[0001] This application relates to electronic technology, including but not limited to information processing methods and apparatus, devices, equipment, and storage media. Background Technology

[0002] With the development of electronic technology, electronic devices are installing an increasing number of applications, such as video apps, shopping apps, games, and instant messaging apps. The startup speed of these applications directly affects the user's interactive experience. Summary of the Invention

[0003] In view of this, the information processing method, apparatus, device, equipment, and storage medium provided in this application can improve the speed of task initiation.

[0004] According to one aspect of the embodiments of this application, an information processing method is provided, comprising: starting a timer when a first task is started; and adding a first input output (IO) request belonging to the first task generated within a first duration to a first queue reserved by the controller, wherein the initial state of the first queue is an empty queue, thereby enabling the controller to prioritize processing IO requests in the first queue.

[0005] According to one aspect of the embodiments of this application, a processor is provided, which executes a program to implement the information processing method described in this application.

[0006] According to one aspect of the embodiments of this application, an on-chip system is provided, including: a processor, random access memory (RAM), and a first controller; wherein, the processor is configured to start timing when a first task is started; and add a first I / O request belonging to the first task generated within a first duration to a reserved third queue in RAM; wherein the initial state of the third queue is an empty queue; the processor is further configured to trigger the first controller to add the I / O requests in the third queue to a reserved first queue of the first controller; wherein the initial state of the first queue is an empty queue, thereby enabling the first controller to prioritize the processing of I / O requests in the first queue; the first controller is configured to read the I / O requests in the third queue and add them to the first queue.

[0007] According to one aspect of the embodiments of this application, an information processing apparatus is provided, comprising: a first timing module for starting timing when a first task is started; and an adding module for adding a first IO request belonging to the first task generated within a first duration to a first queue reserved by a controller, wherein the initial state of the first queue is an empty queue, thereby enabling the controller to prioritize processing the IO requests in the first queue.

[0008] According to one aspect of the embodiments of this application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the program to implement the information processing method described in this application.

[0009] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the information processing method described in this application.

[0010] In this embodiment of the application, since the initial state of the first queue is an empty queue, that is, before the first IO request is initially added to the first queue, there are no IO requests to be processed in the first queue. Therefore, the first IO request added to the first queue has a higher queuing position because there are no other IO requests in the queue ahead of it, so that these first IO requests can be processed first, thereby shortening the latency of completing the first task startup.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0013] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0014] Figure 1 A schematic diagram of a hardware architecture provided for this application;

[0015] Figure 2 A schematic diagram illustrating one of the processes involved in an I / O request.

[0016] Figure 3 This diagram illustrates the storage format of I / O requests in each module.

[0017] Figure 4 A diagram illustrating the processing path of an IO request;

[0018] Figure 5 This is a schematic diagram illustrating the implementation flow of an information processing method according to an embodiment of this application;

[0019] Figure 6 This is a schematic diagram comparing the results of the controller polling each queue under different conditions, provided in an embodiment of this application.

[0020] Figure 7 This is a schematic diagram illustrating the implementation flow of another information processing method according to an embodiment of this application;

[0021] Figure 8 This is a schematic diagram illustrating the implementation flow of another information processing method according to an embodiment of this application;

[0022] Figure 9 This is a fast track diagram of the storage master controller and storage device controller in an embodiment of this application;

[0023] Figure 10 This is a schematic diagram of the structure of the information processing device according to an embodiment of this application;

[0024] Figure 11 This is a schematic diagram of the structure of a system-on-a-chip according to an embodiment of this application;

[0025] Figure 12 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0028] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0029] It should be noted that the terms "first, second, third" used in the embodiments of this application do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0030] To facilitate readers' understanding of the technical solution of this application, a hardware architecture that may be applicable to the technical solution of this application is first provided here. Figure 1 A schematic diagram of a hardware architecture provided for this application, such as... Figure 1 As shown, the hardware architecture includes a system-on-a-chip (SOC) 11 and a memory device 12. The SOC 11 includes a processor 111, RAM 112, a memory master controller (an example of the first controller mentioned below) 113, and other controllers 114. The memory device 12 includes a memory device controller 121 (an example of the second controller mentioned below) and a storage medium 122. The SOC 11 and the memory device 12 interact via control and data transfer channels.

[0031] It should be noted that, Figure 1 The hardware architecture shown is merely for the purpose of more clearly illustrating the technical solutions of the embodiments of this application and facilitating readers' understanding of these solutions, but it does not constitute a limitation on the technical solutions provided in the embodiments of this application. The technical solutions of the embodiments of this application are not only applicable to this hardware architecture, but also to other hardware architectures capable of handling I / O requests. Those skilled in the art will recognize that, with the evolution of hardware architectures handling I / O requests and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0032] Figure 2 This is a diagram illustrating one type of I / O request processing, such as... Figure 2As shown, firstly, the processor 111 creates an I / O request in RAM, which indicates the location, size, and data itself in the storage device 12. Then, the processor 111 sends the I / O request to the storage master controller 113. Specifically, the processor 111 triggers the storage master controller 113 to operate, and then the storage master controller 113 reads the I / O request from RAM 112. The storage master controller 113 then sends the I / O request to the storage device controller 121. The storage device controller 121 performs a read / write operation on the storage medium 122 according to the I / O request. When the I / O request is a write request, the storage device controller 121 performs a write operation on the storage medium 122, thereby writing the data carried by the I / O request into the storage medium. When the I / O request is a read request, the storage device controller 121 performs a read operation on the storage medium 122, thereby reading the data indicated by the I / O request and returning it to the upper-layer application.

[0033] To accommodate the speed differences between multi-core processors and memory devices, some implementations do not simply perform a single I / O request. For example... Figure 3 As shown, in a software multitasking scenario, multiple tasks run concurrently, generating numerous I / O requests that accumulate in RAM. The processor sends these I / O requests to the storage master controller 113; the storage master controller 113 can cache a certain number of I / O requests, thus sending the I / O requests to the storage device controller 121 while waiting for the hardware bus of the control and data transfer channels to become idle; the storage device controller 121 performs corresponding operations on the storage medium 122 according to the instructions contained in the I / O request.

[0034] like Figure 3 As shown, for multi-core processors, to prevent multiple cores from operating on the same I / O request, the I / O request cache in the storage main controller 113 is divided into multiple groups, each group consisting of a column, called an I / O queue or a storage queue. The queue in RAM 112 is called a software queue, which varies depending on the software design. The queues in the storage main controller 113 and the storage device controller 121 are called hardware I / O queues.

[0035] As can be seen from the preceding introduction, such as Figure 4 As shown, any I / O request must go through the RAM 112 software queue, the storage master controller 113 hardware I / O queue, and the storage device controller 121 hardware I / O queue, which leads to the problem of slow response time for urgent I / O requests.

[0036] To address this technical problem, this application provides an information processing method. Figure 5 This is a schematic diagram illustrating the implementation flow of an information processing method according to an embodiment of this application, such as... Figure 5 As shown, the method may include the following steps 501 to 502:

[0037] Step 501: The processor starts timing when the first task is started;

[0038] Step 502: The processor adds the first IO request belonging to the first task generated within the first time period to the first queue reserved by the controller. The initial state of the first queue is an empty queue, so that the controller can prioritize processing the IO requests in the first queue.

[0039] Understandably, since the first queue is initially empty, meaning there are no pending IO requests in the first queue before the first generated IO request is added to the first queue, the first IO request added to the first queue will be placed at the front of the queue because there are no other IO requests in front of it. This allows these first IO requests to be processed first, thereby shortening the latency of completing the first task startup.

[0040] For example, such as Figure 6 As shown, assume the controller is configured with 4 queues, where queues 0 and 1 are reserved empty queues, and queues 2 and 3 are regular queues. Assume there are currently 10 I / O requests waiting to be processed in each of queues 2 and 3. For ease of description, the 10 I / O requests in queue 2 are sequentially named a1, a2, a3, ..., a10, and the 10 I / O requests in queue 3 are sequentially named b1, b2, b3, ..., b10. When there are no I / O requests in queues 0 and 1, assuming the polling method is to read one I / O request from queues 0, 1, 2, and 3 sequentially, the controller will read a1, b1, a2, b2, a3, b3, ... (as shown in Table 1) according to the configured polling method. If, before reading a1, two first IO requests are inserted into queues 0 and 1 respectively, for ease of description, we will refer to the two first IO requests in queue 0 as c1 and c2, and the two first IO requests in queue 1 as d1 and d2, respectively. In this case, the controller will read c1, d1, a1, b1, c2, d2, a2, b2, a3, b3... according to the configured polling method (as shown in Table 1). It can be seen that c1 and d1 are placed before all IO requests in queues 2 and 3, and c2 and d2 receive priority over a2, b2, a3, and b3.

[0041] Table 1

[0042] When queue 0 and queue 1 have data c1, d1, a1, b1, c2, d2, a2, b2, a3, b3···

[0043] Of course, regardless of which polling method the controller uses to read IO requests from each queue, IO requests entering the first queue will be processed first. This is because the first queue is initially empty; that is, there are no pending IO requests in the first queue before the 0th IO request is added. This allows incoming IO requests to be prioritized in the queue, enabling the controller to read this data as early as possible during polling.

[0044] For example, suppose the controller polls the queues in priority order, such as queues 2, 3, 0, and 1. As shown in Table 2, IO requests c1 and d1 are given priority over IO requests a2 and b2, and IO requests c2 and d2 are given priority over IO requests a3 and b3.

[0045] Table 2

[0046] When queue 0 and queue 1 have data a1, b1, c1, d1, a2, b2, c2, d2, a3, b3···

[0047] On the other hand, only the first IO request generated within the first time period is added to the first queue. As the controller processes the IO requests in the first queue one by one, the number of IO requests in the first queue gradually decreases until it is empty, thus ensuring the rapid start of the next task.

[0048] The following sections will describe further optional implementation methods for each of the above steps, as well as related terms.

[0049] In step 501, the processor starts timing when the first task is started.

[0050] In this embodiment, the processor is not limited to executing the information processing method described herein when starting any first task. The processor can execute the information processing method when starting any first task; the processor can also execute the information processing method when starting a specific task. For example, the specific task may be an application with high startup efficiency requirements, such as a game application, instant messaging application, video application, camera application, etc. Or, the specific task may be an application that takes a long time to start without the information processing method.

[0051] In step 502, the processor adds the first IO request belonging to the first task generated within the first time period to the first queue reserved by the controller; wherein the initial state of the first queue is an empty queue.

[0052] In some embodiments, the first duration is greater than or equal to the expected startup duration of the first task; thus, the first IO request includes all IO requests generated by the processor in executing the startup of the first task, which enables the processor to put as many IO requests generated during the startup of the first task as possible into the first queue, thereby enabling these IO requests to be processed with priority, thereby improving the startup speed of the first task.

[0053] The estimated startup time can be based on the average time taken for the first task to complete startup in previous attempts, or it can be based on the developer's experience-based settings.

[0054] In the embodiments of this application, the controller can be a first controller of the system-on-a-chip or a second controller of the storage device. In the case of the first controller, in some embodiments, step 502 can be implemented as follows: the processor adds the first IO request to a reserved third queue in RAM corresponding to the first queue; wherein the initial state of the third queue is an empty queue; the processor triggers the first controller to read the IO request in the third queue and add it to the first queue.

[0055] In the case of a second controller, the first controller actually reserves an empty queue (referred to as the fourth queue for convenience). In some embodiments, after the first I / O request is added to the fourth queue of the first controller, the first controller transmits the first I / O request from the fourth queue to the second controller. The second controller determines whether to add the request to the first queue based on the received first I / O request and the corresponding tag information. For example, the first controller has four queues, referred to as queues 0, 1, 2, and 3, where queues 0 and 1 are reserved by the first controller and are initially empty. Similarly, the second controller also has four queues, referred to as queues 0, 1, 2, and 3, where queues 0 and 1 are reserved by the first controller and are initially empty. The first controller, assuming it polls the I / O requests in each queue in the order of 0, 1, 2, and 3, can carry its corresponding queue identifier when transmitting these I / O requests. The second controller then places the corresponding I / O request into the queue that matches the queue identifier. For example, I / O requests from queue 0 can be placed into queue 0 of the second controller, and I / O requests from queue 1 can be placed into queue 1 of the second controller. Alternatively, other methods can be used to ensure that when the first I / O request is transmitted to the second controller, it is also placed into its reserved queue, which is initially empty, thereby further improving the processing efficiency of the first I / O request.

[0056] In some embodiments, if the third queue is full, or if the third queue is not full but the number of IO requests therein is greater than a first threshold, the first IO request is added to a queue in the RAM where the number of IO requests is less than a second threshold; wherein the second threshold is less than the first threshold.

[0057] Understandably, IO requests in the RAM queues are continuously transferred to the controller. Therefore, if the IO requests in the third RAM queue are full or exceed the first threshold, it indicates that the IO requests in the controller's first queue may also be full or have reached a certain number. Adding more first IO requests to the third queue at this point may not be efficient. Therefore, in the above embodiment, the first IO requests are added to other queues with less data. This improves the processing speed of these IO requests even when the reserved queue (i.e., the queue initially empty) is insufficient, thereby increasing the startup speed of the first task, which generates a large number of IO requests during startup.

[0058] In this embodiment, the size of the second threshold is not limited and can be arbitrary, but it cannot exceed the maximum storage capacity of the queue. For example, if the second threshold is 1, adding the first IO request to other empty queues can make these requests be polled first, thereby further improving the startup efficiency of the first task even when the reserved empty queues are insufficient.

[0059] In some embodiments, such as Figure 7 As shown, the method further includes: step 503, adding a second IO request belonging to the first task generated after the first duration to the second queue of the controller.

[0060] It's important to note that, unlike the first queue, the second queue is not a queue reserved by the controller. It could be a regular queue or a priority queue; there are no restrictions. After the first duration, for example, after 3 seconds, any second I / O requests belonging to the first task are added to the second queue. Even if there are already many other I / O requests in the second queue before they are added, it will not affect the startup speed of the first task. This is because the first task may have already started after the first duration, or even if it hasn't finished starting, the main data required for its startup may have already been loaded. Therefore, the processing efficiency of the second I / O requests generated after the first duration will not affect the startup speed of the first task, or its impact on the startup speed will be minimal.

[0061] Here, the method of adding the second IO request to the controller's second queue is similar to the implementation of step 502, so it will not be elaborated here.

[0062] It should be noted that, in this application, IO requests belonging to the first task generated within the first time period are referred to as first IO requests, and IO requests belonging to the first task generated after the first time period are referred to as second IO requests. The difference between "first" and "second" lies in the different time periods in which they are generated. IO requests "belonging to the first task" include, but are not limited to, IO requests generated due to the initiation of the first task, and IO requests generated in response to user interaction commands after the initiation of the first task is completed.

[0063] In this embodiment of the application, the number of the first queue reserved by the controller is not limited. It can be one queue or multiple queues. Correspondingly, the number of the third queue reserved in RAM is the same as the number of the first queue, and the two correspond to each other.

[0064] In multi-tasking scenarios, such as when the processor starts a second task while starting the first, to ensure the startup speed of the second task, in some embodiments, such as... Figure 8 As shown, the method further includes:

[0065] Step 801: The processor starts the second task and begins timing when the first task is started;

[0066] Step 802: The processor selects a target queue from multiple queues in RAM whose number of IO requests is less than a third threshold.

[0067] In this embodiment, the third threshold is less than the first threshold, and the third threshold is less than or equal to the second threshold. The third threshold can be 1 or a value greater than 1, specifically to meet the task startup speed. Understandably, in the scheme where the third threshold is less than 1, it is equivalent to selecting an empty queue from RAM as the target queue; thus, adding the third IO request corresponding to the second task to the target queue allows these third IO requests to receive priority processing. For the specific reason, please refer to the technical effect brought about by step 502 mentioned above.

[0068] Of course, if the number of I / O requests in the third queue reserved in RAM is less than the third threshold, third I / O requests belonging to the second task can also be added to this queue. In short, when the reserved third queue is insufficient, or when the number of I / O requests in the reserved third queue is greater than the first threshold, the processor can dynamically specify a "fast lane" (i.e., the target queue) to achieve rapid startup of the second task.

[0069] Step 803: The processor adds the third I / O request belonging to the second task generated within the second time period to the target queue;

[0070] Step 804: The processor triggers the controller to read the IO requests in the target queue and add them to the queue corresponding to the target queue.

[0071] Of course, similar to the way the processor handles I / O requests belonging to the first task, the processor can add fourth I / O requests belonging to the second task that are generated after the second duration to a non-target queue in RAM (including or excluding the third queue), and trigger the controller to read these requests from them and add them to the corresponding queue.

[0072] Understandably, adding the third IO request generated within the second time period to the target queue and adding the fourth IO request generated after the second time period to the non-target queue has a similar technical effect to steps 502 and 503. This ensures that more empty queues are reserved in RAM to cope with multi-task concurrency, thereby ensuring the startup speed of each task as much as possible when multiple tasks are concurrent.

[0073] Similarly, here, IO requests belonging to the second task generated within the second time period are referred to as third IO requests, and IO requests belonging to the second task generated after the second time period are referred to as fourth IO requests. The difference between "third" and "fourth" lies in the different time periods in which they are generated. IO requests "belonging to the second task" include, but are not limited to, IO requests generated due to the initiation of the second task, and IO requests generated in response to user interaction commands after the second task has been completed.

[0074] The second duration may be the same as or different from the first duration. In some embodiments, the second duration is greater than or equal to the expected startup duration of the second task. This expected startup duration may be based on the time taken to start the second task in previous attempts, such as using the average of the previous startup times as the second duration. Alternatively, the expected startup duration may be an empirical value configured by the developer.

[0075] It should be noted that in this application, the queues initially empty reserved by the controller (e.g., the first queue) and the queues initially empty reserved in RAM (e.g., the third queue) are figuratively referred to as "fast lanes." Of course, as... Figure 8 In the technical solution shown, the dynamically specified target queue can also be referred to as a "fast lane".

[0076] The following describes an exemplary application of the embodiments of this application in a real-world application scenario.

[0077] The information processing method provided in this application embodiment, namely the Key IO First (KIF) "fast track" method, can quickly process key IO requests with minimal changes to existing hardware controllers. This method is applicable to storage master controllers (an example of the first controller) and storage device controllers (an example of the second controller).

[0078] The KIF fast lane method has three key actions:

[0079] 1. Maintain one or more queues in the hardware queue. These queues are not used under normal circumstances and are called "fast lanes". When an urgent I / O request (I / O request) comes in, the "fast lane" is activated for transmission.

[0080] 2. The controller has priority in transmitting I / O requests in the "fast lane".

[0081] The KIF fast lane method requires that the controller has a large number of hardware queues, so that the method can reserve queues.

[0082] by Figure 9 For example, Figure 9 As shown, each column represents a queue. Queues in RAM are called software queues, while queues in the storage master controller and storage device controller are called hardware queues. The rectangles in the storage master controller and storage device controller represent reserved queues, also known as "fast lanes." Queues outside the "fast lanes" are ordinary I / O queues.

[0083] If an I / O request that needs to be processed quickly arrives, execute the following:

[0084] 1. If the "fast lane" is full, put the IO request into the normal queue; otherwise, put the IO request into the "fast lane" queue.

[0085] 2. After an IO request is enqueued, control is handed over to the controller.

[0086] The controller's behavior has been modified as follows:

[0087] 1. Complete the currently ongoing IO request and prepare to select the next IO request to be transmitted.

[0088] 2. Prioritize processing IO requests from the "fast lane". Once the IO requests in the "fast lane" are processed, then process the IO requests in the regular queue.

[0089] Advantages of the "fast lane":

[0090] 1. I / O requests in the "Fast Lane" have the highest priority, while I / O requests in other queues have equal low priority. Urgent I / O requests should use the "Fast Lane" first to avoid being frequently blocked by low-priority I / O requests;

[0091] 2. Suitable for scenarios where IO request priorities are relatively fixed;

[0092] 3. The controller is easy to implement.

[0093] In this application's embodiments, the focus is on improving the response speed and user experience of critical applications. For example, when a phone opens an application, the application's IO requests are sent to the fast lane, ensuring that the IO response requests of the currently new application have the highest priority. This indirectly improves the application's opening speed, preventing it from being affected by other IO requests during the opening process and enhancing the user experience.

[0094] In this embodiment, a high-priority IO queue, referred to as the "fast lane," is reserved in the storage controller. High-priority IO requests are given priority to use the "fast lane," thereby improving the request speed of critical IO requests. This method is suitable for emergency IO processing in certain scenarios.

[0095] This method is simple and universal, and can be applied to different storage controllers, including storage master controllers and storage device controllers. The controller only needs to make slight adjustments to the selection of IO requests.

[0096] Furthermore, only critical I / O requests are prioritized, while other I / O requests are not prioritized, maintaining the original design. This results in good compatibility.

[0097] In this application embodiment, a single "fast lane" or multiple "fast lanes" can be reserved.

[0098] In this embodiment of the application, a certain queue can be fixed as the "fast lane" or a certain queue can be dynamically designated as the "fast lane" to realize the switching of the "fast lane".

[0099] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps; or steps from different embodiments may be combined into a new technical solution.

[0100] Based on the foregoing embodiments, this application provides an information processing device, which includes various modules and units included in each module, and can be implemented by a processor; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), microprocessor (MPU), digital signal processor (DSP) or field programmable gate array (FPGA), etc.

[0101] Figure 10 A schematic diagram of the structure of the information processing device according to an embodiment of this application is shown below. Figure 10 As shown, the device 10 includes:

[0102] The first timing module 1001 is used to start timing when the first task is started;

[0103] The addition module 1002 is used to add the first IO request belonging to the first task generated within the first time period to the first queue reserved by the controller. The initial state of the first queue is an empty queue, so that the controller can prioritize the processing of IO requests in the first queue.

[0104] In some embodiments, the adding module 1002 is further configured to: add a second IO request belonging to the first task generated after the first duration to the second queue of the controller.

[0105] In some embodiments, the adding module 1002 is configured to: add the first IO request to a reserved third queue in RAM corresponding to the first queue; wherein the initial state of the third queue is an empty queue; and trigger the controller to read the IO request in the third queue and add it to the first queue.

[0106] In some embodiments, the adding module 1002 is further configured to: add the first IO request to a queue in RAM where the number of IO requests is less than a second threshold when the third queue is full, or when the third queue is not full but the number of IO requests therein is greater than a first threshold; wherein the second threshold is less than the first threshold.

[0107] In some embodiments, the information processing device 100 further includes: a startup module for starting a second task when starting a first task; a second timing module for starting a timer when starting the second task; a selection module for selecting a target queue from a plurality of queues in RAM where the number of IO requests is less than a third threshold; an addition module 1002 for adding third IO requests belonging to the second task generated within a second duration to the target queue; and a trigger module for triggering the controller to read the IO requests in the target queue and add them to the queue corresponding to the target queue.

[0108] In some embodiments, the first duration is greater than or equal to the expected startup duration of the first task.

[0109] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0110] It should be noted that, in the embodiments of this application... Figure 10 The module division of the information processing device shown is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or have two or more units integrated into one unit. The integrated units can be implemented in hardware, as software functional units, or a combination of both.

[0111] It should be noted that, in the embodiments of this application, if the above-described methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0112] For example, it can be implemented in a system-on-a-chip. Figure 11 This is a schematic diagram of the structure of an on-chip system according to an embodiment of this application, such as... Figure 11 As shown, the system-on-a-chip 110 includes a processor 1101, RAM 1102, and a first controller 1103; wherein,

[0113] Processor 1101 is configured to start timing when starting the first task; and to add a first I / O request belonging to the first task generated within a first duration to a reserved third queue in RAM 1102; wherein the initial state of the third queue is an empty queue;

[0114] The processor 1101 is also configured to trigger the first controller 1103 to add the IO requests in the third queue to the first queue reserved by the first controller 1103; wherein the initial state of the first queue is an empty queue, so that the first controller 1103 can prioritize the processing of IO requests in the first queue;

[0115] The first controller 1103 is used to read IO requests from the third queue and add them to the first queue.

[0116] The descriptions of the above hardware-software combined embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the hardware-software combined embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0117] This application provides an electronic device. Figure 12 This is a schematic diagram of the hardware entity of the electronic device according to an embodiment of this application, such as... Figure 12 As shown, the electronic device 120 includes a memory 1201 and a processor 1202. The memory 1201 stores a computer program that can run on the processor 1202. When the processor 1202 executes the program, it implements the steps in the method provided in the above embodiments.

[0118] This application does not limit the type of electronic device; it can be of various kinds. For example, the electronic device can be a mobile phone, tablet computer, smartwatch, laptop computer, television, or projector, among other types of devices.

[0119] It should be noted that the memory 1201 is configured to store instructions and applications executable by the processor 1202, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data and video communication data) in the processor 1202 and the various modules in the electronic device 120. It can be implemented by flash memory or random access memory (RAM).

[0120] This application provides a processor that executes the steps of the information processing method described in this application when executing a program.

[0121] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method provided in the above embodiments.

[0122] This application provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the method provided in the above-described method embodiments.

[0123] It should be noted that the descriptions of the storage medium and device embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium, storage medium, and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0124] It should be understood that the phrases "one embodiment," "an embodiment," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be repeated here.

[0125] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0126] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0127] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0128] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules. They may be located in one place or distributed across multiple network units. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0129] In addition, each functional module in the various embodiments of this application can be integrated into one processing unit, or each module can be a separate unit, or two or more modules can be integrated into one unit; the integrated modules can be implemented in hardware or in the form of hardware plus software functional units.

[0130] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0131] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0132] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0133] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0134] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0135] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An information processing method, characterized in that, The method includes: Start timing when the first task is initiated; and The first input / output (I / O) request generated within the first time period belonging to the first task is added to the third queue reserved in the random access memory (RAM); the third queue corresponds to the first queue reserved by the controller. The third queue is initially an empty queue. The controller is triggered to read the IO requests in the third queue and add them to the first queue. The first queue is initially empty, so that the controller can prioritize processing the IO requests in the first queue. The number of the third queue is equal to the number of the first queue. If the third queue is full, or if the third queue is not full but the number of IO requests therein is greater than a first threshold, the first input / output IO request is added to a queue in RAM where the number of IO requests is less than a second threshold; wherein the second threshold is less than the first threshold. The second I / O request belonging to the first task generated after the first duration will be added to the second queue of the controller; the second queue is a queue other than the queue reserved by the controller.

2. The method according to claim 1, characterized in that, The method further includes: Start the second task and begin timing when the first task starts; and Select the target queue from multiple queues in RAM whose number of IO requests is less than the third threshold; The third I / O request belonging to the second task generated within the second time period is added to the target queue; The controller is triggered to read the IO requests in the target queue and add them to the queue corresponding to the target queue.

3. The method according to claim 1 or 2, characterized in that, The first duration is greater than or equal to the expected startup duration of the first task.

4. A processor, characterized in that, When the processor executes the program, it implements the method described in any one of claims 1 to 3.

5. A system-on-a-chip, characterized in that, include: Processor, RAM, and first controller; among which, The processor is configured to start timing when the first task is started; and to add a first I / O request belonging to the first task generated within a first duration to a third queue reserved in RAM; wherein the initial state of the third queue is an empty queue; The processor is further configured to trigger the first controller to add the IO requests in the third queue to the first queue reserved by the first controller; wherein the initial state of the first queue is an empty queue, thereby enabling the first controller to prioritize the processing of IO requests in the first queue; the number of the third queue is equal to the number of the first queue; The processor is further configured to add the first IO request to a queue in the RAM where the number of IO requests is less than a second threshold, either when the third queue is full or when the third queue is not full but the number of IO requests therein is greater than a first threshold; wherein the second threshold is less than the first threshold. The first controller is used to read IO requests from the third queue and add them to the first queue; The on-chip system is configured to add a second I / O request belonging to the first task generated after the first duration to a second queue of the controller; the second queue is a queue other than the queue reserved by the controller.

6. An information processing device, characterized in that, include: The first timing module is used to start timing when the first task is started; An adding module is used to add first input / output (I / O) requests belonging to the first task generated within a first time period to a third queue reserved in random access memory (RAM); wherein, the third queue corresponds to a first queue reserved by the controller; the initial state of the third queue is an empty queue; the controller is triggered to read the I / O requests in the third queue and add them to the first queue, the initial state of the first queue is an empty queue, so that the controller can prioritize processing the I / O requests in the first queue; the number of the third queue is equal to the number of the first queue; The adding module is further configured to add the first input / output IO request to a queue in RAM where the number of IO requests is less than a second threshold when the third queue is full, or when the third queue is not full but the number of IO requests therein is greater than a first threshold; wherein the second threshold is less than the first threshold. The adding module is further configured to add a second IO request belonging to the first task generated after the first duration to the second queue of the controller; the second queue is a queue other than the queue reserved by the controller.

7. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 3.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 3.

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