A chip layout method, device, equipment and storage medium

Abstract

Embodiments of the present application provide a chip layout method, device, equipment and storage medium, the method comprises: obtaining the target array corresponding to the original circuit data set containing network class and node class; according to the target array, in combination with the set graph neural network model, determine the initial position information of chip layout;According to the initial position information and the pre-set layout tool, determine the layout result of the chip. By using the method, the data information obtained by screening and processing in the array corresponding to the original circuit data set is input into the graph neural network model to divide and adjust the initial position of the module on the chip, and the initial position information of the chip layout is obtained. Unlike the zero initialization or random initialization of the module in the prior art, the present scheme can reduce the number of iterations in the chip layout process, faster convergence is achieved, and the efficiency of chip layout optimization is realized.

Description

Technical Field

[0001] This invention relates to the field of chip layout technology, and in particular to a chip layout method, apparatus, device and storage medium. Background Technology

[0002] Chip placement primarily refers to the process of determining the location of each unit or module in a chip under design on a circuit board. Chip placement is one of the key steps in Electronic Design Automation (EDA). With the rapid development of integrated circuits, the scale of chip placement is growing exponentially, making the optimization of existing EDA placement methods increasingly urgent. Accelerated placement will inevitably save more time and labor costs.

[0003] Similar to the neural network training process, the chip layout problem is solved analytically. The chip layout can be regarded as an analytical nonlinear optimization problem. That is to say, the goal of chip layout is to determine the final position of each module based on the initial layout through iteration, under the constraints of the line length non-crossing strategy and the module non-overlapping strategy.

[0004] Current methods typically initialize modules to zero or randomly. Even with pruning operations such as no overlapping modules and no crossovers between pins, this still leads to problems such as a large number of iterations, long iteration cycles, and high computational load, resulting in wasted costs. Summary of the Invention

[0005] This invention provides a chip layout method, apparatus, device, and storage medium, which achieves high efficiency in chip layout optimization by finding the optimal initial layout and reducing the number of iterations during the chip layout process.

[0006] In a first aspect, embodiments of the present invention provide a chip layout method, including:

[0007] Obtain the target array containing network classes and node classes corresponding to the original circuit dataset;

[0008] Based on the target array and the established graph neural network model, the initial position information of the chip layout is determined.

[0009] The layout result of the chip is determined based on the initial position information and the pre-given layout tool.

[0010] In a second aspect, embodiments of the present invention provide a chip layout apparatus, comprising:

[0011] The array acquisition module is used to obtain the target array containing network classes and node classes corresponding to the original circuit dataset;

[0012] The position determination module is used to determine the initial position information of the chip layout based on the target array and a set graph neural network model.

[0013] The result determination module is used to determine the layout result of the chip based on the initial position information and a pre-given layout tool.

[0014] Thirdly, embodiments of the present invention also provide an electronic device, comprising:

[0015] One or more processors;

[0016] Memory, used to store one or more programs;

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement and execute the chip layout method provided in the first aspect embodiment.

[0018] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the chip layout method as described in the first aspect embodiment.

[0019] This invention provides a chip layout method, apparatus, device, and storage medium. The method includes: obtaining a target array containing network classes and node classes corresponding to an original circuit dataset; determining initial position information for chip layout based on the target array and a pre-defined graph neural network model; and determining the chip layout result based on the initial position information and a pre-given layout tool. Using this method, filtered and processed data information is obtained by mapping data information in the original circuit dataset to arrays of network classes and node classes. This data information is then input into a graph neural network model to perform initial position partitioning of modules on the chip, thereby obtaining the initial position information for chip layout. Unlike existing technologies where module initial positions are set to zero or randomly initialized, this technical solution achieves faster convergence by finding the optimal initial layout, reducing the number of iterations during chip layout and realizing high efficiency in chip layout optimization.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating a chip layout method provided in Embodiment 1 of the present invention;

[0023] Figure 1a This is an example diagram illustrating the initialization position information of the chip layout in a chip layout method provided in Embodiment 1 of the present invention;

[0024] Figure 2 This is a flowchart illustrating another chip layout method provided in Embodiment 2 of the present invention;

[0025] Figure 3 This is a schematic diagram of a chip layout device provided in Embodiment 3 of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "original," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Example 1

[0030] Figure 1This is a flowchart illustrating a chip placement method according to Embodiment 1 of the present invention. This method is applicable to chip placement and can be executed by a chip placement device. This device can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the chip layout method provided in this embodiment can specifically include the following steps:

[0031] S110. Obtain the target array containing network class and node class corresponding to the original circuit dataset.

[0032] The original circuit dataset can be understood as a data file containing various circuit diagrams, such as circuit diagram netlist files, circuit diagram module attribute files, circuit diagram Verilog (a hardware description language for representing logic circuit diagrams) files, circuit diagram description files, etc. This embodiment does not impose specific restrictions on the form of the original dataset; it can be any data file related to the circuit diagram, used to represent various attribute information of the modules. In this embodiment, the network class (net class) can be specifically understood as a collection of modules with connection information, mapping the connection information of the node class (node ​​class) extracted from the circuit dataset. The node class can be understood as module information, mapping the size information and pin information extracted from the circuit dataset. For example, if implementing a certain function requires the joint implementation of modules 1, 2, and 3, then modules 1, 2, and 3 can be mapped to a network class, with modules 1, 2, and 3 respectively understood as nodes, and the attribute information of each module mapped to the node class.

[0033] In this embodiment, the target array containing network classes and node classes can be understood as a structure that maps the original circuit dataset to node classes containing module information and network classes containing module connection relationships. By calling the data in the target array, the attribute information of the modules and their connection relationships can be obtained. In this embodiment, the initial position information for chip layout is determined based on the target array mapped to network classes and node classes. Specifically, the target array containing network classes and node classes corresponding to the initial circuit dataset is obtained.

[0034] S120. Based on the target array and the set graph neural network model, determine the initial position information of the chip layout.

[0035] In existing technologies, chip placement involves initializing each module on the chip to zero or randomly. Even with pruning operations such as avoiding overlapping modules and ensuring pin connections don't cross, this still results in a large number of iterations and significant time costs. To address this issue, this embodiment uses a target array containing network and node classes, combined with a graph neural network, to first determine the initial chip layout. Then, based on this initial layout, the final layout of each module on the chip is further determined.

[0036] This step is used to determine the initial layout of the chip based on the target array and a graph neural network model. In this embodiment, after obtaining the target array containing network classes and node classes, the data in the target array is first feature-encoded using a graph neural network model to obtain feature-encoded information. The initial position information for the chip layout is then determined based on this feature-encoded information. First, the number of connections in each network class needs to be totaled. This can be understood as simply retrieving the connection information of the node classes within each network class to obtain the statistical results.

[0037] It should be noted that in this embodiment, the chip initialization layout involves placing network classes with strong interconnections together, and the initial position of each network class group needs to be determined. In this embodiment, network classes with strong interconnections can be grouped into network class groups. In this embodiment, the layout is regarded as an N*N two-dimensional matrix, where the size of N is related to the number of node classes to ensure that each node class is placed.

[0038] In this embodiment, based on the target array containing network classes and node classes, network classes with strong connections are preferentially identified. A strong connection refers to a large number of connections between network classes, while a weak connection refers to a small number of connections between them. Strong connections are relative to weak connections, and their definitions can be determined based on practical experience data. Alternatively, a relevant function can be used to make the network class partitioning exhibit a normal distribution, with the left half of the normal distribution curve representing weak connections and the right half representing strong connections. For example, it is assumed that three or more connections between network classes constitute a strong connection, and fewer than three connections between network classes constitute a weak connection.

[0039] Specifically, based on the feature encoding information of the network classes and node classes obtained above, the network classes are reasonably divided into regions. For ease of differentiation, in this embodiment, the label of the network class is set to its number; for example, net0 has a label of 0. When dividing the network classes into regions, the label classification function of the graph neural network model is used, along with multi-classification functionality. It is important to know that a pre-trained graph neural network model is used to determine network classes with strong connectivity relationships. The steps for determining network classes with strong connectivity relationships can be described as follows: inputting the feature encoding information into the pre-trained graph neural network model to obtain network classes with strong connectivity relationships. Then, network classes with strong connectivity relationships are grouped into the same region. Here, a region can be understood as different areas into which the chip layout is divided. It should be noted that the division method is not specifically limited; network classes with strong connectivity relationships can be placed in any region, as long as different groups of network classes with strong connectivity relationships are placed in different regions.

[0040] It is clear that graph neural network models that define strong connections can be obtained through training on a large amount of training sample data. The process involves: constructing an initial graph neural network model; training the graph neural network model using the training sample data; updating the parameters of the graph neural network model; and obtaining the trained graph neural network model after the training iteration ends, provided the conditions for completion are met. For example, the activation function in the graph neural network model can be the sigmoid function, and the loss function can be the cross-entropy function.

[0041] Continuing from the above description, after identifying network classes with strong connections and grouping them into the same region, the positions of the regions need further adjustment to minimize the bus length of the connections between regions. In this embodiment, the final position of each region is determined based on the positional relationships between them. It's important to understand that the connections between regions can be determined based on the weak connections between network classes. Network classes with strong connections are grouped into the same region, while network classes with weak connections represent the connections between regions. First, it's necessary to statistically analyze the connections between network classes in each region and network classes in other regions. The graph neural network model is trained by analyzing the positional and connection relationships between regions. In this step, the length of the connections between regions is used as a weight. When the bus length of the connections between regions is minimized, it can be understood that each region is in a reasonable position, that is, the optimal initial position of each region, which is recorded as the initial position information of the chip layout.

[0042] To more clearly illustrate the region division in the chip layout of this embodiment of the invention, exemplarily, Figure 1a This is an example diagram illustrating the initialization position information of the chip layout in a chip layout method provided in Embodiment 1 of the present invention. Figure 1aAs shown, the chip layout is considered as a 9×9 matrix, dividing the chip into 9 regions, each with corresponding coordinates, represented as (3,3), (3,6), (3,9), (6,3), (6,6), (6,9), (9,3), (9,6), and (9,9). Each region contains network classes with strong interconnections. Assuming initial position information has been determined, for example, region (3,3) contains Net0, Net1, ..., region (3,6) contains Net29 and Net30, and region (6,3) contains Net8 and Net9. These are not listed individually here, nor are they shown in the diagram.

[0043] S130. Determine the chip layout result based on the initial position information and the pre-given layout tool.

[0044] The pre-defined layout tool can be understood as an EDA layout tool. In this embodiment, no specific restrictions are placed on the EDA layout tool used. It is important to note that before inputting the results of the graph neural network training into the EDA layout tool, the input data needs to be processed to adapt to the EDA layout tool's input data format. Furthermore, after obtaining the data file adapted to the EDA layout tool's input data format, the data file is input into the layout tool to achieve the final chip layout result.

[0045] This invention provides a chip placement method. The method first obtains a target array containing network classes and node classes corresponding to the original circuit dataset. Then, based on the target array and a pre-defined graph neural network model, the initial position information for chip placement is determined. Finally, based on the initial position information and a pre-given placement tool, the chip placement result is determined. Using this method, filtered and processed data information is obtained by mapping the data information in the original circuit dataset to arrays of network classes and node classes. This data information is then input into a graph neural network model to perform initial position partitioning of modules on the chip, thus obtaining the initial position information for chip placement. Unlike existing technologies where the initial position of modules is set to zero or randomly initialized, this technical solution achieves faster convergence by finding the optimal initial placement, reducing the number of iterations during chip placement and realizing high efficiency in chip placement optimization.

[0046] As an optional embodiment of the present invention, based on the above embodiments, before obtaining the target array containing network classes and node classes corresponding to the original circuit dataset, the method further includes: preprocessing the original circuit dataset to determine the target array containing network classes and node classes corresponding to the original circuit dataset.

[0047] In this optional embodiment, before obtaining the target array containing network and node classes corresponding to the original circuit dataset, the original circuit dataset needs to be preprocessed to obtain the target array containing network and node classes. Specifically, by preprocessing the original circuit dataset, feature filtering and processing are performed on data such as module attributes, pin offsets, and connection information in the circuit dataset.

[0048] Furthermore, the original circuit dataset is preprocessed to determine the target array corresponding to the original circuit dataset, which includes network classes and node classes. This includes: extracting first data information and second data information from the original circuit dataset. The first data information includes the pin connection information of the module on the chip, and the second data information includes the size information and pin information of the module on the chip. The set of first data information is used to form a network class. The set of second data information is used to form a node class. The target array is constructed based on the network class and the node class.

[0049] Specifically, the size information of the modules, the pin offset information of the modules, and the pin connection information between the modules are extracted from the original circuit dataset and mapped to the structures of the net and node classes, denoted as the target array in this embodiment. In this embodiment, the pin connection information of the modules on the chip is denoted as the first data information, and the size information and pin information of the modules on the chip are denoted as the second data information. The net class can be understood as a set of modules with connection information, mapping the connection information of the node class extracted from the circuit dataset. The node class can be understood as the information of the modules, mapping the size information and pin information extracted from the circuit dataset. The network class is determined based on the set of the first data information, the node class is determined based on the set of the second data information, and the target array is constructed based on the network class and the node class.

[0050] This optional embodiment specifies how to preprocess the original circuit dataset to determine the target array containing network and node classes corresponding to the original circuit dataset. By defining the network and node classes, the data in the original circuit dataset is filtered and processed, so that when the subsequent chip layout process needs to obtain data, it is only necessary to call the network and node classes to obtain relevant information, making subsequent data use simple, fast, and efficient.

[0051] Example 2

[0052] Figure 2This is a flowchart illustrating another chip layout method provided in Embodiment 2 of the present invention. This embodiment is a further optimization of the above embodiment. In this embodiment, the step of "determining the initial position information of the chip layout based on the target array and a set graph neural network model" is further optimized to encode the information contained in the target array to obtain the feature encoding information corresponding to the target array; inputting the feature encoding information into a pre-trained first graph neural network model to determine the network class groups with strong connections in the network class; dividing each network class group into each partition of the chip layout matrix; and training a set second graph neural network model based on the connection relationship between each network class and the position relationship of each partition to determine the initial position information of the chip layout.

[0053] Furthermore, the phrase "determine the layout result of the chip based on the initial position information and the pre-given layout tool" is further optimized to: determine the standard data format corresponding to the pre-given layout tool; based on the standard data format, call the corresponding information from the network class and node class of the target array to determine the adaptation data file corresponding to each module in the initial position information; input the adaptation data file into the layout tool to determine the layout result of the chip.

[0054] like Figure 2 As shown, this embodiment two provides a chip layout method, which specifically includes the following steps:

[0055] S210. Obtain the target array containing network class and node class corresponding to the original circuit dataset.

[0056] S220. Encode the information contained in the target array to obtain the feature encoding information corresponding to the target array.

[0057] Specifically, the information contained in the target array, namely the information corresponding to the network class and node class, is encoded to obtain the feature encoding information corresponding to the target array. One encoding method is to input the information in the target array into the graph neural network model for feature encoding processing to obtain the feature encoding information corresponding to the target array.

[0058] S230. Input the feature encoding information into the pre-trained first graph neural network model to determine the network class group with strong connection relationship in the network class.

[0059] In this embodiment, the pre-trained first graph neural network model performs label classification. This can also be understood as obtaining network classes with strong connections based on this first graph neural network model. Specifically, feature encoding information is input into the first graph neural network model to determine the network classes with strong connections, and these are denoted as network class groups. It should be noted that there can be two or more network classes with strong connections; no specific limitation is made here.

[0060] S240. Divide each network class group into the respective partitions of the chip's layout matrix.

[0061] In this context, the chip can be viewed as a single region, and chip layout can be understood as dividing this region into different areas, resulting in partitions. Specifically, network classes, i.e., network classes with strong interconnections, are grouped into the same partition. Different network classes are then assigned to different partitions within the chip's layout matrix.

[0062] S250. Based on the connection relationships between each network class and the positional relationships of each partition, the set second neural network model is trained to determine the initial positional information of the chip layout.

[0063] Specifically, by statistically analyzing the connections between network classes and identifying the network classes with strong connections as determined in the previous steps, network classes with weak connections can be further identified. These weakly connected network classes can be considered as connections between network classes in each partition and network classes in other partitions. The second neural network model is trained based on these weak connections and the positional relationships of each partition. The length of the connections between partitions is used as the weights. By training the second neural network model, the length of the connections between partitions is minimized, thus obtaining the optimal position for each partition. This can be considered the optimal initial position, i.e., the initial positional information for the chip layout. For example, assuming the position markers for net0 and net1 are the center position (3, 3) of zone 1, through the partition position adjustment in this step, the zones of net0 and net1, etc., change from zone 1 to zone 3, and the positional information becomes (3, 9).

[0064] It should be noted that, considering the original circuit dataset may correspond to a large number of network classes, dividing each network class into a region and training it to its optimal position using the connection and positional relationships of each network class, combined with a graph neural network model, could lead to long training cycles and high computational costs due to the large number of network classes. In this embodiment, network classes with strong connections are first divided into a region, and then the graph neural network model is trained based on the connection and positional relationships of the region. This allows for the layout of each region, resulting in shorter training cycles and lower computational costs. Furthermore, combining this with a layout tool for chip placement can significantly reduce the number of iterations, achieve faster convergence, and realize the high efficiency of this invention for layout optimization.

[0065] Furthermore, based on the connection relationships between network classes and the positional relationships of each partition, the established second-graph neural network model is trained to determine the initial positional information of the chip layout, including:

[0066] a1. Determine the connection relationships between different network classes.

[0067] Specifically, the connection relationships between network classes can be statistically analyzed by using a target array containing network classes and node classes.

[0068] b1. Determine the connection relationships between each partition based on the connection relationships and strong connection relationships.

[0069] Specifically, based on the connection relationships between network classes and the network classes with strong connections identified in the previous steps, network classes with weak connections are determined. Since network classes with weak connections are not assigned to a single partition, the weak connections between network classes represent the connection relationships between their respective partitions. Among the network classes with connections, excluding those with strong connections, the remaining connections can be considered as having weak connections, and these weak connections are further used as the connection relationships between partitions.

[0070] c1. Train the second neural network model based on the connection relationships between the partitions and the positional relationships between the partitions.

[0071] Specifically, after determining the connection relationships between each partition, the line length between the connected partitions can be determined based on their positional relationships. The line length is then used as a weight, and the neural network model in the second graph is trained by adjusting the positional relationships of the partitions.

[0072] d1. When the connection length between each partition of the chip is the shortest, determine the initial position information of the chip layout.

[0073] Specifically, by training the second neural network model, when the length of the connection between each partition in the chip layout is the shortest, the layout method is determined as the optimal initial position and recorded as the initial position information of the chip layout.

[0074] S260. Determine the standard data format corresponding to the layout tool based on the pre-given layout tool.

[0075] Placement tools have defined standard data formats. When chip placement is required, the corresponding data format is needed to perform the placement based on the tool. Specifically, the standard data format corresponding to the placement tool is determined based on the pre-defined placement task. For example, suppose the standard data files required by the placement tool are module information files, pin connection files, etc.

[0076] S270. According to the standard data format, call the corresponding information from the network class and node class of the target array to determine the adaptation data file corresponding to each module in the initial position information.

[0077] Specifically, based on the standard data format, corresponding information is retrieved from the network and node classes to construct the corresponding standard data format adaptation data file. Continuing with the example above, if we assume that the standard data files required by the layout tool are module information files, pin connection files, etc., then relevant information needs to be retrieved from the network and node classes, and this information needs to be divided into module information files, pin connection files, etc. By calling these two classes, the adaptation standard data format can be processed relatively simply.

[0078] S280. Input the adaptation data file into the layout tool to determine the chip layout result.

[0079] Specifically, the adaptation data file is input into the layout tool to determine the chip layout result. The chip layout result can be understood as the layout and connection of each module on the chip.

[0080] The above technical solution specifies the steps for determining the initial position information of the chip layout based on the target array and a set graph neural network model, and the steps for determining the chip layout result based on the initial position information and a pre-given layout tool. Using this method, the original circuit dataset is first processed and mapped into a target array of network classes and node classes. The target array is then encoded to obtain feature encoding information, which is input into a graph neural network model. One graph neural network model divides the node classes into reasonable regions, and another graph neural network model optimizes the positional relationships between these regions to obtain the optimal position information for each partition. Based on this position information, the layout tool is then used to determine the chip layout result. Unlike existing technologies that initialize positions to zero or randomly, requiring multiple iterations to determine the chip layout result, this technical solution first identifies strongly correlated network classes based on a graph neural network model and assigns them to the same partition. Then, it determines the connection relationships between partitions based on weakly correlated network classes. The graph neural network model is trained based on the positional relationships and connection relationships between partitions to determine the optimal initialization position information for chip layout. By performing chip layout based on the optimal initialization position information, a large number of iterations can be avoided during chip layout, reducing the number of iterations and achieving faster convergence, thus making chip layout optimization highly efficient.

[0081] As an optional embodiment of the present invention, the training steps of the first neural network model in the above optional embodiment can be specifically described as follows:

[0082] a2. Construct the initial graph neural network model.

[0083] Specifically, the initial graph neural network model is constructed. For example, the sigmoid activation function is chosen for training because this function can make the network class division present a normal distribution. The cross-entropy function is generally chosen as the classification loss function, and the number of network layers M is generally set to 2 layers, etc.

[0084] b2. Train the graph neural network model based on the training sample data, where the training sample data includes feature encoding information samples and corresponding labeled classification results.

[0085] Specifically, the graph neural network model is trained using training sample data. Feature-encoded information samples are input into the graph neural network model to obtain the input result, i.e., the classification result. The loss function value is then calculated by comparing the classification result with the labeled classification results in the training sample data.

[0086] c2. Update the parameters of the graph neural network model based on the loss function value after training.

[0087] Specifically, the classification results obtained from the graph neural network model are compared with the labeled classification results in the training sample data, and a loss function is calculated to determine the value. The parameters of the graph neural network model are then updated based on the loss function value. In other words, before the training iteration conditions are met, the parameters of the graph neural network model are continuously updated based on each loss function value.

[0088] d2. After the training iteration ends, the trained graph neural network model is used as the first graph neural network model.

[0089] The completion of the training iteration can be understood as the loss function value reaching or not exceeding a set threshold. Specifically, once the completion of the training iteration is met, the trained graph neural network model is used as the first graph neural network model to determine the network classes with strong interconnections.

[0090] This embodiment specifies the training steps of the first graph neural network model. The initially constructed graph neural network model is trained based on training sample data to obtain the trained graph neural network model, which is used to determine the network classes with strong connections, thereby achieving rapid partitioning of network classes with strong connections.

[0091] Example 3

[0092] Figure 3 This is a schematic diagram of a chip placement device according to Embodiment 3 of the present invention. This device is applicable to chip placement and can be configured in electronic devices, such as… Figure 3 As shown, the device includes: an array acquisition module 31, a position determination module 32, and a result determination module 33; wherein,

[0093] The array acquisition module 31 is used to acquire the target array containing network classes and node classes corresponding to the original circuit dataset;

[0094] The position determination module 32 is used to determine the initial position information of the chip layout based on the target array and the set graph neural network model.

[0095] The result determination module 33 is used to determine the chip layout result based on the initial position information and the pre-given layout tool.

[0096] This invention provides a chip placement apparatus. First, a target array containing network classes and node classes corresponding to the original circuit dataset is obtained. Then, based on the target array and a pre-defined graph neural network model, the initial position information for chip placement is determined. Finally, based on the initial position information and a pre-given placement tool, the chip placement result is determined. Using this method, filtered and processed data information is obtained by mapping the data information in the original circuit dataset to arrays of network classes and node classes. This data information is then input into a graph neural network model to divide the initial positions of modules on the chip, thus obtaining the initial position information for chip placement. Unlike existing technologies where the initial positions of modules are set to zero or randomly initialized, this technical solution achieves faster convergence by finding the optimal initial placement, reducing the number of iterations during chip placement and realizing high efficiency in chip placement optimization.

[0097] Optionally, the device also includes an array determination module for:

[0098] The original circuit dataset is preprocessed to determine the target array containing network and node classes corresponding to the original circuit dataset.

[0099] Optionally, the array determination module is specifically used for:

[0100] Extract the first data information and the second data information from the original circuit dataset. The first data information includes the pin connection information of the module on the chip, and the second data information includes the size information and pin information of the module on the chip.

[0101] The collection of the first data information forms a network class;

[0102] The collection of second data information is used to form node classes;

[0103] Construct a target array based on network and node classes.

[0104] Optionally, the location determination module 32 may include:

[0105] The encoding determination unit is used to encode the information contained in the target array to obtain the feature encoding information corresponding to the target array;

[0106] The network group determination unit is used to input feature encoding information into a pre-trained first graph neural network model to determine network groups with strong connection relationships in the network group;

[0107] The partitioning unit is used to divide each network class group into different partitions of the chip's layout matrix;

[0108] The position determination unit is used to train the set second graph neural network model based on the connection relationship between each network class and the position relationship of each partition, so as to determine the initial position information of the chip layout.

[0109] Optionally, the location determination module 32 also includes a training unit for:

[0110] Construct the initial graph neural network model;

[0111] The graph neural network model is trained based on the training sample data, which includes feature-encoded information samples and corresponding labeled classification results.

[0112] Update the parameters of the graph neural network model based on the loss function values ​​after training;

[0113] After the training iteration ends, the trained graph neural network model is used as the first graph neural network model.

[0114] Optional, the position determination unit is specifically used for:

[0115] Determine the connection relationships between different network classes;

[0116] Determine the connection relationships between each partition based on the connection relationships and strong connection relationships;

[0117] The second graph neural network model is trained based on the connection relationships between the partitions and the positional relationships between the partitions.

[0118] When the connection length between the chip's partitions is minimized, the initial position information of the chip layout is determined.

[0119] Optional, the result determination module 33 is specifically used for:

[0120] Based on the pre-given layout tool, determine the standard data format corresponding to the layout tool;

[0121] Based on the standard data format, the corresponding information is retrieved from the network class and node class of the target array to determine the adaptation data file corresponding to each module in the initial position information;

[0122] Input the adaptation data file into the layout tool to determine the chip layout result.

[0123] The chip layout apparatus provided in the embodiments of the present invention can execute the chip layout method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method.

[0124] Example 4

[0125] Figure 4This is a schematic diagram of an electronic device according to Embodiment 4 of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0126] like Figure 4 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded into the RAM 43 from storage unit 48. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0127] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0128] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as chip layout methods.

[0129] In some embodiments, the chip layout method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the chip layout method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to perform the chip layout method by any other suitable means (e.g., by means of firmware).

[0130] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0131] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0132] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0133] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0134] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0135] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0136] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0137] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip layout method, characterized in that, include: Obtain the target array containing network classes and node classes corresponding to the original circuit dataset; Based on the target array and the established graph neural network model, the initial position information of the chip layout is determined. Based on the initial position information and the pre-given layout tool, the chip layout result is determined; Before obtaining the target array containing network and node classes corresponding to the original circuit dataset, the following steps are also included: Preprocess the original circuit dataset to determine the target array containing network classes and node classes corresponding to the original circuit dataset; The step of preprocessing the original circuit dataset to determine the target array containing network classes and node classes corresponding to the original circuit dataset includes: Extract the first data information and the second data information from the original circuit dataset. The first data information includes the pin connection information of the module on the chip, and the second data information includes the size information and pin information of the module on the chip. The collection of the first data information is used to form a network class; The collection of the second data information is used to form a node class; The target array is constructed based on the network class and the node class; The step of determining the initial position information of the chip layout based on the target array and a set graph neural network model includes: The information contained in the target array is encoded to obtain the feature encoding information corresponding to the target array; The feature encoding information is input into a pre-trained first graph neural network model to determine the network class groups with strong connection relationships in the network class; Each of the aforementioned network groups is assigned to a partition of the chip's layout matrix; Based on the connection relationships between the network classes and the positional relationships of the partitions, the established second graph neural network model is trained to determine the initial positional information of the chip layout.

2. The method according to claim 1, characterized in that, The training steps for the first neural network model include: Construct the initial graph neural network model; The graph neural network model is trained based on the training sample data, wherein the training sample data includes feature encoding information samples and corresponding labeled classification results; The parameters of the graph neural network model are updated based on the trained loss function values; After the training iteration ends, the trained graph neural network model is used as the first graph neural network model.

3. The method according to claim 1, characterized in that, The step of training the set second graph neural network model based on the connection relationships between the network classes and the positional relationships of the partitions to determine the initial positional information of the chip layout includes: Determine the connection relationships between the various network classes; Based on the connection relationships and the strong connection relationships, the connection relationships between each of the partitions are determined; The second graph neural network model is trained based on the connection relationships between the partitions and the positional relationships of the partitions. When the length of the connection between the partitions of the chip is the shortest, the initial position information of the chip layout is determined.

4. The method according to claim 1, characterized in that, The step of determining the chip layout result based on the initial position information and a pre-given layout tool includes: Based on a pre-given layout tool, determine the standard data format corresponding to the layout tool; According to the standard data format, the corresponding information is retrieved from the network class and node class of the target array to determine the adaptation data file corresponding to each module in the initial position information; The adaptation data file is input into the layout tool to determine the chip layout result.

5. A chip placement apparatus, characterized in that, include: The array acquisition module is used to obtain the target array containing network classes and node classes corresponding to the original circuit dataset; The position determination module is used to determine the initial position information of the chip layout based on the target array and a set graph neural network model. The result determination module is used to determine the chip layout result based on the initial position information and a pre-given layout tool. The device also includes an array determination module for: Preprocess the original circuit dataset to determine the target array containing network classes and node classes corresponding to the original circuit dataset; Specifically, the array determination module is used for: Extract the first data information and the second data information from the original circuit dataset. The first data information includes the pin connection information of the module on the chip, and the second data information includes the size information and pin information of the module on the chip. The collection of the first data information is used to form a network class; The collection of the second data information is used to form a node class; The target array is constructed based on the network class and the node class; The location determination module includes: The encoding determination unit is used to encode the information contained in the target array to obtain the feature encoding information corresponding to the target array; A network class group determination unit is used to input the feature encoding information into a pre-trained first graph neural network model to determine network class groups with strong connection relationships in the network class; A partitioning unit is used to divide each of the network class groups into different partitions of the chip's layout matrix. The position determination unit is used to train the set second graph neural network model according to the connection relationship between each network class and the position relationship of each partition, so as to determine the initial position information of the chip layout.

6. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip layout method according to any one of claims 1-4.

7. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a computer processor, are used to perform the chip layout method as described in any one of claims 1-4.

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