A winograd-based correlation algorithm accelerator storage system

Abstract

The present disclosure belongs to the technical field of algorithm hardware circuit design, and in particular to a related algorithm accelerator storage system based on Winograd, comprising: off-chip storage; on-chip tensor cache connected with the off-chip storage, the on-chip tensor cache comprising a reference tensor cache, a real-time tensor cache and a process tensor cache, wherein the reference tensor cache is used to calculate reference graph tensor blocks required by data reuse cache of the accelerator, the real-time tensor cache is used to calculate real-time graph tensor blocks required by the data reuse cache of the accelerator, and the process tensor cache is used to store intermediate result data generated by current calculation of the data reuse cache of the accelerator; and a plurality of registers connected with the on-chip tensor cache, used to receive and / or deliver processing data of the reference graph and / or the real-time graph. The present disclosure meets the high-throughput data requirement of the calculation unit, and can also utilize as few on-chip resources as possible to realize high data multiplexing rate and reduce the demand of the accelerator on off-chip storage bandwidth.

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