Data output control circuit and semiconductor device including the same

Abstract

The present application relates to a data output control circuit and a semiconductor device including the same. A data output control circuit includes a frequency division circuit, a timing signal generation circuit, and a control signal generation circuit. The frequency division circuit frequency-divides a read enable signal to generate a multi-phase clock signal. The timing signal generation circuit generates a plurality of timing signals based on warm-up period information and the multi-phase clock signal. The control signal generation circuit generates a data output control signal based on the multi-phase clock signal and the plurality of timing signals.

Description

Technical Field

[0001] Various implementations generally relate to semiconductor circuits, and more specifically, to data output control circuits and semiconductor devices including such data output control circuits. Background Technology

[0002] As an example of a semiconductor device, a semiconductor memory device can store externally supplied data into its memory region and output data from the memory region to the outside of the semiconductor memory device. To improve the high-speed operation and operational reliability of semiconductor memory devices, controlling the timing of data input / output is crucial. Summary of the Invention

[0003] In one embodiment, a data output control circuit may include a frequency divider circuit, a timing signal generation circuit, and a control signal generation circuit. The frequency divider circuit can be configured to divide a read enable signal to generate a multi-phase clock signal. The timing signal generation circuit can be configured to generate multiple timing signals based on warm-up period information and the multi-phase clock signal. The control signal generation circuit can be configured to generate a data output control signal based on the multi-phase clock signal and the multiple timing signals.

[0004] In one embodiment, a semiconductor device may include a memory cell array, data input / output circuitry, and control circuitry. The data input / output circuitry may be configured to output data from the memory cell array to an external device in response to a data output control signal. The control circuitry may be configured to generate a multi-phase clock signal by dividing a read enable signal provided from another external device, and to generate the data output control signal by selectively masking the multi-phase clock signal based on warm-up cycle information set for the semiconductor device. Attached Figure Description

[0005] Figure 1 This is a diagram illustrating the configuration of a semiconductor system 10 according to an embodiment.

[0006] Figure 2 This is a diagram illustrating the timing of data output based on the preheating cycle of a semiconductor device.

[0007] Figure 3 This is a diagram illustrating the configuration of a semiconductor device 100 according to an embodiment.

[0008] Figure 4 This is a diagram illustrating the configuration of the data output control circuit 131 according to an embodiment.

[0009] Figure 5 This is an operation timing diagram of the data output control circuit 131 according to the implementation method.

[0010] Figure 6 This is a diagram illustrating the configuration of the data output control circuit 132 according to an embodiment.

[0011] Figure 7 This is an example Figure 6 The diagram shows the configuration of the timing signal generation circuit 400.

[0012] Figure 8 This is an example Figure 6 The diagram shows the configuration of the control signal generation circuit 500.

[0013] Figure 9A and Figure 9B This is an operation timing diagram of the data output control circuit 132 according to the implementation method. Detailed Implementation

[0014] According to an embodiment, a data output control circuit capable of improving the control performance for data output timing and a semiconductor device including the data output control circuit can be provided.

[0015] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0016] Figure 1 This is a diagram illustrating the configuration of a semiconductor system 10 according to an embodiment.

[0017] Reference Figure 1 The semiconductor system 10 may include a semiconductor device 100 and a controller 101. The semiconductor device 100 may operate based on the control of the controller 101. In response to a write command provided from the controller 101, the semiconductor device 100 may write data into the memory cell array 110. When the controller 101 receives a write command, an address, and data, the semiconductor device 100 may write data into the memory cell corresponding to the address.

[0018] In response to a read command provided by controller 101, semiconductor device 100 can perform a read operation. When a read command and an address are received from controller 101, semiconductor device 100 can read data from the memory cell corresponding to that address and output the read data to controller 101.

[0019] Semiconductor device 100 may include at least one of NAND flash memory, vertical NAND (hereinafter referred to as "VNAND"), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin-transfer torque random access memory (STT-RAM). In embodiments, semiconductor device 100 may be implemented as having a three-dimensional array structure. In embodiments, semiconductor device 100 may be applied to flash memory devices having a charge storage layer including a conductive floating gate and charge trapping flash memory (CTF) having a charge storage layer including an insulating layer.

[0020] The controller 101 can be connected between the semiconductor device 100 and the host computer. The host computer may include a central processing unit (CPU), a graphics processing unit (GPU), etc. The controller 101 can be configured to interface with the host computer and the semiconductor device 100. Based on the host computer's control, the controller 101 can provide write commands and read commands to the semiconductor device 100.

[0021] The connection between controller 101 and semiconductor device 100 can be a signal line configured to transmit data DQ[7:0], a signal line configured to transmit data strobe signal DQS, and a signal line configured to transmit read enable signal RE. The read enable signal RE can be provided from controller 101. The read enable signal RE can include a complementary signal and can be referred to as an external clock signal. Figure 1 The example given is 8-bit data DQ[7:0], however, data can include 16-bit, 32-bit, etc.

[0022] The data strobe signal DQS can be a bidirectional signal. During the data output operation of the semiconductor device 100, the data strobe signal DQS can be provided from the semiconductor device 100 to the controller 101. When data is input to the semiconductor device 100, the data strobe signal DQS can be provided from the controller 101 to the semiconductor device 100.

[0023] After the read enable signal RE is provided to the semiconductor device 100, data DQ[7:0] can be output based on the data strobe signal DQS. When data is transferred between the controller 101 and the semiconductor device 100, the data transmission timing can be adjusted by the warm-up period defined in the operating specifications of the semiconductor device 100. According to the operating specifications of the semiconductor device 100, data should be output after the warm-up period has elapsed relative to the read enable signal RE.

[0024] The warm-up period can be set to one of "0", "1", "2", and "4". When the warm-up period is set to "0", data can be output in the first cycle of reading the enable signal RE without performing warm-up. When the warm-up period is set to "1", the data output can be delayed in the first cycle of reading the enable signal RE and can also be output in the second cycle of reading the enable signal RE. When the warm-up period is set to "2", the data output can be delayed in the first and second cycles of reading the enable signal RE and can also be output in the third cycle of reading the enable signal RE. When the warm-up period is set to "4", the data output can be delayed in the first to fourth cycles of reading the enable signal RE and can also be output in the fifth cycle of reading the enable signal RE.

[0025] Figure 2 This is a diagram illustrating the timing of data output based on the preheating cycle of a semiconductor device. Figure 2 The read enable signal RE_N, data DQ[7:0], and data strobe signal DQS are illustrated. The read enable signal RE can include complementary signals as described above, and Figure 2 The read enable signal RE_N is illustrated as one of the complementary forms of signals.

[0026] When the preheating cycle is set to '2', such as Figure 2 As shown, the data output can be delayed in the first and second cycles ("cycle 0" and "cycle 1") of the read enable signal RE_N, and the data DQ[7:0] can be output based on the data strobe signal DQS in the third cycle ("cycle 2") of the read enable signal RE_N.

[0027] According to the implementation method, the semiconductor device 100 can adjust the timing of the read enable signal RE_N within the preheating cycle to output data.

[0028] Figure 3 This is a diagram illustrating the configuration of a semiconductor device 100 according to an embodiment.

[0029] Reference Figure 3 The semiconductor device 100 may include a memory cell array 110, peripheral circuitry 120, and control circuitry 130. Peripheral circuitry 120 may include an address decoder 121, a voltage generation circuit 122, a read / write circuit 123, and a data input / output circuit 124.

[0030] The memory cell array 110 can be connected to the address decoder 121 via row lines RL and to the read / write circuitry 123 via bit lines BL1 to BLm. The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The multiple memory cells may be non-volatile memory cells. Each of the multiple memory blocks BLK1 to BLKz may include multiple pages. Among the multiple memory cells, a memory cell connected to a single row line can be defined as a single page.

[0031] The memory cell can be configured by one or more of the following: a single-level cell (SLC) capable of storing a single data bit therein; a multi-level cell (MLC) capable of storing two data bits therein; a three-level cell (TLC) capable of storing three data bits therein; and a four-level cell (QLC) capable of storing four data bits therein.

[0032] The peripheral circuit 120 can drive the memory cell array 110 to perform programming, reading and erasing operations.

[0033] Address decoder 121 can be connected to memory cell array 110 via row lines RL. Address decoder 121 can be configured to operate under the control of control circuitry 130. Address decoder 121 can receive address ADDR from control circuitry 130.

[0034] Address decoder 121 can decode block addresses within address ADDR. Address decoder 121 can select at least one of a plurality of memory blocks BLK1 to BLKz based on the decoded block addresses. Address decoder 121 can decode row addresses within address ADDR. Based on the decoded row addresses, address decoder 121 can select at least one row line RL by applying a voltage provided from voltage generation circuit 122 to at least one row line RL connected to the selected memory block.

[0035] Address decoder 121 can perform programming operations by applying a programming voltage Vpgm to the selected row lines and a pass voltage Vpass lower than the programming voltage Vpgm to the unselected row lines.

[0036] Address decoder 121 can perform a read operation by applying a read voltage Vread to the selected row line and a pass voltage Vpass higher than the read voltage Vread to the unselected row line.

[0037] Erasure operations can be performed on a block-by-block basis within the semiconductor device 100. The address decoder 121 can decode the block address and select a single memory block based on the decoded block address. The address decoder 121 can perform the erase operation by applying a ground voltage to the row line RL connected to the selected memory block and applying an erase voltage Vers to the volume region in which the selected memory block is formed.

[0038] Voltage generation circuit 122 can generate various voltages required for the operation of semiconductor device 100. Voltage generation circuit 122 can generate read voltage Vread, pass voltage Vpass, programming voltage Vpgm, erase voltage Vers, etc., and provide them to address decoder 121. In an embodiment, voltage generation circuit 122 may include multiple pump capacitors, and the multiple pump capacitors can be selectively activated based on the control of control circuit 130 to generate multiple voltages.

[0039] The read / write circuit 123 may include multiple page buffers, such as first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm may be connected to the memory cell array 110 via bit line BL1 to m-th bit line BLm, respectively. First page buffer PB1 to m-th page buffer PBm may operate in response to a control signal CTRL provided from the control circuit 130.

[0040] Page buffers PB1 through PBm can perform data communication with the data input / output circuit 124. Page buffers PB1 through PBm can perform programming operations by transferring data to be stored from the data input / output circuit 124 and data lines DL to the memory cell array 110. Read / write circuit 123 can perform read operations by reading data from the memory cell of the selected page via bit lines BL1 through BLm and providing the read data to the data input / output circuit 124. Read / write circuit 123 can perform erase operations by floating bit lines BL1 through BLm.

[0041] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. In response to the control signal CTRL provided from the control circuit 130, the data input / output circuit 124 can perform data input / output operations. During a read operation, the data input / output circuit 124 can output data provided from the first page buffer PB1 to the m-th page buffer PBm to the controller 101 at a timing based on the aforementioned warm-up period.

[0042] Control circuit 130 can be connected to address decoder 121, voltage generation circuit 122, read / write circuit 123, and data input / output circuit 124. Control circuit 130 can be configured to control the overall operation of semiconductor device 100. Control circuit 130 can operate in response to a command CMD provided from an external device. During a read operation, control circuit 130 can generate a data output control signal by internally adjusting the timing of the read enable signal RE_N, and can output the generated data output control signal as one of the control signals CTRL, so that data is output based on a warm-up cycle. Control circuit 130 can output a signal with the following timing as the data output control signal: at this timing, the pulse in the pulse of read enable signal RE_N corresponding to the warm-up cycle is masked.

[0043] Figure 4 This is a diagram illustrating the configuration of the data output control circuit 131 according to an embodiment. Figure 5 This is an operation timing diagram of the data output control circuit 131 according to the implementation method.

[0044] In the following text, refer to Figure 4 and Figure 5 The description to be made will be based on the configuration and operation of the data output control circuit 131 according to the implementation method.

[0045] According to an embodiment, the data output control circuit 131 may be included in Figure 3 This is just an example in the control circuit 130. The arrangement of the data output control circuit 131 is not limited to this.

[0046] According to an implementation, the data output control circuit 131 may include a decoder 210, a timing signal generation circuit 220, and a control signal generation circuit 230, such as... Figure 4 As shown.

[0047] Decoder 210 can decode the preliminary preheating cycle information LTC<0:1> used to set the preheating cycle to generate preheating cycle information LTC00, LTC01, LTC10, and LTC11. Preheating cycle information LTC00 can correspond to preheating cycle "0", preheating cycle information LTC01 can correspond to preheating cycle "1", preheating cycle information LTC10 can correspond to preheating cycle "2", and preheating cycle information LTC11 can correspond to preheating cycle "4". For example, when only preheating cycle information LTC00 among preheating cycle information LTC00, LTC01, LTC10, and LTC11 is high, the preheating cycle of semiconductor device 100 can be set to "0". When only preheating cycle information LTC01 among preheating cycle information LTC00, LTC01, LTC10, and LTC11 is high, the preheating cycle can be set to "1". The preheating cycle can be set to "2" when only preheating cycle information LTC10 among LTC00, LTC01, LTC10, and LTC11 is high. The preheating cycle can be set to "4" when only preheating cycle information LTC11 among LTC00, LTC01, LTC10, and LTC11 is high.

[0048] The timing signal generation circuit 220 can generate preliminary timing signals LTEN10, LTEN20, LTEN30, and LTEN40 based on the read enable signal RE_N, and can output one of the preliminary timing signals LTEN10, LTEN20, LTEN30, and LTEN40 as the timing signal LTEN based on the warm-up period information LTC00, LTC01, LTC10, and LTC11. The timing signal generation circuit 220 may include logic gate 221, shift register 222, and multiplexer 223.

[0049] Logic gate 221 can invert the read enable signal RE_N to generate an inverted read enable signal RE_N_B.

[0050] Shift register 222 can shift the power supply voltage VCCD based on the inverted read enable signal RE_N_B to generate preliminary timing signals LTEN10, LTEN20, LTEN30, and LTEN40. Shift register 222 may include multiple flip-flops, such as first flip-flop 222-1 to fourth flip-flop 222-4. First flip-flop 222-1 to fourth flip-flop 222-4 can collectively receive the inverted read enable signal RE_N_B as a reference signal (i.e., a clock signal) for the shift operation. First flip-flop 222-1 can latch the level of the power supply voltage VCCD in response to the transition of the inverted read enable signal RE_N_B and can output the latched signal as the preliminary timing signal LTEN10. Second flip-flop 222-2 can latch the preliminary timing signal LTEN10 in response to the transition of the inverted read enable signal RE_N_B and can output the latched signal as the preliminary timing signal LTEN20. The third flip-flop 222-3 can latch the initial timing signal LTEN20 in response to the inverted read enable signal RE_N_B, and can output the latched signal as the initial timing signal LTEN30. The fourth flip-flop 222-4 can latch the initial timing signal LTEN30 in response to the inverted read enable signal RE_N_B, and can output the latched signal as the initial timing signal LTEN40.

[0051] Reference Figure 5 You can input a pair of read enable signals RE_N and RE_C. The read enable signals RE_N and RE_C can have opposite phases. An inverted read enable signal RE_N_B can have the same phase as the read enable signal RE_C.

[0052] With reference to the rising edge of the inverted read enable signal RE_N_B, the preliminary timing signals LTEN10, LTEN20, LTEN30 and LTEN40 can sequentially transition to a high level.

[0053] Based on the warm-up cycle information LTC00, LTC01, LTC10, and LTC11, multiplexer 223 can output one of the preliminary timing signals LTEN10, LTEN20, and LTEN40 as the timing signal LTEN. Here, since semiconductor device 100 is sufficient to support warm-up cycles "0", "1", "2", and "4" as defined in the previously mentioned operating specifications, therefore... Figure 4The data output control circuit 131 is exemplified by not inputting the preliminary timing signal LTEN30 to the multiplexer 223. When the warm-up period information LTC01 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, the multiplexer 223 can output the preliminary timing signal LTEN10 as the timing signal LTEN. When the warm-up period information LTC10 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, the multiplexer 223 can output the preliminary timing signal LTEN20 as the timing signal LTEN. When the warm-up period information LTC11 among the warm-up period information LTC00, LTC01, LTC10, and LTC11 is high, the multiplexer 223 can output the preliminary timing signal LTEN40 as the timing signal LTEN. When the warm-up cycle information LTC00 among the warm-up cycle information LTC00, LTC01, LTC10 and LTC11 is at a high level (i.e., when no warm-up cycle is applied), the multiplexer 223 can output the timing signal LTEN as high level before the timing signal LTEN10 turns high.

[0054] The control signal generation circuit 230 can generate data output control signals RE_RDP and RE_FDP based on the timing signal LTEN by utilizing a signal that masks the pulse corresponding to the preheating cycle in the pulse of the read enable signal RE_N. Of the data output control signals RE_RDP and RE_FDP, RE_RDP can be referred to as the first data output control signal RE_RDP, and RE_FDP can be referred to as the second data output control signal RE_FDP.

[0055] The control signal generation circuit 230 may include a delay unit 231, logic gates 232 and 233, and oscillators 234 and 235.

[0056] Delay unit 231 can delay the read enable signal RE_N by a predetermined amount of time so that the read enable signal RE_N is driven after the predetermined amount of time. Delay unit 231 can be configured to compensate for the delay in signal processing of timing signal generation circuit 220. That is, delay unit 231 can be designed to have a delay amount corresponding to the delay in signal processing of timing signal generation circuit 220.

[0057] The first logic gate 232 can perform a NAND operation on the output signal of the delay unit 231 and the timing signal LTEN to output the signal RE_N_LT. The second logic gate 233 can invert the signal RE_N_LT output from the first logic gate 232.

[0058] Reference Figure 5When the warm-up period is set to "0", the signal RE_N_LT output from the first logic gate 232 can have the same waveform as the read enable signal RE_N. When the warm-up period is set to "1", the signal RE_N_LT can have a waveform that masks the first cycle of the read enable signal RE_N. When the warm-up period is set to "2", the signal RE_N_LT can have a waveform that masks the first and second cycles of the read enable signal RE_N. When the warm-up period is set to "4", the signal RE_N_LT can have a waveform that masks the first to fourth cycles of the read enable signal RE_N.

[0059] The first oscillator 234 can perform an oscillation operation in response to the output signal of the second logic gate 233 to generate the first data output control signal RE_RDP in the data output control signals RE_RDP and RE_FDP. The first oscillator 234 may include a flip-flop 234-1 and a logic gate 234-2. The flip-flop 234-1 can generate the first data output control signal RE_RDP by repeating the following operations: receiving the output signal of the second logic gate 233 as a clock signal, and receiving an inverted signal of the output terminal level as a feedback signal from the logic gate 234-2 inverting the output terminal level to generate an inverted signal in response to a change in the output signal of the second logic gate 233.

[0060] Reference Figure 5 The first data output control signal RE_RDP can be based on the corresponding warm-up cycles "0", "1", "2" and "4", the rising edge of the reference signal RE_N_LT begins its transition, and it can have half the frequency of the signal RE_N_LT.

[0061] The second oscillator 235 can perform an oscillation operation in response to the output signal of the first logic gate 232 to generate the second data output control signal RE_FDP in the data output control signals RE_RDP and RE_FDP. The second oscillator 235 may include a flip-flop 235-1 and a logic gate 235-2. The flip-flop 235-1 can generate the second data output control signal RE_FDP by repeating the following operations: receiving the output signal of the first logic gate 232 as a clock signal, and receiving an inverted signal of the output terminal level as a feedback signal from the logic gate 235-2 in response to the transition of the output signal of the first logic gate 232, the logic gate 235-2 inverting the output terminal level to generate an inverted signal.

[0062] Reference Figure 5The second data output control signal RE_FDP can be based on the corresponding preheating cycles "0", "1", "2" and "4", the falling edge of the reference signal RE_N_LT begins its transition, and it can have half the frequency of the signal RE_N_LT.

[0063] As described above, the data output control circuit 131 according to the embodiment can generate data output control signals RE_RDP and RE_FDP based on a signal that masks the pulse of the read enable signal RE_N to support the warm-up cycle.

[0064] Therefore, when the warm-up cycle is set to "0" (i.e., when no warm-up cycle is applied), the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the first cycle of the read enable signal RE_N.

[0065] When the preheating cycle is set to "1", the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the second cycle of the read enable signal RE_N.

[0066] When the preheating cycle is set to "2", the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP, starting from the third cycle of the read enable signal RE_N.

[0067] When the warm-up cycle is set to "4", the semiconductor device 100 can output data based on the data output control signals RE_RDP and RE_FDP starting from the fifth cycle of the read enable signal RE_N.

[0068] In the following text, refer to Figures 6 to 9B The description to be made will be based on the configuration and operation of the data output control circuit 132 according to the implementation method.

[0069] According to an embodiment, the data output control circuit 132 may be included in Figure 3 In the control circuit 130, this is merely an example. The arrangement of the data output control circuit 132 is not limited to this. According to an embodiment, the data output control circuit 132 can output a signal with the following timing as a data output control signal: at this timing, the pulses corresponding to the warm-up period in the pulses of the read enable signal RE_N are masked based on a multi-phase clock signal generated by dividing the read enable signals RE_N and RE_C. Therefore, under low voltage conditions (i.e., low operating voltage conditions) and high-speed operating conditions (i.e., high operating frequency conditions), the data output control circuit 132 can ensure that the timing margin is referenced. Figure 4The described data output control circuit 131, configured to perform a masking operation based on the read enable signal RE_N, is used to operate stably.

[0070] Figure 6 This is a diagram illustrating the configuration of the data output control circuit 132 according to an embodiment. Figure 7 This is an example Figure 6 The diagram shows the configuration of the timing signal generation circuit 400. Figure 8 This is an example Figure 6 The diagram shows the configuration of the control signal generation circuit 500. Figure 9A and Figure 9B This is an operation timing diagram of the data output control circuit 132 according to the implementation method.

[0071] According to the implementation method, such as Figure 6 As shown, the data output control circuit 132 may include a decoder 310, a frequency divider circuit 320, a timing signal generation circuit 400, and a control signal generation circuit 500.

[0072] Decoder 310 can decode the preliminary preheating cycle information LTC<0:1> used to set the preheating cycle to generate preheating cycle information LTC00, LTC01, LTC10 and LTC11.

[0073] The frequency divider circuit 320 can generate multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB by dividing and separating the phases of a pair of read enable signals RE_N and RE_C. Among the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB, phase clock signal ICLK can be referred to as the first phase clock signal ICLK, phase clock signal QCLK can be referred to as the second phase clock signal QCLK, phase clock signal ICLKB can be referred to as the third phase clock signal ICLKB, and phase clock signal QCLKB can be referred to as the fourth phase clock signal QCLKB.

[0074] Each of the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB can have half the frequency of the read enable signal RE_N. The frequency divider circuit 320 may include a first flip-flop 321 and a second flip-flop 322.

[0075] The first flip-flop 321 can receive the read enable signal RE_N from a pair of read enable signals RE_N and RE_C as a clock signal, can receive the second phase clock signal QCLK as a non-inverting input, and can receive the fourth phase clock signal QCLKB as an inverting input to generate the first phase clock signal ICLK and the third phase clock signal ICLKB. The first flip-flop 321 can latch the input signals (i.e., the second phase clock signal QCLK and the fourth phase clock signal QCLKB) in response to the transition of the read enable signal RE_N to generate the first phase clock signal ICLK and the third phase clock signal ICLKB.

[0076] The second flip-flop 322 can receive the read enable signal RE_C from a pair of read enable signals RE_N and RE_C as a clock signal, receive the first phase clock signal ICLK as a non-inverting input, and receive the third phase clock signal ICLKB as an inverting input to generate the second phase clock signal QCLK and the fourth phase clock signal QCLKB. The second flip-flop 322 can latch the input signals (i.e., the first phase clock signal ICLK and the third phase clock signal ICLKB) in response to the change of the read enable signal RE_C to generate the second phase clock signal QCLK and the fourth phase clock signal QCLKB.

[0077] The timing signal generation circuit 400 can generate multiple timing signals LTENS<0:3> based on the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB and the warm-up period information LTC00, LTC01, LTC10 and LTC11.

[0078] The control signal generation circuit 500 can generate data output control signals RE_RDP and RE_FDP based on multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB and multiple timing signals LTENS<0:3>.

[0079] Reference Figure 7 The timing signal generation circuit 400 can generate preliminary timing signals LTEN10_I, LTEN20_I, LTEN40_I, LTEN10_Q, LTEN20_Q, and LTEN40_Q based on the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. Furthermore, the timing signal generation circuit 400 can selectively combine the preliminary timing signals LTEN10_I, LTEN20_I, LTEN40_I, LTEN10_Q, LTEN20_Q, and LTEN40_Q based on the warm-up period information LTC00, LTC01, LTC10, and LTC11 to generate multiple timing signals LTENS<0:3>.

[0080] The timing signal generation circuit 400 may include a first shift register 410, a second shift register 420, and a multiplexer 430.

[0081] The first shift register 410 can generate preliminary timing signals LTEN10_I, LTEN20_I, and LTEN40_I by shifting the power supply voltage VCCD based on the first phase clock signal ICLK and the third phase clock signal ICLKB. The first shift register 410 may include multiple flip-flops, such as first flip-flop 411 to third flip-flop 413. First flip-flop 411 can latch the level of the power supply voltage VCCD in response to the transition of the first phase clock signal ICLK, and can output the latched signal as the preliminary timing signal LTEN10_I. Second flip-flop 412 can latch the level of the power supply voltage VCCD in response to the transition of the third phase clock signal ICLKB, and can output the latched signal as the preliminary timing signal LTEN20_I. Third flip-flop 413 can latch the preliminary timing signal LTEN20_I in response to the transition of the third phase clock signal ICLKB, and can output the latched signal as the preliminary timing signal LTEN40_I.

[0082] The second shift register 420 can generate preliminary timing signals LTEN10_Q, LTEN20_Q, and LTEN40_Q by shifting the power supply voltage VCCD based on the second phase clock signal QCLK and the fourth phase clock signal QCLKB. The second shift register 420 may include multiple flip-flops, such as first flip-flop 421 to third flip-flop 423. First flip-flop 421 can latch the level of the power supply voltage VCCD in response to the transition of the second phase clock signal QCLK and can output the latched signal as the preliminary timing signal LTEN10_Q. Second flip-flop 422 can latch the level of the power supply voltage VCCD in response to the transition of the fourth phase clock signal QCLKB and can output the latched signal as the preliminary timing signal LTEN20_Q. Third flip-flop 423 can latch the preliminary timing signal LTEN20_Q in response to the transition of the fourth phase clock signal QCLKB and can output the latched signal as the preliminary timing signal LTEN40_Q.

[0083] Multiplexer 430 can selectively combine preliminary timing signals LTEN10_I, LTEN20_I, LTEN40_I, LTEN10_Q, LTEN20_Q, and LTEN40_Q based on warm-up period information LTC00, LTC01, LTC10, and LTC11 to generate multiple timing signals LTENS<0:3>. Among the multiple timing signals LTENS<0:3>, timing signal LTENS0 can be referred to as the first timing signal LTENS0, timing signal LTENS1 can be referred to as the second timing signal LTENS1, timing signal LTENS2 can be referred to as the third timing signal LTENS2, and timing signal LTENS3 can be referred to as the fourth timing signal LTENS3.

[0084] The multiplexer 430 may include multiple logic gates 431-1 to 431-6 and 432-1 to 432-6. The multiple logic gates 431-1 to 431-6 and 432-1 to 432-6 may be divided into a first logic gate group and a second logic gate group. The first logic gate group may include first logic gates 431-1 to sixth logic gates 431-6, and the second logic gate group may include seventh logic gates 432-1 to twelfth logic gates 432-6.

[0085] The first logic gate group can generate the first timing signal LETNS by combining the preliminary timing signals LTEN10_I, LTEN20_I, and LTEN40_I with the warm-up period information LTC00, LTC01, LTC10, and LTC11. <0> Second timing signal LETNS <1> The first logic gate 431-1 performs a NAND operation on the power supply voltage VCCD and the warm-up period information LTC00. The second logic gate 431-2 performs a NAND operation on the preliminary timing signal LTEN20_I and the warm-up period information LTC10. The third logic gate 431-3 performs a NAND operation on the preliminary timing signal LTEN40_I and the warm-up period information LTC11. The fourth logic gate 431-4 performs a NAND operation on the outputs of the first logic gate 431-1 to the third logic gate 431-3 to output the first timing signal LTENS0. The fifth logic gate 431-5 performs a NAND operation on the preliminary timing signal LTEN10_I and the warm-up period information LTC01. The sixth logic gate 431-6 inverts the output of the fifth logic gate 431-5 to output the second timing signal LTENS1.

[0086] The second logic gate group can generate the third timing signal LETNS by combining the initial timing signals LTEN10_Q, LTEN20_Q, and LTEN40_Q with the warm-up period information LTC00, LTC01, LTC10, and LTC11. <2> and the fourth timing signal LTENS <3> The seventh logic gate 432-1 performs a NAND operation on the power supply voltage VCCD and the warm-up period information LTC00. The eighth logic gate 432-2 performs a NAND operation on the preliminary timing signal LTEN20_Q and the warm-up period information LTC10. The ninth logic gate 432-3 performs a NAND operation on the preliminary timing signal LTEN40_Q and the warm-up period information LTC11. The tenth logic gate 432-4 performs a NAND operation on the outputs of the seventh to ninth logic gates 432-3 to output the third timing signal LTENS2. The eleventh logic gate 432-5 performs a NAND operation on the preliminary timing signal LTEN10_Q and the warm-up period information LTC01. The twelfth logic gate 432-6 inverts the output of the eleventh logic gate 432-5 to output the fourth timing signal LTENS3.

[0087] Reference Figure 8 The control signal generation circuit 500 can selectively mask the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB based on multiple timing signals LTENS<0:3> to generate multiple correction clock signals ICLK_A, QCLK_A, ICLK_B, and QCLK_B. Furthermore, the control signal generation circuit 500 can drive the output terminals based on the multiple correction clock signals ICLK_A, QCLK_A, ICLK_B, and QCLK_B to generate data output control signals RE_RDP and RE_FDP. Among the multiple correction clock signals ICLK_A, QCLK_A, ICLK_B, and QCLK_B, correction clock signal ICLK_A can be referred to as the first correction clock signal ICLK_A, correction clock signal QCLK_A can be referred to as the second correction clock signal QCLK_A, correction clock signal ICLK_B can be referred to as the third correction clock signal ICLK_B, and correction clock signal QCLK_B can be referred to as the fourth correction clock signal QCLK_B. The control signal generation circuit 500 may include multiple logic gates 511 to 514, a first driver 520, and a second driver 530.

[0088] Multiple logic gates 511 to 514 can generate multiple correction clock signals ICLK_A, QCLK_A, ICLK_B, and QCLK_B by selectively masking the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB based on multiple timing signals LTENS<0:3>.

[0089] The first logic gate 511 performs a NAND operation on the first phase clock signal ICLK and the first timing signal LTENS0 to output the first correction clock signal ICLK_A. The second logic gate 512 performs a NAND operation on the third phase clock signal ICLKB and the second timing signal LTENS1 to output the third correction clock signal ICLK_B. The third logic gate 513 performs a NAND operation on the second phase clock signal QCLK and the third timing signal LTENS2 to output the second correction clock signal QCLK_A. The fourth logic gate 514 performs a NAND operation on the fourth phase clock signal QCLKB and the fourth timing signal LTENS3 to output the fourth correction clock signal QCLK_B.

[0090] The first driver 520 can generate a first data output control signal RE_RDP by driving the output terminal 521 to a power supply voltage level or a ground voltage level based on a first correction clock signal ICLK_A and a third correction clock signal ICLK_B. The first driver 520 may include a plurality of transistors 522 to 527.

[0091] A first transistor 522 can be connected between a power supply voltage node and an output terminal 521, and can drive the output terminal 521 to the power supply voltage level based on a first correction clock signal ICLK_A. A second transistor 523, connected in parallel with the first transistor 522, can be connected between a power supply voltage node and an output terminal 521, and can drive the output terminal 521 to the power supply voltage level based on a third correction clock signal ICLK_B. A third transistor 524 and a fourth transistor 525 can be connected in series between the first transistor 522 and a ground terminal, and can drive the output terminal 521 to the ground voltage level based on each of the first correction clock signal ICLK_A and the third correction clock signal ICLK_B. A fifth transistor 526 and a sixth transistor 527 can be connected in series between the second transistor 523 and a ground terminal, and can drive the output terminal 521 to the ground voltage level based on each of the third correction clock signal ICLK_B and the first correction clock signal ICLK_A.

[0092] The second driver 530 can generate a second data output control signal RE_FDP by driving the output terminal 531 to a power supply voltage level or a ground voltage level based on a second correction clock signal QCLK_A and a fourth correction clock signal QCLK_B. The second driver 530 may include a plurality of transistors 532 to 537.

[0093] The first transistor 532 can be connected between the power supply voltage node and the output terminal 531, and can drive the output terminal 531 to the power supply voltage level based on the second correction clock signal QCLK_A. In parallel with the first transistor 532, the second transistor 533 can be connected between the power supply voltage node and the output terminal 531, and can drive the output terminal 531 to the power supply voltage level based on the fourth correction clock signal QCLK_B. The third transistor 534 and the fourth transistor 535 can be connected in series between the first transistor 532 and the ground terminal, and can drive the output terminal 531 to the ground voltage level based on each of the second correction clock signal QCLK_A and the fourth correction clock signal QCLK_B. The fifth transistor 536 and the sixth transistor 537 can be connected in series between the second transistor 533 and the ground terminal, and can drive the output terminal 531 to the ground voltage level based on each of the fourth correction clock signal QCLK_B and the second correction clock signal QCLK_A.

[0094] Reference Figure 9A It can generate multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB based on the read enable signals RE_N and RE_C.

[0095] The first-phase clock signal ICLK and the third-phase clock signal ICLKB can be generated by dividing the read enable signal RE_N. The second-phase clock signal QCLK and the fourth-phase clock signal QCLKB can be generated by dividing the read enable signal RE_C.

[0096] By referring to the first phase clock signal ICLK and the third phase clock signal ICLKB, preliminary timing signals LTEN10_I, LTEN20_I and LTEN40_I can be generated.

[0097] Based on the initial timing signals LTEN10_I, LTEN20_I, and LTEN40_I, a first data output control signal RE_RDP suitable for the warm-up cycle can be generated.

[0098] When the warm-up period is set to "1", the first data output control signal RE_RDP can have a waveform that masks the first cycle of the read enable signal RE_N. When the warm-up period is set to "2", the first data output control signal RE_RDP can have a waveform that masks the first and second cycles of the read enable signal RE_N. When the warm-up period is set to "4", the first data output control signal RE_RDP can have a waveform that masks the first to fourth cycles of the read enable signal RE_N.

[0099] By referring to the second phase clock signal QCLK and the fourth phase clock signal QCLKB, preliminary timing signals LTEN10_Q, LTEN20_Q and LTEN40_Q can be generated.

[0100] Based on the initial timing signals LTEN10_Q, LTEN20_Q, and LTEN40_Q, a second data output control signal RE_FDP suitable for the warm-up cycle can be generated.

[0101] When the warm-up period is set to "1", the second data output control signal RE_FDP can have a waveform that masks the first cycle of the read enable signal RE_C. When the warm-up period is set to "2", the second data output control signal RE_FDP can have a waveform that masks the first and second cycles of the read enable signal RE_C. When the warm-up period is set to "4", the second data output control signal RE_FDP can have a waveform that masks the first to fourth cycles of the read enable signal RE_C.

[0102] Each of the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB can have half the frequency of each of the read enable signals RE_N and RE_C. Therefore, regardless of the operating conditions of the semiconductor device 100 (i.e., even when the semiconductor device 100 operates under low voltage conditions or high frequency operating conditions), the first data output control signal RE_RDP and the second data output control signal RE_FDP can be generated stably.

[0103] Reference Figure 9B When the warm-up cycle is set to "0" (i.e., when no warm-up cycle is applied), the semiconductor device 100 can start from the first cycle of reading the enable signal RE_N based on each of the output data in the data output control signals RE_RDP and RE_FDP.

[0104] When the warm-up cycle is set to "1", the semiconductor device 100 can output data based on each of the data output control signals RE_RDP and RE_FDP, starting from the second cycle of the read enable signal RE_N.

[0105] When the warm-up cycle is set to "2", the semiconductor device 100 can output data based on each of the data output control signals RE_RDP and RE_FDP, starting from the third cycle of the read enable signal RE_N.

[0106] When the warm-up cycle is set to "4", the semiconductor device 100 can output data based on each of the data output control signals RE_RDP and RE_FDP, starting from the fifth cycle of the read enable signal RE_N.

[0107] While certain embodiments have been described above, those skilled in the art will understand that the described embodiments are merely illustrative. Therefore, the data output control circuit and the semiconductor device including the data output control circuit should not be limited based on the described embodiments. Rather, the data output control circuit and the semiconductor device including the data output control circuit described herein should be limited only to the appended claims, taken in conjunction with the foregoing description and drawings.

[0108] Cross-references to related applications

[0109] This application claims priority to Korean Application No. 10-2021-0114791, filed with the Korean Intellectual Property Office on August 30, 2021, which is incorporated herein by reference in its entirety as if it were set forth herein.

Claims

1. A data output control circuit, the data output control circuit comprising: The frequency divider circuit divides the read enable signal to generate a multi-phase clock signal. A timing signal generation circuit that generates multiple timing signals based on preheating cycle information and the multi-phase clock signal; as well as A control signal generation circuit generates a data output control signal based on the multi-phase clock signal and the plurality of timing signals. The control signal generation circuit generates multiple correction clock signals by selectively masking the multi-phase clock signals based on the multiple timing signals, and generates the data output control signal by driving the output terminal based on the multiple correction clock signals.

2. The data output control circuit according to claim 1, further comprising a decoder, the decoder decoding the preliminary preheating cycle information used to set the preheating cycle to generate the preheating cycle information.

3. The data output control circuit according to claim 1, wherein, The frequency divider circuit includes: A first flip-flop, responding to a change in a first signal within the read enable signal, latches a second-phase clock signal and a fourth-phase clock signal within the multi-phase clock signal to generate a first-phase clock signal and a third-phase clock signal within the multi-phase clock signal; and A second flip-flop latches the first phase clock signal and the third phase clock signal in response to a change in the second signal in the read enable signal, so as to generate the second phase clock signal and the fourth phase clock signal.

4. The data output control circuit according to claim 1, wherein, The timing signal generation circuit generates the plurality of timing signals by generating a preliminary timing signal based on the multi-phase clock signal and by selectively combining the preliminary timing signal based on the preheating cycle information.

5. The data output control circuit according to claim 1, wherein, The timing signal generation circuit includes: A first shift register shifts the power supply voltage based on the first phase clock signal and the third phase clock signal in the multi-phase clock signal to generate a portion of the initial timing signal; A second shift register, which shifts the power supply voltage based on the second and fourth phase clock signals in the multi-phase clock signal to generate the remainder of the initial timing signal; and A multiplexer that selectively combines the initial timing signals based on the preheating cycle information to generate the plurality of timing signals.

6. The data output control circuit according to claim 1, wherein, The control signal generation circuit includes: Multiple logic gates, which selectively mask the multi-phase clock signal based on the multiple timing signals to generate the multiple correction clock signals; A first driver, based on a first correction clock signal and a third correction clock signal among the plurality of correction clock signals, drives the output terminal to a power supply voltage level or a ground voltage level to generate a first data output control signal among the data output control signals; and The second driver, based on the second and fourth correction clock signals among the plurality of correction clock signals, drives the output terminal to the power supply voltage level or the ground voltage level to generate the second data output control signal among the data output control signals.

7. A semiconductor device, the semiconductor device comprising: Memory cell array; A data input / output circuit that outputs data from the memory cell array to an external device in response to a data output control signal; as well as The control circuit generates the data output control signal by: dividing a read enable signal provided from another external device to generate a multi-phase clock signal; generating multiple timing signals based on warm-up cycle information set for the semiconductor device and the multi-phase clock signal; selectively masking the multi-phase clock signal based on the multiple timing signals to generate multiple correction clock signals; and driving the output terminal based on the multiple correction clock signals.

8. The semiconductor device according to claim 7, wherein, The memory cell array includes multiple memory blocks, and each memory block includes multiple pages.

9. The semiconductor device of claim 7, further comprising a read / write circuit including a plurality of page buffers connected to the memory cell array via bit lines.

10. The semiconductor device according to claim 7, wherein, The control circuit includes: A decoder that decodes the preliminary preheating cycle information used to set the preheating cycle to generate the preheating cycle information; A frequency divider circuit divides the read enable signal to generate the multi-phase clock signal. A timing signal generation circuit generates the plurality of timing signals based on the preheating cycle information and the multi-phase clock signal; and A control signal generation circuit generates the data output control signal based on the multi-phase clock signal and the plurality of timing signals.

11. The semiconductor device according to claim 10, wherein, The timing signal generation circuit generates the plurality of timing signals by generating a preliminary timing signal based on the multi-phase clock signal and by selectively combining the preliminary timing signal based on the preheating cycle information.

12. The semiconductor device according to claim 10, wherein, The timing signal generation circuit includes: A first shift register shifts the power supply voltage based on the first phase clock signal and the third phase clock signal in the multi-phase clock signal to generate a portion of the initial timing signal; A second shift register, which shifts the power supply voltage based on the second and fourth phase clock signals in the multi-phase clock signal to generate the remainder of the initial timing signal; and A multiplexer that selectively combines the initial timing signals based on the preheating cycle information to generate the plurality of timing signals.

13. The semiconductor device according to claim 10, wherein, The control signal generation circuit includes: Multiple logic gates, which selectively mask the multi-phase clock signal based on the multiple timing signals to generate the multiple correction clock signals; A first driver, based on a first correction clock signal and a third correction clock signal among the plurality of correction clock signals, drives the output terminal to a power supply voltage level or a ground voltage level to generate a first data output control signal among the data output control signals; and The second driver, based on the second and fourth correction clock signals among the plurality of correction clock signals, drives the output terminal to the power supply voltage level or the ground voltage level to generate the second data output control signal among the data output control signals.

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