Continuous memory programming operations

Abstract

This application relates to sequential memory programming operations. An example memory device includes: a memory array including a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations including: performing a memory programming operation relative to a set of memory cells of the memory array, wherein the memory programming operation includes applying a sequence of programming pulses to one or more conductive lines electrically coupled to the set of memory cells; pausing the memory programming operation after executing a current programming pulse in the sequence of programming pulses in response to receiving a command to perform a memory access operation, wherein the current programming pulse is executed at a first voltage level; initiating the memory access operation; and restarting the memory programming operation by executing a next programming pulse at a second voltage level exceeding the first voltage level.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to implementing sequential memory programming operations. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory device comprising: a memory array including a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array, the controller performing operations including: performing a memory programming operation relative to a set of memory cells of the memory array, wherein the memory programming operation includes applying a sequence of programming pulses to one or more conductive lines electrically coupled to the set of memory cells; pausing the memory programming operation after executing a current programming pulse in the sequence of programming pulses in response to receiving a command to perform a memory access operation, wherein the current programming pulse is executed at a first voltage level; initiating the memory access operation; and restarting the memory programming operation by executing a next programming pulse at a second voltage level exceeding the first voltage level.

[0004] Another embodiment of this disclosure provides a non-transitory computer-readable storage medium including executable instructions that, when executed by a controller managing a memory array comprising a plurality of memory cells, cause the controller to perform operations including: performing a memory programming operation relative to a set of memory cells of the memory array, wherein the memory programming operation includes applying a first sequence of programming pulses to one or more conductive lines electrically coupled to the set of memory cells; pausing the memory programming operation after executing a current programming pulse in the programming pulse sequence in response to receiving a command to perform a memory access operation, wherein the current programming pulse is executed at a first voltage level; initiating the memory access operation; restarting the memory programming operation by executing a second sequence of programming pulses applied to the one or more conductive lines; and completing the memory access operation by storing one or more data items read from the memory device in an input / output (I / O) buffer associated with the set of memory cells, wherein the I / O buffer is not utilized by the memory programming operation.

[0005] Another embodiment of this disclosure provides a method comprising: performing a memory programming operation relative to a set of memory cells of a memory array via a processing means, wherein the memory programming operation includes a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; pausing the memory programming operation after executing a current programming pulse in the sequence of programming pulses in response to receiving a command to perform a memory access operation, wherein the current programming pulse is executed at a first voltage level; initiating the memory access operation; and restarting the memory programming operation by executing a next programming pulse at a second voltage level exceeding the first voltage level. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 3A This schematically illustrates a set of memory cells arranged in a memory device.

[0010] Figure 3B This schematically illustrates the dependence of source-drain current on the control gate voltage used for two memory cells.

[0011] Figure 3C An example distribution of threshold control gate voltages for memory cells is illustrated schematically.

[0012] Figure 4 An example memory array is shown schematically.

[0013] Figure 5 Examples of sequential memory programming operations according to aspects of this disclosure are illustrated schematically.

[0014] Figure 6 This is a flowchart of an example method for performing sequential memory programming operations according to embodiments of the present disclosure.

[0015] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0016] This disclosure pertains to implementing sequential memory programming operations. One or more memory devices may be part of a memory subsystem, which may be a storage device, a memory module, or a mixture of a storage device and a memory module. (In conjunction with...) Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0017] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may contain two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. In some embodiments, each block may contain multiple sub-blocks. Each plane carries a matrix of memory cells formed on a silicon wafer and connected by conductors called word lines and bit lines, such that word lines connect multiple memory cells forming rows of the memory cell matrix, while bit lines connect multiple memory cells forming columns of the memory cell matrix.

[0018] Depending on the cell type, each memory cell can store one or more bits of binary information and has various logical states related to the number of bits being stored. Logical states can be represented by binary values ​​(e.g., "0" and "1" or combinations thereof). A set of memory cells, called a memory page, can be programmed in a single operation, for example, by selecting consecutive word lines together.

[0019] A programming operation that can be performed relative to a set of memory cells (e.g., a page) in response to a write command received from the host may involve sequentially applying programming voltage pulses to selected word lines. In some embodiments, the programming pulse voltage may sequentially ramp up from an initial voltage value (e.g., 0 V) ​​to a final voltage value (e.g., V). MAX Unselected word lines can be biased during programming operations at a specific voltage (e.g., pass voltage) less than the programming voltage.

[0020] In an illustrative example, a series of high-amplitude pulses with incremental values ​​(e.g., incrementing by a predefined pulse step size) are applied to a selected word line to increase the charge level of the set of memory cells connected to that word line, and consequently, to increase the threshold voltage. After each programming pulse, or after a certain number of programming pulses, a programming verification operation can be performed to determine whether the threshold voltage of the set of memory cells has increased to the desired programming level.

[0021] In some implementations, the memory subsystem controller may pause an ongoing programming operation to perform a higher-priority memory access operation (e.g., a read operation). After the higher-priority memory access operation is completed, the controller may immediately receive a restart programming command indicating that the resources occupied by the higher-priority memory access operation have become available, and therefore the paused programming operation can resume. The duration of the pause is unpredictable, thus causing a priori unknown charge loss, so restarting the programming operation will require performing a programming verification operation followed by issuing a series of programming pulses starting at a voltage level lower than the voltage level at the time of the previous programming operation. Therefore, it may be necessary to repeat at least some of the programming pulses immediately after restarting the programming operation, which will further increase the duration of the programming operation. Considering that any programming operation may be paused more than once, the total duration of programming operations in the memory subsystem is significantly increased by pauses attributable to higher-priority memory access operations.

[0022] The embodiments disclosed herein address the aforementioned drawbacks and other shortcomings of various common techniques by implementing sequential programming operations. Sequential programming operations may be interrupted by higher-priority memory access operations, but will automatically resume immediately after the higher-priority memory access operation is initiated (rather than after the higher-priority memory access operation completes). To allow for immediate resumption of programming operations, there should be no shared input / output (I / O) buffers between the programming operation and the intervening higher-priority memory access (e.g., read) operation. This decoupling of such buffers can be achieved by implementing additional memory elements for storing data necessary to perform the programming operation, thus freeing up the I / O buffers implemented by the secondary data cache (SDC) for performing the intervening higher-priority memory access operation, as described in more detail below.

[0023] While the examples described herein relate to single-level hierarchical cell (SLC) programming, similar techniques can be implemented in various other implementations for programming n memory cells to store two or more bits per cell.

[0024] Therefore, the advantages of this method include, but are not limited to, improving the efficiency of memory programming operations by implementing sequential programming operations, which, if interrupted by a higher-priority memory access operation, will automatically restart immediately after the higher-priority memory access operation is initiated.

[0025] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0030] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further use NVM High Speed ​​(NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller for media management within the same memory device package (e.g., memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0041] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 is responsible for handling interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0042] In one embodiment, memory device 130 includes a programming manager 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from memory interface 113. In some embodiments, local media controller 135 includes at least a portion of programming manager 134 and is configured to perform the functionality described herein. In some embodiments, programming manager 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, programming manager 134 receives a request from, for example, a requester of memory interface 113, for programming data into a memory array of memory device 130. The memory array may comprise an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, for example, memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein a given word line is shared across several sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. The group of memory cells associated with a word line within a sub-block is referred to as a physical page.

[0043] In various embodiments, the memory array may comprise multiple portions, including, for example, portions where sub-blocks are configured as SLC memory and / or portions where sub-blocks are configured as multilevel cell (MLC) memory (i.e., containing memory cells capable of storing two or more bits of information per cell, such as TLC cells). The voltage levels of the memory cells in a TLC memory form a set of eight programming distributions, representing eight different combinations of the three bits stored in each memory cell. Depending on how they are configured, each physical page in a sub-block may contain multiple page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logical page (LP). Multilevel cell (MLC) physical page types may include LP and upper logical page (UP), TLC physical page types are LP, UP, and additional logical page (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). For example, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, wherein each logical page may store data different from the data stored in other logical pages associated with the physical page.

[0044] In an illustrative example, programming manager 134 may receive one or more data items to be programmed into memory device 130. In response, programming manager 134 may perform a programming operation that applies a progressively increasing sequence of programming voltage levels to one or more word lines. The programming operation may be interrupted by a higher-priority memory access operation and will automatically restart immediately after the higher-priority memory access operation is initiated, as described in more detail below.

[0045] Figure 2 The first device, in the form of a memory device 130, and the memory subsystem controller 115, in the form of a memory subsystem, are, according to the embodiment, (e.g., Figure 1 A simplified block diagram of communication between a second device and a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and so on. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0046] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 2 (Not shown in the image) can be programmed to one of at least two target data states.

[0047] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) responds to a command to control access to memory cell array 104 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to an address. In one embodiment, the local media controller 135 includes a programming manager 134 that can perform memory programming operations relative to memory device 130, as described herein.

[0049] The local media controller 135 also communicates with cache register 118. Cache register 118 latches incoming or outgoing data as instructed by the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 121 to the memory cell array 104; then new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to output to memory subsystem controller 115; then new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer of memory device 130 (e.g., may form part of said page buffer). The page buffer may additionally include sensing devices ( Figure 2 (Not shown in the diagram) is used to sense the data status of a memory cell, for example, by sensing the status of the data line connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0050] The memory device 130 receives control signals from the local media controller 135 via control link 132 at the memory subsystem controller 115. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, the memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 136, and outputs data to the memory subsystem controller 115 via the I / O bus 136.

[0051] For example, commands can be received via I / O pins [7:0] of the I / O bus 136 at the input / output (I / O) control circuitry system 112, and then written to the command register 124. Addresses can be received via I / O pins [7:0] of the I / O bus 136 at the input / output (I / O) control circuitry system 112, and then written to the address register 114. Data can be received via I / O pins [7:0] for 8-bit devices or I / O pins [15:0] for 16-bit devices at the input / output (I / O) control circuitry system 112, and then written to the cache register 118. Data can then be written to the data register 121 for programming the memory cell array 104.

[0052] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0053] In some implementations, additional circuitry and signals may be provided, and Figure 2 The memory device 130 has been simplified. It should be understood that the reference... Figure 2 The functions of the various block components described do not necessarily need to be divided into different components or component parts of the integrated circuit device. For example, a single component or component part of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The function of a single block component. Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0054] One or more memory devices of the memory subsystem 100 may be represented, for example, by a NAND memory device utilizing an array of transistors built on a semiconductor chip. Figure 3AAs schematically illustrated, the memory cells of a memory device can be transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), having source (S) electrodes and drain (D) electrodes to allow current to flow through them. The source and drain electrodes can be connected to conductive bit lines (BLs), which can be shared by multiple memory cells. The memory device can comprise an array or memory cells connected to multiple word lines (WLs) and multiple bit lines (BLs), as shown in the diagram. Figure 4 This is an illustrative illustration. The memory device may additionally include circuitry for selectively coupling WL and BL to voltage sources that provide control gate and source-drain signals, as illustrated below for clarity and simplicity. Figure 4 omitted.

[0055] Refer again Figure 3A Memory cells 302 and 304 can be connected to the same bit line N and two different conductive word lines M and M+1, respectively. The memory cells may further have a control gate (CG) electrode to receive a voltage signal V. CG This controls the amount of current flowing between the source and drain electrodes. More specifically, a threshold control gate voltage V can exist. T (Also referred to in this paper as the “threshold voltage” or simply the “threshold”), such that for V CG < V T The source-drain current may be low, but once the control gate voltage exceeds the threshold voltage, i.e., V0... CG > V T This can be roughly increased. The transistors of the same memory device can be characterized by the distribution of their threshold voltages, i.e., P(V... T =dW / dV T Therefore, dW = P(V) T )dV T This indicates that the threshold voltage of any given transistor is in the range [V]. T V T +dV T The possibilities within. For example, Figure 3B A schematic illustration of the source-drain current I. SD Dependence on the control gate voltage for two memory cells, such as memory cell 302 (solid line) and memory cell 304 (dashed line), which have different threshold control gate voltages.

[0056] To make the memory cells non-volatile, the cells can be further equipped with conductive islands-charge storage nodes, which can be transmitted through an insulating layer (in... Figure 3A The area depicted as a dashed line is electrically isolated from the control gate, source electrode, and drain electrode. It responds to an appropriately selected positive (relative to the source potential) control gate voltage V. CGThe charge storage node can receive a charge Q, which can be permanently stored even after the memory cell is powered on, thus stopping the source-drain current. The charge Q can affect the threshold voltage P (V). T The distribution of Q). Generally speaking, it is similar to the distribution of uncharged charge storage nodes P(V). T In contrast, the presence of charge Q shifts the threshold voltage distribution toward higher voltages. This occurs because a stronger positive gate voltage V may be required. CG To overcome the negative potential of the charge Q at the charge storage node. If the charge sequence Q can be selected... k (where 1 ≤ k ≤ 2) N If any charge Q is programmed (and then detected during a read operation) into a memory cell, the memory cell can be used as an N-bit memory cell. k Preferably, they are chosen to be sufficiently different from each other such that any two adjacent voltage distributions P(V) are such that... T Q k ) and P(V T Q k+1 ) do not overlap but are separated by valley margins, thus 2 N Distribution P(V) T Q k ) and 2 N -1 valley margin interval.

[0057] Figure 3C The distribution of threshold-controlled gate voltages of a memory cell capable of storing three bits of data by programming the memory cell to at least eight charge states is illustrated, the at least eight charge states being different from the charge storage node of the cell. Figure 3C The exhibition is presented in 2 3 -1 = 7 valley margins VM k 2 of the separated three-level cell (TLC) N = Threshold voltage P(V) for 8 different charge states T Q k The distribution of ) is thus programmed into the k-th charge state (i.e., having a charge Q deposited on its charging storage node). k The memory cell can store a specific combination of N bits (e.g., for N=4, 0110). This charge state Q k Valley margin VM can be detected during read operations. k Internal control gate voltage V CG Sufficient to open the cell to source-drain current while the previous valley line tolerance VM k-1 The control gate voltage within is insufficient to open the cell to the source-drain current.

[0058] Memory devices can be classified by the number of bits stored in each cell of the memory. For example, a single-level cell (SLC) memory has cells that can each store one bit of data (N=1). A multi-level cell (MLC) memory has cells that can each store up to two bits of data (N=2), a three-level cell (TLC) memory has cells that can each store up to three bits of data (N=3), and a four-level cell (QLC) memory has cells that can each store up to four bits of data (N=4). Generally, the operations described herein are applicable to memory devices with N bits (where N>1) of memory cells.

[0059] For example, a TLC may be able to exist in at least eight charge states Q. k One of them (where the first state can be the uncharged state Q1 = 0), its threshold voltage distribution is determined by the valley margin VM k Separating the data allows for reading data stored in memory cells. For example, if the read threshold voltage is determined to be 2 during a read operation... N Within a specific valley margin of -1, it can be determined that the memory cell is in a 2 N A specific charge state among the possible charge states. By identifying the right valley margin of the cell, the values ​​of all its N bits can be determined. The identifier of the valley margin (e.g., its coordinates, such as the position of the center and width) can be stored in the read level threshold register of the memory controller 215.

[0060] As mentioned above, the memory controller 215 can program the state of the memory cells, and then read the memory cells by setting the read threshold voltage V. T This state is read by comparing it with one or more read level thresholds. The read operation can be performed after the memory cell has been placed into one of its charged states by a previous programming operation, which may consist of one or more programming passes. Each programming pass applies an appropriate programming voltage to a given word line to place the appropriate charge on the charge storage node of the memory cell connected to the word line.

[0061] The programming operation involves a sequence of programming voltage pulses applied to the selected (target) word line (i.e., the word line electrically coupled to the target memory cell). See again... Figure 3A The source (S) and drain (D) electrodes of a memory cell can be connected to a conductive bit line shared by multiple memory cells. Programming operations apply a sequence of programming voltage pulses to the control gate (CG) via the corresponding word line (WL). Each programming voltage pulse induces an electric field that pulls electrons to the charge storage node. After each programming pulse is applied to the selected word line, a verification operation can be performed by reading the memory cell to determine the threshold voltage V of the memory cell. THas the desired value (voltage verification level) been reached? If the threshold voltage V of the memory cell... T Once the verification voltage associated with the desired state has been reached, the bit line connected to the memory cell can be biased at the programming disable voltage, thereby preventing further programming of the memory cell coupled to the bit line, i.e., to prevent the threshold voltage V of the memory cell from being exceeded. T In response to a subsequent programming pulse applied to the selected word line, the bit is shifted further upwards.

[0062] Figure 5 Examples of sequential memory programming operations according to aspects of this disclosure are illustrated schematically. For example... Figure 5 To illustrate, a programming operation 500 can be performed relative to a set of memory cells (e.g., a page) in response to a write command received from the host. The programming operation 500 may involve sequentially applying programming voltage pulses 510A-510K to a selected word line to increase the charge level of the set of memory cells connected to that word line, and thereby increase the threshold voltage.

[0063] In some implementations, the programming pulse voltage can be sequentially ramped up from an initial voltage value (e.g., 0 V) ​​to a final voltage value (e.g., V). PGM Unselected word lines can be biased during programming operations at a specific voltage (e.g., pass voltage) less than the programming voltage.

[0064] After each programming pulse 510A-510Z, or after a specific number of programming pulses, programming verification operations 520A-520Z may be performed, which may involve one or more read operations to determine whether the threshold voltage of the memory cell set has been increased to the desired programming level.

[0065] As mentioned above, the memory subsystem controller can pause ongoing programming operations to perform higher-priority memory access operations (e.g., read operations). Figure 5 In an illustrative example, the memory device controller may, in response to receiving a higher-priority memory access command (e.g., a read command), initiate an intermediate read operation 530 after applying the current programming pulse 510K and performing the corresponding programming verification operation 520K. The memory device controller may save the programming operation state (e.g., programming pulse sequence number or corresponding voltage level, block address, and programming verification operation parameters) in a status register (e.g., in the page buffer latch of the memory device). After saving the programming operation state, the memory device controller may immediately initiate the read operation 530, which involves reading one or more requested data items from the memory device.

[0066] After initiating a higher-priority memory access operation 530, the memory device controller can immediately and automatically restart the interrupted programming operation 500 without waiting for the intermediate read operation 530 to complete. The memory device controller does not require an externally initiated restart command to restart the interrupted programming operation 500. To restart the interrupted programming operation 500, the memory device controller restores the previously saved programming operation state (e.g., programming pulse sequence number or corresponding voltage level, block address, and programming verification operation parameters) by reading the status register.

[0067] To allow programming operation 500 to resume immediately after a higher-priority memory access operation 530 is initiated, data read from the memory device via a read command is stored in an input / output (I / O) buffer (e.g., a secondary data cache (SDC)) that is not used by programming operation 500. To free up the SDC for dedicated read operations, programming operation data is stored in a separate memory element, such as one bit per bit line, which may be allocated in a page buffer latch.

[0068] Since the interrupted and automatically restarted programming operation 500 automatically resumes immediately after the intervening read operation is initiated, and the restarted operation continues to apply the programming voltage, which follows the last programming voltage pulse applied before the interruption, the additional delay of initiating the intervening read operation is negligible compared to the total delay of a typical programming operation.

[0069] Figure 6 This is a flowchart illustrating an example method of performing sequential memory programming operations in overwrite mode according to embodiments of the present disclosure. Method 600 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing device), or a combination thereof. In some embodiments, method 600 is executed by a programming manager component 134, which may be... Figure 1 The memory subsystem controller 115 and / or local media controller 135 are implemented. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, one or more operations may be omitted in various embodiments. Therefore, not all operations are required in every embodiment.

[0070] At operation 610, the controller implementing the method identifies data items to be stored by a portion of the memory device. In an illustrative example, by Figure 1The programming manager 134 implemented by the local media controller 135 can receive requests from the memory interface 113 of the memory subsystem controller 115 to perform programming operations (e.g., write operations) relative to a specified portion of the memory device. A portion of the memory device may contain a set of memory cells electrically coupled to word lines and one or more bit lines. In one embodiment, the set of memory cells may be represented by a block. Data items written to the memory device are transmitted via… Figure 2 The I / O data path 112 is received and routed to the memory device via the controller. In one embodiment, the data to be programmed may be stored in a page buffer associated with the set of memory cells, as described in more detail above herein.

[0071] At operation 620, the controller performs a memory programming operation relative to the set of memory cells. The memory programming operation involves applying a sequence of programming pulses to word lines electrically coupled to the set of memory cells. In one embodiment, the programming operation may involve selectively suppressing bit lines based on the desired charge level of the corresponding memory cell while applying one or more programming pulses to the selected word lines. Each programming pulse may be followed by a programming verification operation, which involves reading the set of memory cells to confirm that the memory cells have reached the desired charge level, as described in more detail above.

[0072] At operation 630, the controller receives a command to perform a higher-priority memory access operation (e.g., a read operation), as described in more detail above herein.

[0073] At operation 640, the controller pauses the memory programming operation. In one embodiment, pausing the memory programming operation involves completing the current programming pulse in the programming pulse sequence and performing a subsequent read verification operation. Pausing the memory programming operation also involves storing metadata encoding the programming operation state (e.g., programming pulse sequence number or corresponding voltage level, block address, and programming verification operation parameters) in the status register of the memory device, as described in more detail above herein.

[0074] At operation 650, the controller initiates a requested memory access operation (e.g., a read operation), which involves reading one or more data items from a set of memory cells, as described in more detail above herein.

[0075] At operation 660, the controller restarts the interrupted memory programming operation. Restarting the memory programming operation involves recovering metadata (e.g., programming pulse sequence number or corresponding voltage level, block address, and programming verification operation parameters) from the status register, as described in more detail above. In one embodiment, the controller restarts the interrupted memory programming operation by continuing to apply a programming pulse sequence to the word line electrically coupled to the memory cell collector, the programming pulse sequence starting at the next programming pulse immediately following the last voltage pulse applied before the interrupted programming operation, as described in more detail above.

[0076] At operation 670, the controller performs the restarted memory programming operation while simultaneously completing the requested memory access operation (e.g., a read operation). The controller stores one or more data items read from the memory device in an input / output (I / O) buffer associated with the set of memory cells. In one embodiment, the I / O buffer is represented by a secondary data cache (SDC) associated with the set of memory cells, as described in more detail above herein.

[0077] Figure 7 This describes an example machine of a computer system 1100 in which an instruction set for causing the machine to perform the methods discussed herein can be executed. In some embodiments, the computer system 1100 corresponds to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to... Figure 1 (Operation of the programming manager 134). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0078] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0079] Example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1118, which communicate with each other via a bus 1130.

[0080] Processing device 1102 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1102 is configured to execute instructions 1126 to perform the operations and steps discussed herein. Computer system 1100 may additionally include a network interface device 1108 for communication on network 1120.

[0081] Data storage system 1118 may include machine-readable storage medium 1114 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more instruction sets 1126 or software embodying any or more of the methods or functions described herein. Instructions 1126 may also reside wholly or at least partially in main memory 1104 and / or processing device 1102 during execution by computer system 1100, which also constitute machine-readable storage medium. Machine-readable storage medium 1124, data storage system 1118, and / or main memory 1104 may correspond to... Figure 1 The memory subsystem 110.

[0082] In one embodiment, instruction 1126 includes instructions for implementing the corresponding Figure 1 The programming manager 134 provides functional instructions. Although the machine-readable storage medium 1124 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0083] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0084] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0085] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0087] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0088] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A memory array comprising multiple memory cells electrically coupled to multiple conductive lines; and A controller, coupled to the memory array, performs operations including the following: A memory programming operation is performed relative to the memory cell set of the memory array, wherein the memory programming operation includes a first programming pulse sequence applied to one or more conductive lines electrically coupled to the memory cell set; In response to receiving a command to perform a memory access operation, the memory programming operation is paused after the current programming pulse in the first programming pulse sequence is executed, wherein the current programming pulse is executed at a first voltage level; Initiate the memory access operation; The memory programming operation is restarted by executing a second programming pulse sequence applied to the one or more conductive lines; and The memory access operation is performed by storing one or more data items read from the memory array in an input / output I / O buffer associated with the set of memory cells, wherein the I / O buffer is not used by the memory programming operation.

2. The memory device of claim 1, wherein the programming operation data for the programming operation is stored in a page buffer associated with the set of memory cells.

3. The memory device of claim 1, wherein the I / O buffer is represented by a secondary data cache SDC associated with the set of memory cells.

4. The memory device of claim 1, wherein pausing the memory programming operation further comprises: The state of the programming operation is stored in a page buffer associated with the set of memory cells.

5. The memory device of claim 1, wherein the memory programming operation further includes one or more programming verification operations that compare a threshold voltage level of the memory cell set with at least one predefined threshold voltage level.

6. The memory device according to claim 1, wherein The memory access operation is completed simultaneously with one or more programming pulses that execute the restarted memory programming operation.

7. The memory device according to claim 1, wherein the memory access operation is a read operation.

8. The memory device of claim 1, wherein the set of memory cells is a block of the memory array.

9. A non-transitory computer-readable storage medium comprising executable instructions, which, when executed by a controller managing a memory array comprising a plurality of memory cells, cause the controller to perform operations including: A memory programming operation is performed relative to the memory cell set of the memory array, wherein the memory programming operation includes a first programming pulse sequence applied to one or more conductive lines electrically coupled to the memory cell set; In response to receiving a command to perform a memory access operation, the memory programming operation is paused after the current programming pulse in the first programming pulse sequence is executed, wherein the current programming pulse is executed at a first voltage level; Initiate the memory access operation; The memory programming operation is restarted by executing a second programming pulse sequence applied to the one or more conductive lines; and The memory access operation is performed by storing one or more data items read from the memory array in an input / output I / O buffer associated with the set of memory cells, wherein the I / O buffer is not used by the memory programming operation.

10. The non-transitory computer-readable storage medium of claim 9, wherein the programming operation data for the programming operations is stored in a page buffer associated with the set of memory cells.

11. The non-transitory computer-readable storage medium of claim 9, wherein the I / O buffer is represented by a secondary data cache SDC associated with the set of memory cells.

12. The non-transitory computer-readable storage medium of claim 9, wherein suspending the memory programming operation further comprises: The state of the programming operation is stored in a page buffer associated with the set of memory cells.

13. The non-transitory computer-readable storage medium of claim 9, wherein the memory programming operation further includes one or more programming verification operations that compare a threshold voltage level of the memory cell set with at least one predefined threshold voltage level.

14. The non-transitory computer-readable storage medium of claim 9, wherein... The memory access operation is completed simultaneously with one or more programming pulses that execute the restarted memory programming operation.

15. The non-transitory computer-readable storage medium of claim 9, wherein the memory access operation is a read operation.

16. The non-transitory computer-readable storage medium of claim 9, wherein the set of memory cells is a block of the memory array.

17. A method comprising: A memory programming operation is performed by a processing device relative to a set of memory cells of a memory array, wherein the memory programming operation includes a first programming pulse sequence applied to one or more conductive lines electrically coupled to the set of memory cells; In response to receiving a command to perform a memory access operation, the memory programming operation is paused after the current programming pulse in the first programming pulse sequence is executed, wherein the current programming pulse is executed at a first voltage level; Initiate the memory access operation; The memory programming operation is restarted by executing a second programming pulse sequence applied to the one or more conductive lines; and The memory access operation is performed by storing one or more data items read from the memory array in an input / output I / O buffer associated with the set of memory cells, wherein the I / O buffer is not used by the memory programming operation.

18. The method of claim 17, wherein the memory access operation is a read operation.

19. The method of claim 17, wherein the set of memory cells is a block of the memory array.

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