Memory device and operating method thereof

Abstract

A memory device includes a memory cell and a program operation executor configured to perform a verify operation and a program voltage application operation, wherein the verify operation uses a first verify voltage, a second verify voltage higher than the first verify voltage, and a third verify voltage higher than the second verify voltage to verify whether a threshold voltage of the memory cell has reached a threshold voltage corresponding to a target program state, and the program voltage application operation applies a program voltage to a word line. The memory device also includes a program operation controller configured to control the program operation executor such that, during the program voltage application operation, a pre-charge voltage is first applied to a second bit line coupled to a second memory cell before the pre-charge voltage is applied to a first bit line.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically to memory devices and methods of operating the memory devices. Background Technology

[0002] Memory devices are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Memory devices are generally classified as volatile memory devices or non-volatile memory devices.

[0003] Volatile memory devices are memory devices that lose stored data when power is interrupted. Representative examples of volatile memory devices include those using Static Random Access Memory (SRAM), Dynamic RAM (DRAM), and Synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices that retain stored data even when power is interrupted. Representative examples of non-volatile memory devices include those using Read-Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash memory, Phase-Change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). Flash memory is typically classified as NOR or NAND. Summary of the Invention

[0004] Various embodiments of this disclosure relate to memory devices capable of mitigating or preventing coupling phenomena between adjacent bit lines during programming operations, and to methods of operating the memory device.

[0005] Embodiments of this disclosure may provide a memory device. The memory device may include: a memory cell; a programming operation executor configured to perform a verification operation and a programming voltage application operation, wherein the verification operation verifies whether a threshold voltage of the memory cell has reached a threshold voltage corresponding to a target programming state using a first verification voltage, a second verification voltage higher than the first verification voltage, and a third verification voltage higher than the second verification voltage; and wherein, based on the result of the verification operation, a programming voltage application operation is performed to apply a programming voltage to a word line commonly connected to the memory cell; and a programming operation controller configured to control the programming operation executor such that, during the programming voltage application operation, before applying a precharge voltage to a first bit line connected to a first memory cell in the memory cell having a threshold voltage higher than the first verification voltage and lower than or equal to the second verification voltage, a precharge voltage is first applied to a second bit line connected to a second memory cell in the memory cell having a threshold voltage higher than the second verification voltage and lower than or equal to the third verification voltage.

[0006] Embodiments of this disclosure may provide a method for operating a memory device that performs a programming operation to store data in memory cells. The method may include: applying at least three verification voltages to word lines commonly connected to memory cells; applying precharge voltages to bit lines respectively connected to memory cells at different time points based on threshold voltages of memory cells identified using the at least three verification voltages; and applying programming voltages to the word lines after applying the precharge voltages. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 This is an example Figure 1 A diagram of the structure of a memory device.

[0009] Figure 3 This is an example Figure 2 A diagram of the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0010] Figure 4 This is a diagram illustrating the threshold voltage distribution of memory cells according to the programming operations of the memory device.

[0011] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0012] Figure 6 This is a diagram illustrating the TPGM operation of a memory device.

[0013] Figure 7This is a diagram illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0014] Figure 8 This is a diagram illustrating the operation of a page buffer circuit according to an embodiment of the present disclosure.

[0015] Figure 9 This is a diagram illustrating the steps of applying the programming voltage during the programming operation of a memory device.

[0016] Figure 10 This is a diagram illustrating the coupling phenomenon between adjacent bit lines that occurs during programming operations of a memory device.

[0017] Figure 11 This is a diagram illustrating the programming voltage application step in the programming operation of a memory device according to an embodiment of the present disclosure.

[0018] Figure 12 This is a flowchart illustrating the programming operations of a memory device according to an embodiment of the present disclosure.

[0019] Figure 13 This is an example Figure 1 A diagram of the memory controller.

[0020] Figure 14 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0021] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system that applies an embodiment of the memory system according to the present disclosure.

[0022] Figure 16 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions of embodiments of this disclosure incorporated herein are illustrative of implementations based on the concept of this disclosure. Implementations based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to those described in this specification or application.

[0024] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0025] Reference Figure 1The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device that stores data under the control of the host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0026] Depending on the host interface used for communication with host 300, memory system 50 can be manufactured as any of various types of storage devices. For example, memory system 50 can be implemented as any of various types of storage devices, such as: solid-state drives (SSDs); multimedia cards (such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), or micro MMC); secure digital cards (such as SD, mini SD, or micro SD); universal serial bus (USB) storage devices; universal flash memory (UFS) devices; PCMCIA card-type storage devices; peripheral component interconnect (PCI) card-type storage devices; high-speed PCI (PCI-E) card-type storage devices; compact flash (CF) cards; smart media cards; and memory sticks.

[0027] The memory system 50 can be manufactured in any of a variety of package types. For example, the memory system 50 can be manufactured in any of a variety of package types such as POP, SIP, SoC, MCP, COB, WFP, and WSP.

[0028] The memory device 100 can store data. The memory device 100 can be operated in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0029] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0030] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or a unit for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0031] In embodiments, the memory device 100 may use Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, for ease of description, the description assumes that the memory device 100 uses NAND flash memory.

[0032] Memory device 100 can receive commands and addresses from memory controller 200 and can access address-selected regions in the memory cell array. Memory device 100 can perform operations instructed by commands on the address-selected regions. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, memory device 100 can program data into the address-selected region. During a read operation, memory device 100 can read data from the address-selected region. During an erase operation, memory device 100 can erase data stored in the address-selected region.

[0033] In an embodiment, the memory device 100 may include a programming operation executor 150 and a programming operation controller 160.

[0034] The programming operation executor 150 can perform programming operations on memory cells. A programming operation can be an operation of storing data in a memory cell. Specifically, a programming operation can be an operation of increasing the threshold voltage of a memory cell based on the data to be stored in the memory cell. When performing a programming operation, each memory cell can have a threshold voltage corresponding to any of a plurality of programming states. The plurality of programming states can be specified based on the number of data bits stored in a memory cell. For example, when programming data in a three-level cell (TLC) scheme that stores three bits of data in one memory cell, the plurality of programming states can indicate an erase state and first programming states through seventh programming states. After a programming operation has been performed, the threshold voltage of the memory cell can be determined based on the data to be stored in the memory cell. Each memory cell can have any of a plurality of programming states as the target programming state, depending on the data to be stored in the corresponding memory cell.

[0035] In an implementation, the programming operation may include a programming voltage application operation and a verification operation. The programming voltage application operation may be the application of a programming voltage to a word line commonly connected to a memory cell. The verification operation may be the verification of whether a threshold voltage for each memory cell has reached the threshold voltage corresponding to the target programming state. In an implementation, the verification operation may be the application of at least three verification voltages to the word line connected to the memory cell.

[0036] The programming operation controller 160 can control the programming operation actuator 150 during programming operations. In one embodiment, the programming operation controller 160 can control the programming operation actuator 150 such that a programming voltage is applied to the word line commonly connected to the memory cell during a programming voltage application operation. In another embodiment, the programming operation controller 160 can control the programming operation actuator 150 such that at least three verification voltages are applied to the word line connected to the memory cell during a verification operation.

[0037] Please refer to later Figure 7 The operation of the programming operation executor 150 and the programming operation controller 160 according to embodiments of the present disclosure is described in detail.

[0038] The memory controller 200 can control the overall operation of the memory system 50.

[0039] When power is applied to the memory system 50, the memory controller 200 can run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0040] In this embodiment, the memory controller 200 can receive data and logical block addresses (LBAs) from the host 300, and can convert the logical block addresses (LBAs) into physical block addresses (PBAs), whereby the physical block addresses (PBAs) indicate the addresses of the memory cells included in the memory device 100 where data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. In this specification, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0041] The memory controller 200 can control the memory device 100 to perform write, read, or erase operations in response to requests received from the host 300. During a write operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0042] In this implementation, the memory controller 200 can autonomously generate commands, addresses, and data regardless of whether it receives a request from the host 300, and can send them to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data used to perform read and write operations involved in wear leveling, read recycling, garbage collection, etc.

[0043] In one implementation, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the memory devices 100 such that the operations of at least two memory devices 100 overlap with each other.

[0044] The host 300 can communicate with the memory system 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduction DIMM (LRDIMM).

[0045] Figure 2 This is an example Figure 1 A diagram showing the structure of the memory device 100.

[0046] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0047] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 121 via row lines. Memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLm. Each of memory blocks BLK1 to BLKz may include multiple memory cells. In embodiments, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a page. In other words, memory cell array 110 may include multiple pages. In embodiments of this disclosure, each of the memory blocks BLK1 to BLKz included in memory cell array 110 may include multiple dummy cells. For a dummy cell, one or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0048] Each memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0049] Peripheral circuitry 120 can drive memory cell array 110. In this example, peripheral circuitry 120 can drive memory cell array 110 under the control of control logic 130 to perform programming, reading, and erasing operations. In other examples, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLm or discharge the applied voltages under the control of control logic 130.

[0050] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0051] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments, row lines RL may also include pipe select lines.

[0052] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0053] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD in the received address ADDR. Address decoder 121 can select at least one word line WL of the selected memory block by applying the voltage provided from voltage generator 122 to at least one word line WL according to the decoded row address RADD.

[0054] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and apply a pass voltage having a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and apply a verification pass voltage having a level higher than the verification voltage to the unselected word line.

[0055] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage with a level higher than the read voltage to the unselected word line.

[0056] Erasure operations on memory device 100 are performed on a block-by-block basis. During the erase operation, the address ADDR input to memory device 100 includes the block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0057] According to embodiments of this disclosure, address decoder 121 can decode column addresses in received address ADDR. The decoded column addresses can be transmitted to page buffer set 123. In embodiments, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0058] Voltage generator 122 can use the external power supply voltage supplied to memory device 100 to generate multiple operating voltages Vop. Voltage generator 122 can operate under the control of control logic 130.

[0059] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as the operating voltage of the memory device 100.

[0060] In this implementation, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. Voltage generator 122 can use either an external or internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can generate various voltages used by the memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0061] Voltage generator 122 may include multiple pumping capacitors for receiving internal power supply voltages to generate multiple operating voltages Vop with various voltage levels, and the multiple operating voltages Vop may be generated by selectively enabling the multiple pumping capacitors under the control of control logic 130.

[0062] The generated operating voltage Vop can be supplied to the memory cell array 110 by the address decoder 121.

[0063] Page buffer group 123 includes page buffer PB1 to page buffer PBm. Page buffer PB1 to page buffer PBm are connected to memory cell array 110 via bit line BL1 to bit line BLm respectively. Page buffer PB1 to page buffer PBm are operated under the control of control logic 130.

[0064] Page buffers PB1 through PBm can send / receive data DATA to / from data input / output circuit 124. During programming operations, page buffers PB1 through PBm receive the data DATA to be stored through data input / output circuit 124 and data line DL.

[0065] During programming operations, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page is programmed based on the received data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0066] During a read operation, page buffer group 123 can read data DATA from the memory cell in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0067] During an erase operation, page buffer group 123 may allow bit lines BL1 to BLm to float. In one embodiment, page buffer group 123 may include column select circuitry.

[0068] In one implementation, when multiple data entries stored in some of the multiple page buffers included in the page buffer group 123 are being programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0069] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates in response to the control logic 130.

[0070] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives the data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs the data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the page buffer group 123 to the external controller.

[0071] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass or fail signal to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0072] Control logic 130 can be connected to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0073] Control logic 130 can control peripheral circuit 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit signal VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit signal VRYBIT to sensing circuit 125. In addition, control logic 130 can determine whether the verification operation is successful or unsuccessful in response to pass signal PASS or failure signal FAIL output from sensing circuit 125.

[0074] Figure 3 This is an example Figure 2 A diagram of the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0075] Storage block BLKi indicator Figure 2 Any one of the storage blocks BLK1 to BLKz.

[0076] Reference Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). Specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be individually connected to string STs, and the source line SL can be collectively connected to string STs. String STs can be configured equally; therefore, the string ST connected to the first bit line BL1 will be described in detail by way of example.

[0077] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, multiple memory cells MC1 to MC16, and a drain selection transistor DST. A single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more memory cells than the memory cells MC1 to MC16 shown in the figure.

[0078] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST included in different string STs can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16 respectively. Among the memory cells included in different string STs, a group of memory cells connected to the same word line can be referred to as a "physical page (PG)". Therefore, the memory block BLKi can include the same number of physical pages (PG) as the number of word lines WL1 to WL16.

[0079] A memory cell can store one bit of data. This cell is typically designated as a "single-level cell (SLC)". In this case, a physical page (PG) can store data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PG).

[0080] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store data corresponding to two or more logical pages (LPG).

[0081] Figure 4 This is a diagram illustrating the threshold voltage distribution of memory cells according to the programming operations of the memory device.

[0082] exist Figure 4 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (the number of cells).

[0083] Reference Figure 4 The threshold voltage distribution of a memory cell can be changed from the initial state to the programmed state according to the programming operation.

[0084] exist Figure 4 The text describes a TLC scheme that programs data using one of the memory cells to store three bits of data.

[0085] The initial state can be a state where no programming operation has been performed and the threshold voltage distribution of the memory cell is in the erase state E.

[0086] A programming state can be a distribution of threshold voltages for memory cells to which programming operations are performed. Each of the memory cells to which programming operations are performed can have a threshold voltage corresponding to any one of a plurality of programming states. For example, when programming data in a three-level cell (TLC) scheme in which three bits of data are stored in a memory cell, a plurality of programming states can indicate an erase state E and first programming states PV1 through seventh programming states PV7. In an implementation, each of the memory cells to which programming operations are performed can have a threshold voltage corresponding to either erase state E or any one of the first programming states PV1 through seventh programming states PV7. The threshold voltage of each memory cell in the initial state can be increased by programming operations to a threshold voltage corresponding to either erase state E or any one of the first programming states PV1 through seventh programming states PV7.

[0087] Each memory cell can have either an erase state E or a programming state PV1 through PV7 as its target programming state. The target programming state is determined based on the data to be stored in the corresponding memory cell. Through a corresponding programming operation, each memory cell can have a threshold voltage corresponding to the target programming state in the programming state.

[0088] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0089] exist Figure 5 In the graph, the horizontal axis represents time, and the vertical axis represents the magnitude of the programming voltage Vpgm.

[0090] exist Figure 5 The text describes a TLC scheme that programs data using one of the memory cells to store three bits of data.

[0091] Reference Figure 5 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. The memory device 100 may perform the programming operation by executing multiple programming cycles PL1 to PLn, such that each of the selected memory cells has a threshold voltage corresponding to any one of the multiple programming states.

[0092] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application step (PGM step) and a verification step (verification step).

[0093] The programming voltage application step (PGM step) can be a step of applying a programming voltage to a selected word line connected to the selected memory cell. For example, memory device 100 can apply a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell in a first programming cycle PL1. After the first programming voltage Vpgm1 is applied to the selected word line connected to the selected memory cell, the corresponding threshold voltage of the selected memory cell can be a threshold voltage corresponding to a target programming state among a plurality of programming states.

[0094] The verification step can be the step of applying a verification voltage to the selected word line connected to the selected memory cell. The verification step can also be the step of determining whether the corresponding threshold voltage of the selected memory cell corresponds to a threshold voltage among multiple programming states. Alternatively, the verification step can be the step of applying a verification voltage corresponding to the target programming state of the selected memory cell. For example, when the selected memory cell is read as a shutdown cell using a verification voltage corresponding to the corresponding target programming state of the selected memory cell, the selected memory cell passes the verification step.

[0095] In this implementation, during the first programming cycle PL1, after the first programming voltage Vpgm1 is applied to the selected word line connected to the selected memory cell, a first verification voltage V_vfy1 to a seventh verification voltage V_vfy7 can be sequentially applied. In this case, the first verification voltage V_vfy1 can be applied to the memory cell with the first programming state as the target programming state, thus initiating the first verification step. A second verification voltage V_vfy2 can be applied to the memory cell with the second programming state as the target programming state, thus continuing the first verification step. A third verification voltage V_vfy3 can be applied to the memory cell with the third programming state as the target programming state, thus continuing the first verification step. A fourth verification voltage V_vfy4 can be applied to the memory cell with the fourth programming state as the target programming state, thus continuing the first verification step. A fifth verification voltage V_vfy5 can be applied to the memory cell with the fifth programming state as the target programming state, thus continuing the first verification step. A sixth verification voltage V_vfy6 can be applied to a memory cell with a sixth programming state as the target programming state, thus allowing the first verification step to continue. A seventh verification voltage V_vfy7 can be applied to a memory cell with a seventh programming state as the target programming state, thus completing the first verification step. The number of verification voltages is not limited to this embodiment.

[0096] It can be determined that the memory cell that has undergone the verification steps using the corresponding verification voltages V_vfy1 to V_vfy7 has a threshold voltage corresponding to the target programming state. The memory cell that has passed the first verification step can be programmed disabled in the second programming cycle PL2. The programming disable voltage can be applied to the bit line connected to the programmed disable memory cell.

[0097] It can be determined that memory cells that fail the verification steps using the corresponding verification voltages V_vfy1 to V_vfy7 do not have the threshold voltage corresponding to the target programming state. Memory cells that fail the first verification step can execute the second programming cycle PL2.

[0098] In the second programming cycle PL2, the memory device 100 may apply a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, to the selected word line connected to the selected memory cell. Thereafter, the memory device 100 may perform the verification steps of the second programming cycle PL2 in the same manner as the verification steps of the first programming cycle PL1.

[0099] Then, the memory device 100 can execute subsequent programming cycles up to a preset number of times in the same manner as the second programming cycle PL2.

[0100] In this implementation, the programming operation may fail if it is not completed within a preset number of programming cycles. The programming operation can proceed if it is completed within the preset number of programming cycles. Whether the programming operation is complete can be determined based on whether all selected memory cells have passed the verification step. If all selected memory cells have passed the verification step, subsequent programming cycles may not be executed.

[0101] In this implementation, the programming voltage can be determined based on the Incremental Step Pulse Programming (ISPP) method. The level of the programming voltage can be gradually increased or decreased as programming cycles PL1 to PLn are repeated. Under the control of the memory controller 200, the number of times the programming voltage is applied, the voltage level of the programming voltage, the voltage application time, etc., used in each programming cycle can be determined in various ways.

[0102] Figure 6 This is a diagram illustrating the triple-verified programming (TPGM) operation of a memory device.

[0103] exist Figure 6 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (the number of cells).

[0104] Reference Figure 6Triple Verification Programming (TPGM) can be an operation that uses at least three verification voltages at the verification step to identify the threshold voltage of a memory cell. Specifically, TPGM can be an operation that uses at least three verification voltages to verify whether the threshold voltage of the memory cell has reached the threshold voltage corresponding to the target programming state. The at least three verification voltages may include a first pre-verification voltage Vvfyp1, a second pre-verification voltage Vvfyp2, and a main verification voltage Vvfym.

[0105] Figure 6 The programming state P shown can be Figure 4 Any one of the first programming states PV1 to the seventh programming state PV7 shown. Figure 5 Each of the verification voltages V_vfy1 to V_vfy7 shown may include a first pre-verification voltage Vvfyp1, a second pre-verification voltage Vvfyp2, and a main verification voltage Vvfym.

[0106] In this implementation, the primary verification voltage Vvfym can be a voltage higher than the second pre-verification voltage Vvfyp2. The second pre-verification voltage Vvfyp2 can be a voltage higher than the first pre-verification voltage Vvfyp1.

[0107] In this implementation, the primary verification voltage Vvfym can be a threshold voltage corresponding to the programming state P. For example, the primary verification voltage Vvfym can be... Figure 5 The verification voltages shown are any one of V_vfy1 to V_vfy7.

[0108] In an implementation, the threshold voltage of the memory cell at the end of the programming voltage application step in any of the multiple programming cycles can be the threshold voltages of the first cell (Cell1) through the fourth cell (Cell4). At the verification step performed after the programming voltage application step, the memory device 100 can perform a TPGM operation to identify the threshold voltage of the memory cell using a first pre-verification voltage Vvfyp1, a second pre-verification voltage Vvfyp2, and a main verification voltage Vvfym. At the verification step, the memory device 100 can perform a TPGM operation to verify whether the threshold voltage of the memory cell has reached the threshold voltage corresponding to the target programming state using the first pre-verification voltage Vvfyp1, the second pre-verification voltage Vvfyp2, and the main verification voltage Vvfym.

[0109] In this implementation, the first cell, Cell1, may have a threshold voltage lower than or equal to the first pre-verification voltage Vvfyp1. The second cell, Cell2, may have a threshold voltage higher than the first pre-verification voltage Vvfyp1 and lower than or equal to the second pre-verification voltage Vvfyp2. The third cell, Cell3, may have a threshold voltage higher than the second pre-verification voltage Vvfyp2 and lower than or equal to the main verification voltage Vvfym. The fourth cell, Cell4, may have a threshold voltage higher than the main verification voltage Vvfym.

[0110] In the implementation, it is assumed that the target programming state of the first cell (Cell1) to the fourth cell (Cell4) is... Figure 6 The programming state P is shown. That is, the threshold voltage of the first cell (Cell1) to the fourth cell (Cell4) can be increased to the threshold voltage corresponding to the programming state P.

[0111] Compared to the threshold voltages of Cells 2 through 4, the threshold voltage of Cell 1 may need to be further increased to reach the threshold voltage corresponding to the programming state P. Here, Cell 1 can be a programming cell (PGM cell). Compared to the threshold voltages of Cells 3 and 4, the threshold voltage of Cell 2 may need to be further increased to reach the threshold voltage corresponding to the programming state P. Here, Cell 2 can be a TPGM1 cell. The threshold voltage of Cell 3 still needs to be further increased to reach the threshold voltage corresponding to the programming state P, but by less than Cells 1 and 2. Here, Cell 3 can be a TPGM2 cell. Because the threshold voltage of Cell 4 already has the threshold voltage corresponding to the programming state P, this threshold voltage is not increased further. Here, Cell 4 can be a disable cell.

[0112] Figure 7 This is a diagram illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0113] Reference Figure 7 The memory device 100 may include a programming operation executor 150, a programming operation controller 160, and a memory cell array 110. The memory cell array 110 can be coupled with... Figure 2 The memory cell array 110 shown is configured and operated in the same manner. The programming operation controller 160 can be implemented as... Figure 2 A component of the control logic 130 shown. The programmable operation actuator 150 may include... Figure 2 The voltage generator 122, address decoder 121, and page buffer group 123 are shown and can be operated by components.

[0114] The programming operation controller 160 may include a word line controller 161 and a bit line controller 162. The word line controller 161 may control the programming operation actuator 150 such that a programming voltage is applied to the selected word line during a programming operation. In one embodiment, the word line controller 161 may control the programming operation actuator 150 such that a memory cell to be programmed is selected during a programming operation. Thereafter, the word line controller 161 may control the programming operation actuator 150 such that a programming voltage to be applied to the selected word line connected to the selected memory cell and a pass voltage to be applied to the unselected word line are generated.

[0115] Bit line controller 162 can control programming operation executor 150 to generate voltages to be applied to bit lines connected to memory cells during programming operations. In one embodiment, bit line controller 162 can control programming operation executor 150 to generate voltages to be applied to bit lines connected to memory cells according to usage. Figure 6 The verification voltages Vvfyp1, Vvfyp2, and Vvfym are used to identify the threshold voltages of the memory cells to generate the voltages to be applied to the bit lines connected to the memory cells, respectively. For example, the bit line controller 162 can control the programming operation executor 150 to generate the voltages to be applied to the bit lines connected to the programming unit PGM cell, the bit lines connected to the TPGM1 cell, the bit lines connected to the TPGM2 cell, and the bit lines connected to the disable cell, respectively.

[0116] The programming operation executor 150 can perform programming operations on a plurality of memory cells included in the memory cell array 110 under the control of the programming operation controller 160. In one embodiment, during the programming operation, the programming operation executor 150 can apply a generated programming voltage to the selected word line of the selected memory cell connected to the plurality of memory cells under the control of the programming operation controller 160. The programming operation executor 150 can also apply a generated pass voltage to the unselected word line under the control of the programming operation controller 160.

[0117] In other embodiments, the programming operation executor 150 may apply generated bit line voltages to corresponding bit lines connected to memory cells under the control of the programming operation controller 160 during programming operations. For example, the programming operation executor 150 may apply bit line voltages to corresponding bit lines connected to programming units (PGM units), TPGM1 units, TPGM2 units, and disable units during programming operations.

[0118] Figure 8 This is a diagram illustrating the operation of a page buffer circuit according to an embodiment of the present disclosure.

[0119] Figure 8The page buffer circuit 800 shown can be Figure 2 Any one of the page buffers PBi included in the page buffer group 123 shown.

[0120] Reference Figure 8 The page buffer circuit 800 may include a precharger 810, a discharger 820, and a latch assembly 830. The precharger 810, discharger 820, and latch assembly 830 may be connected between bit line BL and data line DL. Bit line BL may be connected to a memory cell.

[0121] The precharger 810 can precharge the voltage of bit line BL. In one embodiment, when the memory cell connected to bit line BL is TPGM1, the precharger 810 can apply a first precharge voltage to bit line BL. The first precharge voltage can be a voltage higher than ground. When the memory cell connected to bit line BL is TPGM2, the precharger 810 can apply a second precharge voltage higher than the first precharge voltage to bit line BL. When the memory cell connected to bit line BL is a disable cell, the precharger 810 can apply a programming disable voltage higher than the second precharge voltage to bit line BL. The programming disable voltage can be a power supply voltage.

[0122] The discharger 820 can precharge the voltage of bit line BL to ground voltage. In an embodiment, when the memory cell connected to bit line BL is a programming unit (PGM cell), the discharger 820 can apply ground voltage to bit line BL.

[0123] The latch component 830 can store the result of identifying the threshold voltage of the memory cell using the verification voltage by sensing the potential of the bit line BL.

[0124] Figure 9 This is a diagram illustrating the steps of applying the programming voltage during the programming operation of a memory device.

[0125] Reference Figure 9 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application step (PGM step) and a verification step (verification step).

[0126] The programming voltage application step (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a pre-charge period, a programming pulse (Pgm pulse) period, and a discharge period.

[0127] The time period from t1 to t2 can be a pre-charge period. The pre-charge period can be the time during which bit line BL is pre-charged. In an embodiment, memory device 100 may apply a ground voltage Gnd to bit line BL (PGM cell) connected to a programming unit during the pre-charge period. Memory device 100 may apply a programming disable voltage VCC to bit line BL (disable cell) connected to a disable unit during the pre-charge period. Memory device 100 may apply a first pre-charge voltage Vm1 to bit line BL (TPGM1 cell) connected to TPGM1 cell during the pre-charge period. Memory device 100 may apply a second pre-charge voltage Vm2 to bit line BL (TPGM2 cell) connected to TPGM2 cell during the pre-charge period.

[0128] The time period from t2 to t3 can be a programmed pulse period (Pgm pulse). Figure 5 The programming voltages Vpgm1 to Vpgmn shown can be applied to the selected word line Sel_WL connected to the selected memory cell during the programming pulse period (Pgm pulse). The programming pulse period (Pgm pulse) can be the period during which data is stored in the selected memory cell. For example, during the programming pulse period (Pgm pulse), the memory device 100 can apply a voltage Vpass to the selected word line Sel_WL connected to the selected memory cell for a predetermined period of time, and then apply the programming voltage Vpgm to the selected word line Sel_WL. The memory device 100 can maintain the voltage of the bit line BL (PGM cell) connected to the programming cell at the ground voltage Gnd during the programming pulse period (Pgm pulse). The memory device 100 can maintain the voltage of the bit line BL (inhibit cell) connected to the inhibit cell at the programming inhibit voltage VCC during the programming pulse period (Pgm pulse). The memory device 100 can maintain the voltage of the bit line BL (TPGM1 cell) connected to the TPGM1 cell at a first precharge voltage Vm1 during the programming pulse (Pgm pulse) period. The memory device 100 can also maintain the voltage of the bit line BL (TPGM2 cell) connected to the TPGM2 cell at a second precharge voltage Vm2 during the programming pulse (Pgm pulse) period.

[0129] The period from t3 to t4 can be a discharge period. During the discharge period, the memory device 100 can apply a ground voltage Gnd to the selected word line Sel_WL. During the discharge period, the memory device 100 can apply the ground voltage Gnd to the bit line BL (PGM cell) connected to the programming unit, the bit line BL (inhibit cell) connected to the inhibit unit, the bit line BL (TPGM1 cell) connected to the TPGM1 cell, and the bit line BL (TPGM2 cell) connected to the TPGM2 cell.

[0130] Figure 10 This is a diagram illustrating the coupling phenomenon between adjacent bit lines that occurs during programming operations of a memory device.

[0131] Figure 10 It is used to additionally describe the above references Figure 9 A diagram illustrating the case where bit lines BL (TPGM1 cell) connected to TPGM1 cell and bit lines BL (TPGM2 cell) connected to TPGM2 cell are adjacent to each other during the pre-charge period of the described programming voltage application step (PGM step). Therefore, in Figure 10 In the middle, the pair will be omitted. Figure 9 The component description is the same as the component in the text.

[0132] Reference Figure 10 The time period from t1 to t2 can be a pre-charge period. During the pre-charge period, the memory device 100 can apply a first pre-charge voltage Vm1 to the bit line BL (TPGM1 cell) connected to the TPGM1 cell. During the pre-charge period, the memory device 100 can apply a second pre-charge voltage Vm2 to the bit line BL (TPGM2 cell) connected to the TPGM2 cell.

[0133] In this scenario, if the bit line BL (TPGM1 cell) closest to the bit line connected to the TPGM1 cell is also connected to the bit line BL (TPGM2 cell), coupling due to parasitic capacitance between the bit lines may occur. During the precharge period, the voltage on the bit line BL (TPGM1 cell) connected to the TPGM1 cell may increase to a third precharge voltage Vm1', which is higher than the first precharge voltage Vm1, due to the second precharge voltage Vm2 applied to the bit line BL (TPGM2 cell) connected to the TPGM2 cell. That is, because the voltage on the bit line BL (TPGM1 cell) connected to the TPGM1 cell increases due to coupling, the TPGM1 cell may have a threshold voltage lower than the threshold voltage corresponding to the target programming state during programming operations.

[0134] Figure 11 This is a diagram illustrating the programming voltage application step in the programming operation of a memory device according to an embodiment of the present disclosure.

[0135] exist Figure 11 In the middle, the pair will be omitted. Figure 9 and Figure 10 The component description is the same as the component in the text.

[0136] Reference Figure 11The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application step (PGM step) and a verification step (verification step).

[0137] The programming voltage application step (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a pre-charge period, a programming pulse (Pgm pulse) period, and a discharge period.

[0138] The period from t1 to t2 can be a pre-charging period. The pre-charging period can be the period during which bit line BL is pre-charged.

[0139] The memory device 100 may apply a fourth precharge voltage Vst to the bit line BL (TPGM2 cell) connected to the TPGM2 cell during a time period from t1 to t12. The fourth precharge voltage Vst may be the voltage difference between the second precharge voltage Vm2 and the first precharge voltage Vm1. The memory device 100 may also apply a fifth precharge voltage Gnd, lower than the fourth precharge voltage Vst, to the bit line BL (TPGM1 cell) connected to the TPGM1 cell during the time period from t1 to t12. The fifth precharge voltage Gnd may be a ground voltage.

[0140] The memory device 100 may apply a first pre-charge voltage Vm1 to the bit line BL (TPGM1 cell) connected to the TPGM1 cell during a time period from t12 to t2. The memory device 100 may also apply a second pre-charge voltage Vm2 to the bit line BL (TPGM2 cell) connected to the TPGM2 cell during the same time period. The second pre-charge voltage Vm2 may be a voltage higher than the first pre-charge voltage Vm1. In an embodiment, the difference between the magnitude of the first pre-charge voltage Vm1 and the magnitude of the fifth pre-charge voltage Gnd may be equal to the difference between the magnitude of the second pre-charge voltage Vm2 and the magnitude of the fourth pre-charge voltage Vst. For example, the range by which the voltage of the bit line BL (TPGM1 cell) connected to the TPGM1 cell increases from the magnitude of the fifth pre-charge voltage Gnd to the magnitude of the first pre-charge voltage Vm1 may be equal to the range by which the voltage of the bit line BL (TPGM2 cell) connected to the TPGM2 cell increases from the magnitude of the fourth pre-charge voltage Vst to the magnitude of the second pre-charge voltage Vm2.

[0141] In this disclosure, after the fourth precharge voltage Vst is first applied to the bit line BL (TPGM2 cell) connected to the TPGM2 cell, the second precharge voltage Vm2 is applied to it, thereby reducing or preventing the coupling phenomenon between the bit line BL (TPGM1 cell) connected to the TPGM1 cell and the bit line BL (TPGM2 cell) connected to the TPGM2 cell.

[0142] Figure 12 This is a flowchart illustrating the programming operations of a memory device according to an embodiment of the present disclosure.

[0143] Reference Figure 12 In step S1201, the memory device 100 may apply at least three verification voltages to word lines commonly connected to memory cells. In an embodiment, the memory device 100 may use at least three verification voltages to identify the threshold voltage of a memory cell. For example, at least three verification voltages may be used to identify each memory cell as any one of a programming cell (PGM cell), a TPGM1 cell, a TPGM2 cell, and a disable cell.

[0144] In step S1203, the memory device 100 may, during the precharge period including the programming voltage application step, first apply a precharge voltage to the second bit line connected to the second memory cell before applying a precharge voltage to the first bit line connected to the first memory cell. In an embodiment, the first memory cell may be a TPGM1 cell. The second memory cell may be a TPGM2 cell. Thereafter, the voltage applied to the first bit line may be a lower voltage than the precharge voltage initially applied to the second bit line. For example, the voltage applied to the first bit line may be ground.

[0145] In step S1205, the memory device 100 may change the corresponding voltages applied to the first bit line and the second bit line. In an embodiment, the voltage applied to the second bit line may be higher than the voltage applied to the first bit line.

[0146] Figure 13 This is an example Figure 1 A diagram of the memory controller.

[0147] Figure 13 The memory controller 1300 can be Figure 1 The memory controller 200.

[0148] Reference Figure 13 The memory controller 1300 may include a processor 1310, RAM 1320, error correction circuitry 1330, host interface 1340, ROM 1350, and flash memory interface 1360.

[0149] The processor 1310 can control the overall operation of the memory controller 1300. The RAM 1320 can be used as a buffer memory, cache memory, or working memory of the memory controller 1300.

[0150] Error correction circuit 1330 can perform error correction. Error correction circuit 1330 can perform error correction code (ECC) encoding based on data to be written to memory device 100 via flash interface 1360. ECC-encoded data can be transmitted to memory device 100 via flash interface 1360. Error correction circuit 1330 can perform error correction decoding (ECC decoding) on ​​data received from memory device 100 via flash interface 1360. In embodiments, error correction circuit 1330 can be included as a component of flash interface 1360 within flash interface 1360.

[0151] ROM 1350 can store various types of information for the operation of memory controller 1300 in the form of firmware.

[0152] The memory controller 1300 can communicate with external devices (e.g., host 300, application processor, etc.) via host interface 1340.

[0153] The memory controller 1300 can communicate with the memory device 100 via the flash interface 1360. The memory controller 1300 can send commands, addresses, control signals, etc., to the memory device 100 and receive data from the memory device 100 via the flash interface 1360. In this example, the flash interface 1360 may include a NAND interface.

[0154] Figure 14 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0155] Reference Figure 14 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0156] Memory controller 2100 is coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and a host computer. Memory controller 2100 can run firmware for controlling memory device 2200. Memory controller 2100 can be configured as described above. Figure 1 The memory controller 200 described herein is implemented in the same manner. The memory device 2200 can be implemented in the same manner as described above. Figure 1The memory device 100 described is implemented in the same manner.

[0157] In some implementations, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0158] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on a specific communication protocol. In embodiments, the memory controller 2100 can communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) protocol. In embodiments, connector 2300 can be defined by at least one of the aforementioned communication protocols.

[0159] In an implementation, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), or spin-transfer torque magnetic RAM (STT-MRAM).

[0160] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC or eMMC), an SD card (SD, mini SD, micro SD or SDHC), or universal flash memory (UFS).

[0161] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system that applies an embodiment of the memory system according to the present disclosure.

[0162] Reference Figure 15The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0163] According to embodiments of this disclosure, the SSD controller 3210 can perform the functions described above. Figure 1 The functions of the memory controller 200 are described.

[0164] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to signals received from host 3100. In implementations, the signals can be signals based on the interface between host 3100 and SSD 3200. For example, the signals can be signals defined through at least one of various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0165] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with power from host 3100 and can be charged. When there is no stable power supply from host 3100, auxiliary power supply 3230 can supply power to SSD 3200. In implementations, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located in the motherboard and can supply auxiliary power to SSD 3200.

[0166] Buffer memory 3240 serves as a buffer for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0167] Figure 16 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure.

[0168] Reference Figure 16 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0169] Application processor 4100 can run components, operating systems (OS), or user programs included in user system 4000. In some implementations, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-chip (SoC).

[0170] The memory module 4200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) and then provided as a single semiconductor package.

[0171] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi. In an implementation, network module 4300 may be included in application processor 4100.

[0172] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device using, for example, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as a memory card or external drive for user system 400.

[0173] In an implementation, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 100 described herein operates in the same manner. The storage module 4400 can operate in the same manner as described above. Figure 1 The memory system 50 described operates in the same manner.

[0174] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0175] According to embodiments of the present disclosure, a memory device capable of mitigating or preventing coupling between adjacent bit lines during programming operations, and a method for operating the memory device, are provided.

[0176] Cross-reference to related applications

[0177] This application claims priority to Korean Patent Application No. 10-2021-0114203, filed with the Korean Intellectual Property Office on August 27, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Memory unit; A programming operation executor performs a verification operation and a programming voltage application operation, wherein the verification operation is performed to verify whether a threshold voltage of the memory cell has reached a threshold voltage corresponding to a target programming state using a first verification voltage, a second verification voltage higher than the first verification voltage, and a third verification voltage higher than the second verification voltage; and wherein the programming voltage application operation is performed based on the result of the verification operation to apply a programming voltage to a word line commonly connected to the memory cell; and A programming operation controller controls the programming operation actuator such that, during the programming voltage application operation, before applying a precharge voltage to a first bit line connected to a first memory cell having a threshold voltage higher than the first verification voltage and lower than or equal to the second verification voltage, a precharge voltage is first applied to a second bit line connected to a second memory cell having a threshold voltage higher than the second verification voltage and lower than or equal to the third verification voltage.

2. The memory device according to claim 1, wherein, The programming operation controller controls the programming operation executor such that the voltages applied to the first bit line and the second bit line during a first time period and the voltages applied to the first bit line and the second bit line during a second time period following the first time period are respectively changed.

3. The memory device according to claim 2, wherein, The programming operation controller controls the programming operation executor such that a voltage lower than the voltage applied to the second bit line during the first time period is applied to the first bit line during the first time period.

4. The memory device according to claim 3, wherein, The voltage lower than the voltage applied to the second bit line during the first time period is the ground voltage.

5. The memory device according to claim 2, wherein, The voltage applied to the second bit line during the first time period is the difference between the voltage applied to the second bit line during the second time period and the voltage applied to the first bit line during the second time period.

6. The memory device according to claim 2, wherein, The voltage applied to the first bit line during the second time period is lower than the voltage applied to the second bit line during the second time period and higher than the ground voltage.

7. The memory device according to claim 2, wherein, The programming operation controller controls the programming operation actuator to apply the programming voltage to the word line after the first time period and the second time period have ended.

8. The memory device according to claim 1, wherein, The second bit line is the bit line that is closest to the first bit line.

9. The memory device according to claim 1, wherein, The third verification voltage is a threshold voltage corresponding to the target programming state of the memory cell.

10. The memory device according to claim 2, wherein, The difference between the magnitude of the voltage applied to the first bit line during the second time period and the magnitude of the voltage applied to the first bit line during the first time period is equal to the difference between the magnitude of the voltage applied to the second bit line during the second time period and the magnitude of the voltage applied to the second bit line during the first time period.

11. A method of operating a memory device, the memory device performing a programming operation to store data in a memory cell, the method comprising the steps of: At least three verification voltages are applied to a word line that is commonly connected to the memory cell; Based on the threshold voltage of the memory cell identified using the at least three verification voltages, a precharge voltage is applied to the bit lines respectively connected to the memory cell at different time points; as well as After applying the pre-charge voltage, a programming voltage is applied to the word line. The step of applying the precharge voltage to the bit line before applying the programming voltage to the word line includes the following steps: applying the precharge voltage to the second bit line of the first memory cell connected to the second memory cell before applying the precharge voltage to the first bit line of the first memory cell connected to the memory cell. The second memory cell has a threshold voltage between the two highest of the at least three verification voltages.

12. The method according to claim 11, wherein, The step of applying the precharge voltage to the bit line before applying the programming voltage to the word line further includes the following steps: Change the voltage applied to the first bit line and the second bit line respectively.

13. The method according to claim 11, wherein, The first memory cell has a threshold voltage between the third highest verification voltage and the second highest verification voltage among the at least three verification voltages.

14. The method according to claim 13, wherein, The second memory cell is the memory cell closest to the first memory cell.

15. The method according to claim 11, wherein, The step of applying the precharge voltage to the second bit line before applying the precharge voltage to the first bit line includes the following steps: While applying the pre-charge voltage to the second bit line, a voltage lower than the voltage applied to the second bit line is applied to the first bit line.

16. The method according to claim 15, wherein, The voltage lower than the voltage applied to the second bit line is the ground voltage.

17. The method according to claim 12, wherein, In the step of changing the voltages applied to the first bit line and the second bit line respectively, the voltage applied to the first bit line is lower than the voltage applied to the second bit line.

18. The method according to claim 12, wherein, The magnitude of the precharge voltage applied to the second bit line is the difference between the magnitude of the voltage applied to the second bit line and the magnitude of the voltage applied to the first bit line during the step of changing the voltages applied to the first bit line and the second bit line respectively.

19. The method according to claim 11, wherein, The highest of the at least three verification voltages is the threshold voltage corresponding to the target programming state of the memory cell.

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