Semiconductor structure and method of fabrication

Abstract

The application provides a semiconductor structure and a preparation method. The semiconductor structure comprises a supporting substrate, a rewiring layer, a packaging structure, a dielectric layer and a metal layer. The rewiring layer is on the supporting substrate. The packaging structure is on the rewiring layer. The packaging structure comprises a metal column and a right trapezoidal plastic sealing layer. The first end of the metal column is electrically connected with the rewiring layer. The right trapezoidal plastic sealing layer exposes the second end of the metal column. The dielectric layer is on the surface of the right trapezoidal plastic sealing layer. The metal layer is on the dielectric layer and is electrically connected with the second end of the metal column. The right trapezoidal plastic sealing layer with inclined side surfaces can form a uniformly distributed metal layer, thereby improving product quality and yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging and relates to a semiconductor structure and its preparation method. Background Technology

[0002] Lower cost, greater reliability, faster speed, and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing feature size. Currently, commonly used packaging methods include wafer-level packaging (WLP) and package-on-package (POP). Among them, three-dimensional packaging uses the wafer as the processing object, packaging and testing the entire wafer, and then dicing it into individual chips. It has the advantages of small size, fast processing speed, and low cost, and has become one of the more advanced packaging technologies, gaining widespread application.

[0003] In 3D packaging, the chip needs to be attached to the wafer and then encapsulated by filling with molding compound. After that, a metal conductive layer that is electrically connected to the chip is prepared for electrical lead-out. However, when the metal conductive layer is prepared by sputtering, the metal conductive layer at the edge often has uneven distribution, which affects the quality of the final product.

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure and preparation method to solve the problem of uneven distribution of the metal conductive layer in the prior art.

[0006] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0007] Provide a supporting substrate;

[0008] A redistribution layer is formed on the supporting substrate;

[0009] An encapsulation structure is formed on the redistribution layer. The encapsulation structure includes a metal pillar and a molding compound, wherein a first end of the metal pillar is electrically connected to the redistribution layer, and the molding compound covers the metal pillar.

[0010] The surface of the plastic sealant is ground to expose the second end of the metal pillar;

[0011] The side surface of the molding compound is cut to form a trapezoidal molding compound;

[0012] A patterned dielectric layer is formed on the surface of the trapezoidal molding layer;

[0013] A metal layer is formed on the dielectric layer by sputtering, and the metal layer is electrically connected to the second end of the metal pillar.

[0014] Optionally, the cutting process includes laser cutting.

[0015] Optionally, the angle between the side of the formed trapezoidal molding layer and the surface of the redistribution layer ranges from 30° to 60°.

[0016] Optionally, a separation layer is provided between the support substrate and the redistribution layer, the separation layer including a photothermal conversion layer.

[0017] Optionally, the formed package structure further includes a chip, and the chip is electrically connected to the redistribution layer or the chip is electrically connected to the metal layer.

[0018] Optionally, the method further includes surface treatment of the surface of the packaging structure, and the surface treatment includes surface plasma treatment.

[0019] The present invention also provides a semiconductor structure, the semiconductor structure comprising:

[0020] Support substrate;

[0021] A redistribution layer, the redistribution layer being located on the support substrate;

[0022] A packaging structure is located on the redistribution layer. The packaging structure includes a metal pillar and a trapezoidal molding layer, wherein a first end of the metal pillar is electrically connected to the redistribution layer, and the trapezoidal molding layer exposes a second end of the metal pillar.

[0023] A graphical dielectric layer located on the surface of the trapezoidal molding layer;

[0024] A metal layer is located on the dielectric layer and is electrically connected to the second end of the metal pillar.

[0025] Optionally, the angle between the side of the trapezoidal molding layer and the surface of the redistribution layer ranges from 30° to 60°.

[0026] Optionally, a separation layer is provided between the support substrate and the redistribution layer, the separation layer including a photothermal conversion layer.

[0027] Optionally, the package structure further includes a chip, and the chip is electrically connected to the redistribution layer or the chip is electrically connected to the metal layer.

[0028] As described above, the semiconductor structure and fabrication method of the present invention include a supporting substrate, a redistribution layer, a packaging structure, a dielectric layer, and a metal layer. The redistribution layer is located on the supporting substrate; the packaging structure is located on the redistribution layer and includes metal pillars and a trapezoidal molding compound, with a first end of the metal pillars electrically connected to the redistribution layer and the trapezoidal molding compound exposing the second end of the metal pillars; the dielectric layer is located on the surface of the trapezoidal molding compound; and the metal layer is located on the dielectric layer and electrically connected to the second end of the metal pillars. The present invention, through the trapezoidal molding compound having inclined sides, can form a uniformly distributed metal layer, improving product quality and yield. Attached Figure Description

[0029] Figure 1 The diagram shows a process flow chart for fabricating a semiconductor structure according to an embodiment of the present invention.

[0030] Figure 2 The diagram shown is a schematic representation of the structure after the encapsulation structure is formed in an embodiment of the present invention.

[0031] Figure 3 The diagram shows the structure after the surface of the encapsulation layer has been ground in an embodiment of the present invention.

[0032] Figure 4 The diagram shown is a schematic representation of the structure after the trapezoidal plastic sealant layer is formed by cutting in an embodiment of the present invention.

[0033] Figure 5 The diagram shown is a schematic representation of the structure after the formation of the graphical medium layer in an embodiment of the present invention.

[0034] Figure 6 The diagram shows the structure after the metal layer is formed by sputtering in an embodiment of the present invention.

[0035] Component designation explanation

[0036] 100 Supporting substrate

[0037] 200 Separation Layer

[0038] 300 Rerouting Layer

[0039] 400 package structure

[0040] 401 Metal Column

[0041] 402 chip

[0042] 403 sealing layer

[0043] 500 dielectric layer

[0044] 600 metal layer Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please see Figures 1-6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. The illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] like Figure 1 This embodiment provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0048] S1: Provides a supporting substrate;

[0049] S2: A redistribution layer is formed on the supporting substrate;

[0050] S3: An encapsulation structure is formed on the redistribution layer, the encapsulation structure including a metal pillar and a molding compound, wherein a first end of the metal pillar is electrically connected to the redistribution layer, and the molding compound covers the metal pillar;

[0051] S4: Grind the surface of the plastic sealant to expose the second end of the metal pillar;

[0052] S5: The side surface of the trapezoidal molding layer is cut to form a trapezoidal molding layer;

[0053] S6: A patterned dielectric layer is formed on the surface of the encapsulation layer;

[0054] S7: A metal layer is formed on the dielectric layer by sputtering, and the metal layer is electrically connected to the second end of the metal pillar.

[0055] The semiconductor structure fabrication method described in this embodiment can form a trapezoidal molding layer by cutting the side of the molding layer, thereby forming a uniformly distributed metal layer in the subsequent sputtering process, improving product quality and yield.

[0056] The following is in conjunction with the appendix Figures 2-6 The specific steps for preparing the semiconductor structure in this embodiment will be further explained.

[0057] First, refer to Figure 2 Step S1 is executed, providing a support substrate 100, which may include a silicon substrate, a glass substrate, etc. The thickness and size of the support substrate 100 can be selected according to the process requirements. For example, the support substrate 100 can be a wafer-level 8-inch or 12-inch support substrate, and the thickness can be a micrometer-level or centimeter-level support substrate. The specific type is not excessively limited here.

[0058] Next, step S2 is performed to form a redistribution layer 300 on the support substrate 100.

[0059] Specifically, the redistribution layer 300 may include a dielectric layer and a metal wiring layer located within the dielectric layer to facilitate electrical outgoing. No excessive restrictions are placed here regarding the material and specific structure of the redistribution layer 300.

[0060] As an example, a separation layer 200 may also be present between the support substrate 100 and the redistribution layer 300, the separation layer 200 including a photothermal conversion layer.

[0061] Specifically, the separation layer 200 serves to provide an adhesive material layer to bond the support substrate 100 to the redistribution layer 300, facilitating subsequent peeling of the support substrate 100 through processes such as tearing or light irradiation. In this embodiment, the separation layer 200 is preferably the photothermal conversion layer, meaning that subsequent processes can separate the support substrate 100 from the redistribution layer 300 by heating the photothermal conversion layer using lasers or similar methods, thus providing a convenient separation method. However, the type of separation layer 200 is not limited to this and can be selected according to specific needs.

[0062] Next, step S3 is performed to form an encapsulation structure 400 on the redistribution layer 300. The encapsulation structure 400 includes a metal pillar 401 and a molding compound 403. The first end of the metal pillar 401 is electrically connected to the redistribution layer 300, and the molding compound 403 covers the metal pillar 401.

[0063] Specifically, the metal pillar 401 enables double-sided electrical leads of the packaging structure 400, that is, the metal pillar 401 enables electrical connection between the redistribution layer 300 and the subsequent metal layer 600. The specific structure of the packaging structure 400 is not excessively limited here.

[0064] As an example, the formed package structure 400 may also include a chip 402, and the chip 402 is electrically connected to the redistribution layer 300.

[0065] Specifically, such as Figure 2 In this embodiment, the packaging structure 400 includes the chip 402, and the electrical leads of the chip 402 are located away from the redistribution layer 300. However, this is not a limitation; the electrical leads of the chip 402 can also be electrically connected to the redistribution layer 300. The molding compound 403 covers the metal pillar 401 and the chip 402 to protect them and provide a fixed support. The molding compound 403 can be made of commonly used epoxy resin, and the method of forming the molding compound 403 can include molding, vacuum lamination, and spin coating. The material and forming method of the molding compound 403 are not limited here. The type of chip 402 is not limited here.

[0066] Next, refer to Figure 3 Step S4 is executed to grind the surface of the plastic sealant 403 to expose the second end of the metal pillar 403.

[0067] Specifically, the thickness of the packaging structure 400 can be reduced through a polishing process, resulting in a flat surface and exposing the electrical leads in the packaging structure 400. The polishing process may include CMP, physical polishing, or a combination of both. In this embodiment, the electrical leads of the packaging structure 400 include the second end of the metal pillar 401 and the electrical leads of the chip 402, but the electrical leads of the packaging structure 400 are not limited to these.

[0068] Next, as Figure 4 Step S5: Cut the side of the molding layer 403 to form a trapezoidal molding layer.

[0069] Specifically, in this embodiment, the cutting process uses laser cutting, but it is not limited to this and can be selected according to needs. Through this cutting process, the molding compound 403 located at the edge can be removed, forming a trapezoidal molding compound with inclined sides. This facilitates the formation of a uniformly distributed metal layer 600 in subsequent processes, thereby improving product quality. The angle between the side of the formed trapezoidal molding compound and the surface of the redistribution layer 300 can be in the range of 30° to 60°, such as 30°, 45°, 60°, etc., preferably 45°, to further improve the continuity of the sputtering process and prepare a metal layer 600 with higher uniformity.

[0070] Next, as Figure 5 Step S6: A patterned dielectric layer 500 is formed on the surface of the trapezoidal molding layer.

[0071] Specifically, the material of the dielectric layer 500 may include PI polyimide, silicon oxide, silicon nitride, etc., and the method for preparing the dielectric layer 500 may be coating, exposure, and development. No excessive limitations are made here regarding the material, structure, and preparation method of the dielectric layer 500.

[0072] Next, as Figure 6 Step S7: The metal layer 600 is formed on the dielectric layer 500 by sputtering, and the metal layer 600 is electrically connected to the second end of the metal pillar 401.

[0073] Specifically, in this embodiment, the metal layer 600 is electrically connected to the metal pillar 401 and to the chip 402. The metal layer 600 may include Ti metal, Cu metal, etc., and the specific material is not excessively limited here. Since the molding compound 403 is a trapezoidal molding compound with an inclined surface, the sputtering continuity can be improved during the sputtering process, forming a coating with uniform thickness and improving the uniformity of the metal layer 600.

[0074] In this embodiment, since the separation layer 200 is a photothermal conversion layer, it may also include, for example, using laser irradiation, separating the support substrate 100 from the redistribution layer 300 to obtain a reusable support substrate 100, thereby reducing costs, and elements electrically connected to the redistribution layer 300 may be formed on the exposed surface of the redistribution layer 300, and the specific types of the elements are not excessively limited here.

[0075] Furthermore, before forming the patterned dielectric layer 500, a surface treatment step may be included to form the metal layer 600 having good electrical connection with the electrical leads on the surface of the packaging structure 400, and the surface treatment may include, for example, surface plasma treatment.

[0076] like Figure 6 This embodiment also provides a semiconductor structure, which includes a supporting substrate 100, a redistribution layer 300, a package structure 400, a dielectric layer 500, and a metal layer 600. The redistribution layer 300 is located on the supporting substrate 100; the package structure 400 is located on the redistribution layer 300, and the package structure 400 includes metal pillars 401 and a trapezoidal molding compound, with a first end of the metal pillars 401 electrically connected to the redistribution layer 300, and the trapezoidal molding compound exposing the second end of the metal pillars 401; the dielectric layer 500 is located on the surface of the trapezoidal molding compound; and the metal layer 600 is located on the dielectric layer 500, and the metal layer 600 is electrically connected to the second end of the metal pillars 401.

[0077] In this embodiment, the semiconductor structure can be prepared using the above-described preparation method, but is not limited to this method. Therefore, the preparation of the semiconductor structure and the selection of materials can be referred to the above-described preparation method.

[0078] In this embodiment, the trapezoidal molding layer located on the support substrate 100 can form a uniformly distributed metal layer 600 during subsequent sputtering, thereby improving product quality and yield.

[0079] As an example, the angle between the side of the trapezoidal molding layer and the surface of the redistribution layer ranges from 30° to 60°.

[0080] Specifically, by cutting, the plastic sealant layer located at the edge can be removed to form the trapezoidal plastic sealant layer with inclined sides, which facilitates the formation of the uniformly distributed metal layer 600 in subsequent processes, thereby improving product quality. The angle between the side of the formed trapezoidal plastic sealant layer and the surface of the redistribution layer 300 can be in the range of 30° to 60°, such as 30°, 45°, 60°, etc.

[0081] As an example, a separation layer 200 is provided between the support substrate 100 and the redistribution layer 300. The separation layer 200 includes a photothermal conversion layer, through which the support substrate 100 and the redistribution layer 300 can be easily separated, so as to facilitate the reuse of the support substrate 100 and reduce costs.

[0082] As an example, the package structure 400 also includes a chip 402, and the chip 402 is electrically connected to the redistribution layer 300 or the metal layer 600.

[0083] Specifically, in this embodiment, the packaging structure 400 includes the chip 402, and the electrical leads of the chip 402 are far away from the redistribution layer 300. However, it is not limited to this. The electrical leads of the chip 402 can also be electrically connected to the redistribution layer 300. This is not an excessive limitation.

[0084] In summary, the semiconductor structure and fabrication method of the present invention include a supporting substrate, a redistribution layer, a packaging structure, a dielectric layer, and a metal layer. The redistribution layer is located on the supporting substrate; the packaging structure is located on the redistribution layer and includes metal pillars and a trapezoidal molding compound, with a first end of the metal pillars electrically connected to the redistribution layer and the trapezoidal molding compound exposing the second end of the metal pillars; the dielectric layer is located on the surface of the trapezoidal molding compound; and the metal layer is located on the dielectric layer and electrically connected to the second end of the metal pillars. The present invention, through the trapezoidal molding compound with inclined sides, can form a uniformly distributed metal layer, improving product quality and yield. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide a supporting substrate; A redistribution layer is formed on the supporting substrate; An encapsulation structure is formed on the redistribution layer. The encapsulation structure includes a metal pillar and a molding compound, wherein a first end of the metal pillar is electrically connected to the redistribution layer, and the molding compound covers the metal pillar. The surface of the plastic sealant is ground to expose the second end of the metal pillar; The side surface of the molding compound is cut to form a trapezoidal molding compound; A patterned dielectric layer is formed on the surface of the trapezoidal molding layer; A metal layer is formed on the dielectric layer by sputtering, and the metal layer is electrically connected to the second end of the metal pillar.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The cutting process includes laser cutting.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The angle between the side of the formed trapezoidal molding layer and the surface of the redistribution layer ranges from 30° to 60°.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: A separation layer is provided between the supporting substrate and the redistribution layer, the separation layer including a photothermal conversion layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formed package structure also includes a chip, and the chip is electrically connected to the redistribution layer or the chip is electrically connected to the metal layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: It also includes surface treatment of the surface of the packaging structure, and the surface treatment includes surface plasma treatment.

7. A semiconductor structure, characterized in that, The semiconductor structure includes: Support substrate; A redistribution layer, the redistribution layer being located on the support substrate; A packaging structure is located on the redistribution layer. The packaging structure includes a metal pillar and a trapezoidal molding layer, wherein a first end of the metal pillar is electrically connected to the redistribution layer, and the trapezoidal molding layer exposes a second end of the metal pillar. A graphical dielectric layer located on the surface of the trapezoidal molding layer; A metal layer is located on the dielectric layer and is electrically connected to the second end of the metal pillar.

8. The semiconductor structure according to claim 7, characterized in that: The angle between the side of the trapezoidal molding layer and the surface of the redistribution layer ranges from 30° to 60°.

9. The semiconductor structure according to claim 7, characterized in that: A separation layer is provided between the supporting substrate and the redistribution layer, the separation layer including a photothermal conversion layer.

10. The semiconductor structure according to claim 7, characterized in that: The packaging structure also includes a chip, and the chip is electrically connected to the redistribution layer or the chip is electrically connected to the metal layer.

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