A packaging method for improving voiding of TSV process

Abstract

The application discloses a packaging method for improving TSV process hollow virtual soldering, comprising the following steps: providing a chip wafer, an adhesive film and a packaging substrate; the chip wafer is provided with a through hole, and a metal bump is arranged on the front surface of the chip wafer and corresponds to the position of the through hole; an opening corresponding to the metal bump of the chip wafer is formed on the adhesive film; the adhesive film is attached to the front surface of the chip wafer, and the opening on the adhesive film wraps the metal bump on the chip wafer; the chip wafer after the film is attached is thinned and scribed, and a single chip wafer after the film is attached is cut; the single chip wafer after the film is attached is attached to the packaging substrate through the adhesive film, and then welding is performed, and the adhesive film fills the gap between the metal bumps on the chip. The method has low process difficulty, can effectively improve the problems of virtual soldering, hollow and NCF glue overflow in the product soldering packaging process, and can greatly improve the product quality and production capacity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and in particular to a packaging method for improving voids and poor solder joints in TSV process. Background Technology

[0002] In 3DS TSV processes, NCF films are typically used to fill the gaps between the chip bumps. In existing technologies, because NCF films cover the chip bump surfaces, different temperatures and soldering times need to be set according to the characteristics of the bumps and the NCF film during thermoforming. This is especially problematic when stacking TCB layers, where optimal temperature settings are difficult to achieve, easily leading to issues such as cold solder joints, voids, and NCF adhesive overflow, resulting in product failure or reliability issues. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a packaging method for improving the problem of voids and poor solder joints in the TSV process. This method has low process difficulty and can effectively improve the problems of poor solder joints, voids, and NCF glue overflow during the product soldering and packaging process, thereby greatly improving product quality and production capacity.

[0004] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution:

[0005] A packaging method for improving voids and poor solder joints in TSV process includes the following steps:

[0006] S1 provides a chip wafer, a film, and a packaging substrate; the chip wafer has through holes, and metal bumps are provided on the front side of the chip wafer corresponding to the positions of the through holes;

[0007] S2, an opening corresponding to the metal bumps on the chip wafer is formed on the adhesive film;

[0008] S3, apply the adhesive film to the front side of the chip wafer, and the openings in the adhesive film cover the metal bumps on the chip wafer;

[0009] S4, the chip wafer after film application is thinned and diced to obtain a single film-coated chip;

[0010] S5, a single film-mounted chip is attached to the packaging substrate through the adhesive film, and then soldered. The adhesive film fills the gap between the metal bumps on the chip.

[0011] Furthermore, the shape of the openings on the adhesive film is adapted to the shape of the metal bumps.

[0012] Furthermore, the metal bump is spherical, and the openings on the adhesive film are spherical holes.

[0013] Furthermore, the aperture of the opening on the adhesive film is larger than the diameter of the metal bump.

[0014] Furthermore, the adhesive film is an NCF film.

[0015] Furthermore, in step S5, the welding process is a reflow welding process.

[0016] The beneficial effects of this invention are:

[0017] This invention features a specially designed adhesive film with openings at the locations corresponding to each metal bump on the chip wafer. After the adhesive film is applied to the chip wafer, the openings completely cover the metal bumps. After a single chip is mounted onto the packaging substrate using the FCA process, the chip is connected to the substrate by soldering, with the adhesive film filling the spaces between the metal bumps. This method eliminates the need to set different soldering temperatures and times based on the characteristics of the metal bumps and NCF (Non-Fluorescent Adhesive), enabling the simultaneous soldering of multiple chips to the entire substrate. This improves production efficiency and capacity, and effectively addresses issues such as poor solder joints, voids, or NCF adhesive overflow, thus enhancing product quality. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the adhesive film in the method of the present invention.

[0019] Figure 2 This is a schematic diagram of step S3 in the method of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure of the chip wafer and the adhesive film. Detailed Implementation

[0021] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0022] Example

[0023] This invention provides a packaging method for improving voids and poor solder joints in TSV process, comprising the following steps:

[0024] S1 provides a chip wafer 1, a film 2, and a packaging substrate; the chip wafer 1 has multiple through holes 11, and multiple metal bumps 12 are provided on the front side of the chip wafer 1 corresponding to the positions of the through holes;

[0025] In this embodiment, the adhesive film 2 is an NCF film;

[0026] S2, an opening 21 corresponding to the metal bump 12 of the chip wafer 1 is formed on the adhesive film 2, such as... Figure 1As shown;

[0027] The shape of the opening on the adhesive film 2 is adapted to the shape of the metal bump 12; in this embodiment, the metal bump 12 is spherical, and the opening 21 on the adhesive film 2 is a spherical hole. Furthermore, the diameter of the opening 21 on the adhesive film 2 is larger than the diameter of the metal bump 12. In this embodiment, the opening diameter D of the adhesive film 2 = the diameter of the metal bump + 10 μm.

[0028] S3, apply adhesive film 2 to the front side of chip wafer 1; as shown Figure 2 As shown, when applying the adhesive film, ensure that the openings of the adhesive film 2 correspond one-to-one with the metal bumps 12 on the chip wafer 1; after the adhesive film 2 is applied, the openings 21 on the adhesive film 2 will cover the metal bumps 12 on the chip wafer 1, as shown. Figure 3 As shown;

[0029] S4, the chip wafer 1 after film coating is thinned and diced to obtain a single film-coated chip;

[0030] S5, a single film-mounted chip is attached to the packaging substrate through the adhesive film, and then reflow soldering is performed. The adhesive film 2 fills the gap between the metal bumps 12 on the chip.

[0031] Compared with the prior art, the method of the present invention has the following advantages:

[0032] This invention features a specially designed adhesive film with openings at the locations corresponding to each metal bump on the chip wafer. After the adhesive film is applied to the chip wafer, the openings completely cover the metal bumps. After a single chip is mounted onto the packaging substrate using the FCA process, the chip is connected to the substrate by soldering, with the adhesive film filling the spaces between the metal bumps. This method eliminates the need to set different soldering temperatures and times based on the characteristics of the metal bumps and NCF (Non-Fluorescent Adhesive), enabling the simultaneous soldering of multiple chips to the entire substrate. This improves production efficiency and capacity, and effectively addresses issues such as poor solder joints, voids, or NCF adhesive overflow, thus enhancing product quality.

[0033] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A packaging method for improving voids and poor solder joints in TSV process, characterized in that, Includes the following steps: S1 provides a chip wafer, a film, and a packaging substrate; the chip wafer has through holes, and metal bumps are provided on the front side of the chip wafer corresponding to the positions of the through holes; S2, an opening corresponding to the metal bumps of the chip wafer is formed on the adhesive film; the shape of the opening on the adhesive film is adapted to the shape of the metal bump; the metal bump is spherical, and the opening on the adhesive film is a spherical hole; the diameter of the opening on the adhesive film is larger than the diameter of the metal bump; S3, apply the adhesive film to the front side of the chip wafer, and the openings in the adhesive film cover the metal bumps on the chip wafer; S4, the chip wafer after film application is thinned and diced to obtain a single film-coated chip; S5, a single film-mounted chip is attached to the packaging substrate through the adhesive film, and then soldered. The adhesive film fills the gap between the metal bumps on the chip.

2. The packaging method for improving void solder joints in TSV process according to claim 1, characterized in that, The adhesive film is an NCF film.

3. The packaging method for improving voids and poor solder joints in TSV process according to claim 1, characterized in that, In step S5, the welding process is reflow welding.

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