Semiconductor device, method for manufacturing semiconductor device, and power conversion device

Abstract

Provided is a technology capable of suppressing the generation of cracks in a waterproof layer and suppressing a decrease in the withstand voltage of a semiconductor device when a semiconductor element is mounted by a press-bonding process. The semiconductor device has a semiconductor substrate provided with a cell region, a separation region, and a terminal region, the cell region being an active region through which a current flows, the separation region being provided on an outer circumferential side than the cell region and limiting the generation of an electric field when the withstand voltage is maintained, the terminal region having a guard ring region provided on an outer circumferential side than the separation region and a remaining region provided on an outer circumferential side than the guard ring region and limiting the extension of a depletion layer when the withstand voltage is maintained, an insulating layer covering the upper surface of the semiconductor substrate in the separation region and the terminal region, a surface electrode provided on the upper surface of the semiconductor substrate and a portion of the upper surface of the insulating layer in the cell region and the separation region, and a waterproof layer covering a portion of the insulating layer exposed from the surface electrode. The waterproof layer is provided separately from the surface electrode.

Description

Technical Field

[0001] This invention relates to semiconductor devices, methods for manufacturing semiconductor devices, and power conversion devices. Background Technology

[0002] It has been confirmed that the withstand voltage of a semiconductor device decreases due to moisture intrusion from the end portion of the semiconductor element mounted on the semiconductor device. As a structure to solve this problem, for example, Patent Document 1 discloses a structure in which a silicon nitride film with low moisture permeability (equivalent to a waterproof layer) is wrapped around an insulating layer and a metal electrode (equivalent to a surface electrode) disposed at the end region of the semiconductor substrate to prevent corrosion of the metal electrode caused by moisture.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-175937

[0004] However, in semiconductor devices that mount semiconductor elements via a pressure bonding process, such as silver sintering bonding, where the semiconductor element is pressed against the substrate, the metal electrode is prone to deformation during the pressing process. If the metal electrode deforms, cracks may form at the portion of the silicon nitride film that overlaps the metal electrode, failing to follow the deformation of the thin silicon nitride film. These cracks then propagate into the insulating layer covering the end region. Consequently, moisture can penetrate through these cracks extending into the insulating layer, causing a decrease in the withstand voltage of the semiconductor device. Summary of the Invention

[0005] Therefore, the object of the present invention is to provide a technology that can suppress the formation of cracks in the waterproof layer and suppress the decrease in the withstand voltage of the semiconductor device when installing semiconductor components through a pressure bonding process.

[0006] The semiconductor device of the present invention comprises: a semiconductor substrate having a cell region, a separation region, and an end region, wherein the cell region is an active region through which current flows, the separation region is disposed further outward than the cell region to limit the generation of an electric field during withstand voltage holding, the end region having a guard ring region and a remaining region, the guard ring region being disposed further outward than the separation region, and the remaining region being disposed further outward than the guard ring region to limit the extension of a depletion layer during withstand voltage holding; an insulating layer covering the upper surface of the semiconductor substrate at the separation region and the end region; a surface electrode disposed at the cell region and the separation region on a portion of the upper surface of the semiconductor substrate and the upper surface of the insulating layer; and a waterproof layer covering the portion of the insulating layer exposed from the surface electrode, the waterproof layer being disposed separately from the surface electrode.

[0007] The effects of the invention

[0008] According to the present invention, the waterproof layer is disposed separately from the surface electrode, and the portion of the waterproof layer that overlaps the surface electrode does not become the starting point for cracks in the waterproof layer. Therefore, when mounting a semiconductor device through a pressure bonding process, cracks in the waterproof layer can be suppressed. This, in turn, suppresses voltage drop in the semiconductor device. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view showing the end structure of the semiconductor element in the semiconductor device according to Embodiment 1.

[0010] Figure 2 This is a diagram showing an example of the simulation results of the electric field distribution related to the end configuration of the semiconductor element in the semiconductor device according to Embodiment 1.

[0011] Figure 3 This is a schematic cross-sectional view illustrating the manufacturing process of the semiconductor device according to Embodiment 1.

[0012] Figure 4 This is a block diagram showing the structure of a power conversion system in which the power conversion device described in Embodiment 2 is applied. Detailed Implementation

[0013] The embodiments will now be described with reference to the accompanying drawings. The features described in the following embodiments are illustrative, and not all features are essential. Furthermore, in the following description, the same structural elements are labeled with the same or similar reference numerals in multiple embodiments; the description primarily focuses on the different structural elements. Additionally, in the following description, the specific positions and orientations such as "upper," "lower," "left," "right," "front," or "back" do not necessarily correspond to the actual positions and orientations in the implementation.

[0014] <Implementation Method 1>

[0015] Hereinafter, Embodiment 1 will be described using the accompanying drawings. Figure 1 This schematically illustrates the semiconductor device 50 according to Embodiment 1 (see reference). Figure 3 (e) is a cross-sectional view of the end structure of the semiconductor element 10. Figure 2 This refers to the semiconductor device 50 related to Embodiment 1 (see reference). Figure 3 (e) is a figure showing an example of the simulation results of the electric field distribution related to the end structure of the semiconductor element 10.

[0016] like Figure 1 As shown, semiconductor device 50 (reference) Figure 3(e) The semiconductor element 10 has a semiconductor substrate 1, an insulating layer 11, a surface electrode 12, a waterproof layer 13, and a protective film 14.

[0017] Semiconductor substrate 1 is an n-type semiconductor substrate, and is defined with cell region 2, separation region 3, and end region 6. Cell region 2 is an active region through which current flows, and a p-type semiconductor portion is provided in cell region 2. Separation region 3 is provided at a location further outward than cell region 2, adjacent to and covering cell region 2, and is a region that limits the generation of electric field during voltage withstand. Additionally, a p-type semiconductor portion is provided in separation region 3.

[0018] The end region 6 has a guard ring region 4 and a remaining region 5. The guard ring region 4 is provided at a location further outward than the separation region 3, adjacent to and covering the separation region 3, and a plurality of discrete p-type semiconductor portions are provided in the guard ring region 4.

[0019] The remaining region 5 is located further outward from the guard ring region 4, adjacent to and covering the guard ring region 4. The remaining region 5 is made of n-type semiconductors and is a region that limits the extension of the depletion layer during voltage withstand.

[0020] Unit region 2 is provided with, for example, a semiconductor switching element with a built-in diode (not shown) and at least one of a diode. Hereinafter, a structure in which a semiconductor switching element with a built-in diode is provided in unit region 2 will be described as an example. In such a structure, unit region 2 is energized when the semiconductor switching element is in the ON state, and the separation region 3 and the end region 6 maintain the withstand voltage when the semiconductor switching element is in the OFF state.

[0021] Semiconductor substrate 1 is formed from an n-type semiconductor made primarily of silicon carbide. The p-type semiconductor section is formed, for example, by ion implantation of aluminum into a semiconductor made primarily of silicon carbide, causing the aluminum to diffuse.

[0022] The insulating layer 11 is configured to cover the upper surface of the semiconductor substrate 1 in the separation region 3 and the end region 6. Specifically, when viewed from above, the insulating layer 11 is disposed on the upper surface of the semiconductor substrate 1 in the regions of the separation region 3 and the end region 6 that exclude the edge portion.

[0023] Surface electrodes 12 are disposed on a portion of the upper surface of the semiconductor substrate 1 and the upper surface of the insulating layer 11 in the cell region 2 and the separation region 3. Specifically, surface electrodes 12 are disposed on a portion of the upper surface of the semiconductor substrate 1 in the cell region 2 and the separation region 3, and on a portion of the upper surface of the insulating layer 11 in the separation region 3. Furthermore, surface electrodes 12 are disposed in such a manner that they extend from the upper surface of the semiconductor substrate 1 to a portion of the upper surface of the insulating layer 11.

[0024] The waterproof layer 13 is disposed on the upper surface of the exposed portion of the insulating layer 11 from the surface electrode 12, such that it covers the portion of the insulating layer 11 exposed from the surface electrode 12. Furthermore, the waterproof layer 13 is disposed separately from the surface electrode 12 without adhering to it. That is, the waterproof layer 13 is formed only on the upper surface of the insulating layer 11, which remains substantially undeformed when the semiconductor element 10 is pressed during the pressure bonding process.

[0025] The protective film 14 is disposed on the upper surface of the semiconductor substrate 1 in a portion of the cell region 2, the separation region 3 and the end region 6 in such a way that it covers a portion of the surface electrode 12, the waterproof layer 13 and the insulating layer 11.

[0026] like Figure 2 As shown, when a voltage is applied to the semiconductor element 10, the depletion layer D extends from the cell region 2 toward the outer periphery. However, no electric field is generated in the separation region 3 at this time, but an electric field is generated in the guard ring region 4, which is provided with a plurality of discrete p-type semiconductors. An electric field is generated in the remaining region 5, located further outward from the guard ring region 4, up to the region where the depletion layer D extends. Essentially, the remaining region 5 is set to be longer than the intended extension length of the depletion layer D under actual operating voltage. That is, no electric field is generated in the remaining region 5 from the middle.

[0027] Therefore, as long as moisture intrusion can be suppressed in at least the area where the depleted layer D extends in the protective ring region 4 and the remaining region 5, the semiconductor element 10 can function effectively. Thus, even when the waterproof layer 13 is separated from the surface electrode 12, the semiconductor element 10 can still function effectively, thereby ensuring the reliability of the semiconductor element 10.

[0028] The insulating layer 11 is made primarily of silicon oxide film, for example, and the protective film 14 is made primarily of polyimide or polyamide, for example. The waterproof layer 13 is made primarily of silicon nitride film, for example. Sometimes, a method is used to impart a certain degree of conductivity to the silicon nitride film to equalize the electric field distribution in the protective ring region 4; however, in this embodiment, the silicon nitride film used for waterproofing is preferably non-conductive.

[0029] When forming the waterproof layer 13, for example, if the film is formed in at least two stages, the waterproof function of the waterproof layer 13 can be further improved. This is because even if pores are generated during the first film formation, they will be filled during the second and subsequent film formation stages.

[0030] like Figure 1 As shown, one end of the waterproof layer 13 faces the portion that separates from the surface electrode 12 at the separation region 3 of the semiconductor substrate 1, and the other end of the waterproof layer 13 faces the remaining region 5 of the semiconductor substrate 1. In this way, by covering a portion of the insulating layer 11 that faces the region including the end extending in the direction of the depletion layer D, the waterproof layer 13 can suppress moisture intrusion into the high electric field region, thereby improving the lifetime in the THB (Temperature Humidity Bias) test. Here, the direction in which the depletion layer D extends refers to... Figure 1 To the right of the center. Furthermore, one end of the waterproof layer 13 is capable of... Figure 2 It is separated from the surface electrode 12 within the range indicated by the bidirectional arrow 15.

[0031] Furthermore, the waterproof layer 13 is positioned such that, when viewed from above, it terminates further inward than the edge of the insulating layer 11. When the waterproof layer 13 extends beyond the edge of the insulating layer 11 when viewed from above, it overlaps the edge of the insulating layer 11, creating a localized thinning of the waterproof layer 13. During the pressure bonding process of mounting the semiconductor element 10, this thinning of the waterproof layer 13 could become the starting point of a crack. However, since the waterproof layer 13 terminates further inward than the edge of the insulating layer 11 when viewed from above, this thinning of the waterproof layer 13 is avoided, thus preventing the formation of a crack starting point during the pressure bonding process of the waterproof layer 13.

[0032] Next, use Figure 3 The manufacturing process of semiconductor device 50 is described. Figure 3 (a) to (e) are schematic cross-sectional views illustrating the manufacturing process of the semiconductor device 50 according to Embodiment 1.

[0033] To improve the reliability of the semiconductor element 10 when operating at high temperatures, the case of bonding the semiconductor element 10 by sintering is considered. First, as... Figure 3 As shown in (a), an insulating substrate 16 is prepared with circuit patterns 16b and 16c respectively on the back and surface of the insulating layer 16a, and a bonding material 17 is disposed on the upper surface of the circuit pattern 16c. For example, a bonding material made primarily of silver or copper is used as the bonding material 17.

[0034] Next, as Figure 3As shown in (b), a semiconductor element 10 is placed on an insulating substrate 16 via a bonding material 17, and sintering is performed by applying pressure at a high temperature in a subsequent process, namely a pressure bonding process.

[0035] like Figure 3 As shown in (c), in order to prevent damage to the semiconductor element 10 during the pressure bonding process, a cushioning material 19 such as a Teflon (registered trademark) sheet is placed between the pressure tool 18 and the semiconductor element 10.

[0036] like Figure 3 As shown in (d), after the electrical and thermal connections between the insulating substrate 16 and the semiconductor element 10 are achieved through sintering bonding in the pressure bonding process, as Figure 3 As shown in (e), a large current can be applied by connecting the wire bond 21 to the electrode (not shown) on the surface of the semiconductor element 10.

[0037] Then, the housing 20, which is integrally formed with terminals (not shown) for electrical connection with the outside, is joined to the circuit pattern 16c. The interior of the housing 20 is filled with an encapsulation material 22 such as gel, and the semiconductor element 10 is surrounded by the encapsulation material 22, thereby completing the semiconductor device 50 with improved anti-fouling properties.

[0038] Next, the problems when the waterproof layer 13 is attached to the surface electrode 12 and the effects of the semiconductor device 50 according to Embodiment 1 will be explained.

[0039] When a high bias voltage is applied to the semiconductor device 50 under high humidity conditions, moisture sometimes penetrates the packaging material 22 and reaches the surface of the semiconductor element 10 from the external environment in the protection ring region 4 where an electric field is generated.

[0040] Compared to semiconductor devices primarily made of silicon, semiconductor devices 10 primarily made of silicon carbide typically have a narrower guard ring region 4 and a higher peak electric field generated on the insulating layer 11. Therefore, moisture easily moves in the guard ring region 4, and when moisture penetration occurs, the properties of the p-type semiconductor portion are prone to change. The problem is that if moisture reaching the portion of the insulating layer 11 opposite to the guard ring region 4 penetrates the insulating layer 11, the properties of the p-type semiconductor portion in the guard ring region 4 change, causing a decrease in the withstand voltage of the semiconductor device 50.

[0041] To address this issue, a method exists where a waterproof layer 13, primarily composed of a silicon nitride film that is less permeable to moisture compared to a silicon oxide film, protects the insulating layer 11. However, when the semiconductor element 10 is mounted during a pressure bonding process by pressing it onto the surface of the semiconductor element 10, cracks develop in the waterproof layer 13, which rests on materials such as the surface electrode 12 that are easily deformed by pressure. These cracks extend into the insulating layer 11, covering the end region 6. Consequently, moisture can penetrate through these cracks extending into the insulating layer 11, causing a decrease in the withstand voltage of the semiconductor device 50.

[0042] In contrast, the semiconductor device 50 according to Embodiment 1 includes: a semiconductor substrate 1 having a cell region 2, a separation region 3, and an end region 6, wherein the cell region 2 is an active region through which current flows, the separation region 3 is disposed on the outer periphery of the cell region 2 to limit the generation of an electric field during withstand voltage holding, the end region having a guard ring region 4 and a remaining region 5, the guard ring region 4 being disposed on the outer periphery of the separation region 3 and the remaining region 5 being disposed on the outer periphery of the guard ring region 4 to limit the extension of the depletion layer D during withstand voltage holding; an insulating layer 11 covering the upper surface of the semiconductor substrate 1 at the separation region 3 and the end region 6; a surface electrode 12 disposed on the upper surface of the semiconductor substrate 1 and a portion of the upper surface of the insulating layer 11 at the cell region 2 and the separation region 3; and a waterproof layer 13 covering the portion of the insulating layer 11 exposed from the surface electrode 12, the waterproof layer 13 being disposed separately from the surface electrode 12.

[0043] Therefore, since the waterproof layer 13 is disposed separately from the surface electrode 12, and there is no portion of the waterproof layer 13 that overlaps the surface electrode 12 and becomes the starting point for cracks in the waterproof layer 13, cracking of the waterproof layer 13 can be suppressed during the mounting of the semiconductor element 10 via a pressure bonding process. This, in turn, suppresses the voltage drop of the semiconductor device 50. In summary, the durability of the semiconductor device 50 can be improved.

[0044] Furthermore, the waterproof layer 13 is positioned such that, when viewed from above, it terminates further inward than the edge of the insulating layer 11. Therefore, areas where the waterproof layer 13 becomes thinner are avoided, preventing the initiation of cracks during pressure bonding of the waterproof layer 13. This suppresses the formation of cracks in the waterproof layer 13 originating from the step of the insulating layer 11.

[0045] In addition, the semiconductor element 10 also has a protective film 14 covering the upper surface of the semiconductor substrate 1 at the cell region 2, the separation region 3, and the end region 6. The protective film 14 covers the surface electrode 12, the waterproof layer 13, and the insulating layer 11. Therefore, damage to the waterproof layer 13 and the insulating layer 11 can be suppressed during the pressure bonding process.

[0046] In addition, the waterproof layer 13 contains a silicon nitride film, which further enhances the waterproof function of the waterproof layer 13.

[0047] Furthermore, the protective film 14 contains polyimide or polyamide, making it more easily deformable than the waterproof layer 13 and the insulating layer 11 during the pressure bonding process. This deformation of the protective film 14 allows it to absorb the stress corresponding to the pressure applied to the semiconductor element 10. Consequently, cracking of the waterproof layer 13 and the insulating layer 11 can be suppressed.

[0048] In addition, the waterproof layer 13 is formed in at least two stages. Therefore, even if small holes are generated during the first film formation, they will be filled during the second and subsequent film formations, thus further improving the waterproof function of the waterproof layer 13.

[0049] <Implementation Method 2>

[0050] This embodiment applies the semiconductor device 50 described in Embodiment 1 to a power conversion device. The application of the semiconductor device 50 in Embodiment 1 is not limited to a specific power conversion device; however, as Embodiment 2, the application of the semiconductor device 50 in Embodiment 1 to a three-phase inverter will be described.

[0051] Figure 4 This is a block diagram showing the structure of a power conversion system in which the power conversion device 200 according to Embodiment 2 is applied.

[0052] Figure 4 The power conversion system shown consists of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source, supplying DC power to the power conversion device 200. The power source 100 can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power source 100 can be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0053] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, which converts the DC power supplied from the power source 100 into AC power and supplies AC power to the load 300. The power conversion device 200 is as follows: Figure 4 As shown, it includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203 that outputs control signals to control the drive circuit 202.

[0054] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0055] The details of the power conversion device 200 will be described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements on and off, it converts the DC power supplied from the power source 100 into AC power, which is then supplied to the load 300. Various specific circuit structures exist for the main conversion circuit 201, but the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be constructed from six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. Each switching element of the main conversion circuit 201 uses the semiconductor device 50 described in Embodiment 1. The six switching elements are connected in series in pairs to form upper and lower bridge arms, and each upper and lower bridge arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower bridge arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0056] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signals from the control circuit 203 (described later), drive signals that set the switching elements to the ON state and drive signals that set the switching elements to the OFF state are output to the control electrodes of each switching element. When the switching element is maintained in the ON state, the drive signal is a voltage signal greater than or equal to the threshold voltage of the switching element (ON signal); when the switching element is maintained in the OFF state, the drive signal is a voltage signal less than or equal to the threshold voltage of the switching element (OFF signal).

[0057] Control circuit 203 controls the switching elements of main conversion circuit 201 to supply the desired power to load 300. Specifically, based on the power to be supplied to load 300, the time (on-time) for each switching element of main conversion circuit 201 to be in the on state is calculated. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements in accordance with the output voltage. Furthermore, control commands (control signals) are output to drive circuit 202 to output on signals to the switching elements that should be in the on state at each time and off signals to the switching elements that should be in the off state. Drive circuit 202 outputs the on or off signals as drive signals to the control electrodes of each switching element according to the control signals.

[0058] In the power conversion device 200 according to this embodiment, the semiconductor device 50 according to embodiment 1 is used as the switching element of the main conversion circuit 201. Therefore, even when the semiconductor device 10 is installed through a pressure bonding process, cracks in the waterproof layer 13 with low water permeability can be suppressed, and the pressure resistance of the semiconductor device 50 can be suppressed. As a result, the reliability of the power conversion device 200 can be suppressed.

[0059] In this embodiment, an example of applying the semiconductor device 50 according to Embodiment 1 in a two-level three-phase inverter has been described. However, the application of the semiconductor device 50 according to Embodiment 1 is not limited to this, and it can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but it can also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the semiconductor device 50 according to Embodiment 1 can also be applied to a single-phase inverter. In addition, when supplying power to DC loads, the semiconductor device 50 according to Embodiment 1 can also be applied to DC / DC converters and AC / DC converters.

[0060] Furthermore, the power conversion device that uses the semiconductor device 50 according to Embodiment 1 is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machine, induction heating cooker or contactless power supply system, and can also be used as a power regulator for solar power generation system, energy storage system, etc.

[0061] Furthermore, it is possible to freely combine the various implementation methods, or to appropriately modify or omit the various implementation methods.

[0062] Explanation of the label

[0063] 1 Semiconductor substrate, 2 Unit region, 3 Separation region, 4 Guard ring region, 5 Remaining region, 6 End region, 11 Insulating layer, 12 Surface electrode, 13 Waterproof layer, 14 Protective film, 50 Semiconductor device, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, D Depletion layer.

Claims

1. A semiconductor device comprising: A semiconductor substrate is defined with a cell region, a separation region, and an end region. The cell region is an active region through which current flows. The separation region is disposed on the outer periphery of the cell region to limit the generation of an electric field during voltage withstand. The end region has a guard ring region and a remaining region. The guard ring region is disposed on the outer periphery of the separation region, and the remaining region is disposed on the outer periphery of the guard ring region to limit the extension of the depletion layer during voltage withstand. An insulating layer that covers the upper surface of the semiconductor substrate at the separation region and the end region; A surface electrode is disposed on the upper surface of the semiconductor substrate and a portion of the upper surface of the insulating layer in the unit region and the separation region; as well as A waterproof layer that covers the portion of the insulating layer exposed from the surface electrode. The waterproof layer is configured to be separate from the surface electrode and to cover the upper side of at least the area where the depletion layer extends in the remaining area.

2. The semiconductor device according to claim 1, wherein, The waterproof layer is positioned such that, when viewed from above, it terminates at a point further inward than the edge of the insulating layer.

3. The semiconductor device according to claim 1, wherein, It also has a protective film that covers the upper surface of the semiconductor substrate at the cell region, the separation region, and the end region. The protective film covers the surface electrode, the waterproof layer, and the insulating layer.

4. The semiconductor device according to claim 2, wherein, It also has a protective film that covers the upper surface of the semiconductor substrate at the cell region, the separation region, and the end region. The protective film covers the surface electrode, the waterproof layer, and the insulating layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The waterproof layer comprises a silicon nitride film.

6. The semiconductor device according to claim 3 or 4, wherein, The protective film contains polyimide or polyamide.

7. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor substrate comprises silicon carbide.

8. The semiconductor device according to claim 5, wherein, The semiconductor substrate comprises silicon carbide.

9. The semiconductor device according to claim 6, wherein, The semiconductor substrate comprises silicon carbide.

10. A method for manufacturing a semiconductor device, comprising manufacturing the semiconductor device according to any one of claims 1 to 9. The waterproof layer is formed in at least two stages.

11. A power conversion device, comprising: A main conversion circuit having a semiconductor device according to any one of claims 1 to 9, the main conversion circuit converting the input power and outputting it; A driving circuit that outputs a driving signal to the semiconductor device; as well as The control circuit outputs control signals to the drive circuit to control the drive circuit.

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