Polymer-coated semiconductor devices and hybrid bonding for forming semiconductor assemblies

Abstract

This application is directed to polymer-coated semiconductor devices and hybrid bonding of forming semiconductor assemblies. A semiconductor device assembly includes a first semiconductor device having a front side and a back side opposite the front side, a metal interconnect formed on the back side, and a polymer material deposited over the first semiconductor device to encapsulate the sidewall, the back side, and the metal interconnect. The first semiconductor device is planarized to expose the upper surface of the metal interconnect. The assembly further includes a second semiconductor device having a top side and a bottom side opposite the top side, a polymer material deposited over the second semiconductor device to encapsulate the sidewall and the bottom side. The second semiconductor device is stacked over the first device and hybrid bonded together such that each metal interconnect on the first semiconductor device back side is aligned with and electrically coupled to a corresponding metal interconnect on the second semiconductor device bottom side.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 239,839, filed on September 1, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to polymer-coated semiconductor devices, and more particularly to polymer-coated semiconductor devices and hybrid bonding for forming semiconductor assemblies. Background Technology

[0004] The trend toward manufacturing smaller electronic devices has led to a significant reduction in the thickness of semiconductor devices, which are densely packed with numerous thin films and materials. The sidewalls of these thin, densely packed semiconductor devices are susceptible to damage during several manufacturing processes before being packaged into a semiconductor device assembly. The following outlines some manufacturing processes that introduce cracks, debris, or particles into individual semiconductor devices, potentially damaging the packaged semiconductor device assembly. During the cleaning process to remove particles and residues from the semiconductor device, minor cracks and cavities can form along the semiconductor device sidewalls. Furthermore, during the dicing process to form individual semiconductor devices and the pick-up process to remove individual semiconductor devices from the carrier substrate, particles can be introduced into the semiconductor device sidewalls and can form minor cracks or debris along the semiconductor device sidewalls. Additionally, during the stacking process to form semiconductor device assemblies or packages, debris or cracks can form along the semiconductor device sidewalls. After these processes are completed, the stacked semiconductor devices are bonded together through processes such as hybrid bonding, where particles generated can lead to debonding, individual semiconductor device failure, and / or further damage to the development of sidewall cracks in the semiconductor devices and ultimately, failure of the entire stacked packaged semiconductor device assembly. Summary of the Invention

[0005] In one aspect, this application relates to a semiconductor device assembly comprising: a first semiconductor device having a front side and a back side opposite to the front side, the first semiconductor device including: a first plurality of metal interconnects formed on the back side; a first polymer material deposited over the first semiconductor device to directly encapsulate the sidewalls, the back side, and the first plurality of metal interconnects, wherein the first polymer material is planarized to expose upper surfaces of the first plurality of metal interconnects; a second semiconductor device having a top side and a bottom side opposite to the top side, the second semiconductor device including: a second polymer material deposited over the second semiconductor device to directly encapsulate the sidewalls and the bottom side; and a third material deposited on the top side of the second semiconductor device having a second plurality of metal interconnects formed thereon; wherein the second semiconductor device is stacked over the first semiconductor device such that each of the second plurality of metal interconnects is aligned and electrically coupled to a corresponding one of the first plurality of metal interconnects; and wherein the first semiconductor device and the second semiconductor device are co-bonded together.

[0006] In another aspect, this application relates to a semiconductor device comprising: a front side and a back side opposite to the front side; a first plurality of metal interconnects formed on the back side; a first polymer material deposited over the semiconductor device to directly encapsulate the sidewalls, the back side, and the first plurality of metal interconnects; wherein the first polymer material is planarized to expose the upper surfaces of the first plurality of metal interconnects.

[0007] In another aspect, this application relates to a method of manufacturing a semiconductor device assembly, comprising: placing a device wafer comprising a plurality of semiconductor devices on a temporary carrier, each of the plurality of semiconductor devices having a front side facing the temporary carrier and a back side opposite to the front side; forming a first plurality of metal interconnects on the back side of each of the plurality of semiconductor devices; dicing the plurality of semiconductor devices to separate the semiconductor devices from each other and expose their sidewalls; depositing a first polymer material over the plurality of individualized semiconductor devices such that the polymer material directly encapsulates the sidewalls, the back side, and the first plurality of metal interconnects of each of the plurality of semiconductor devices; individualizing the encapsulated semiconductor devices from each other by removing portions of the first polymer material between adjacent semiconductor devices; and exposing the first plurality of metal interconnects of each of the plurality of semiconductor devices by planarizing the upper surface of the polymer material. Attached Figure Description

[0008] Figures 1A and 1B are simplified schematic cross-sectional and plan views of sidewall debris and cracks in a prior art processed semiconductor device.

[0009] Figures 2A to 2E This is a simplified schematic cross-sectional view of an exemplary semiconductor device processed using polymer materials according to embodiments of the present disclosure.

[0010] Figure 3 It is an exemplary packaged semiconductor device assembly according to embodiments of the present disclosure.

[0011] Figure 4 This is a schematic diagram illustrating an exemplary system comprising a semiconductor device assembly configured according to embodiments of the present disclosure.

[0012] Figure 5 This is a flowchart illustrating an exemplary method for manufacturing a semiconductor device assembly according to embodiments of the present disclosure.

[0013] While various modifications and alternatives are readily apparent from this disclosure, specific embodiments have been illustrated by way of example in the drawings and will be described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the particular forms disclosed. Rather, it is intended to cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure as defined by the appended claims. Detailed Implementation

[0014] The following describes several embodiments of semiconductor devices and specific details of associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein can be performed at the wafer level or the die level. Therefore, depending on the context, the term "substrate" can refer to a wafer-level substrate or a singlet-level die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0015] In this disclosure, numerous specific details are set forth to provide a comprehensive and feasible description of embodiments thereof. Those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. Well-known structures and / or operations typically associated with semiconductor devices may not be shown and / or described in detail to avoid obscuring other aspects of this disclosure. In general, it should be understood that various other devices, systems, and / or methods, in addition to the specific embodiments disclosed herein, may also be within the scope of this disclosure.

[0016] The term "semiconductor device assembly" can refer to an assembly of one or more semiconductor devices, semiconductor device packages, and / or substrates, which may include interposers, supports, and / or other suitable substrates. Semiconductor device assemblies can be manufactured in, but are not limited to, discrete package forms, strip or matrix forms, and / or wafer panel forms. The term "semiconductor device" generally refers to a solid-state device containing semiconductor material. A semiconductor device may include, for example, a semiconductor substrate, a wafer, a panel, or a single die from a wafer or substrate. A semiconductor device may further include one or more device layers deposited on a substrate. Semiconductor device may refer to a semiconductor die herein, but is not limited to semiconductor dies.

[0017] The term "semiconductor device package" can refer to an arrangement having one or more semiconductor devices incorporated into a common package. A semiconductor package may include a housing or enclosure that partially or completely encapsulates at least one semiconductor device. A semiconductor package may also include a substrate that carries one or more semiconductor devices. The substrate may be attached to the housing or enclosure or otherwise incorporated within the housing or enclosure.

[0018] Figures 1A and 1B are simplified schematic cross-sectional and plan views of sidewall debris and cracks in a prior art processed semiconductor device. Referring to Figure 1A, a first semiconductor device A and a second semiconductor device B are attached to a carrier substrate 1 by an adhesive 2 and undergo a cleaning process 11. The carrier substrate 1 may be, for example, a carrier disk or glass substrate that holds the semiconductor devices A and B during the cleaning process 11. While the cleaning process 11 removes most of the particles, residues, and surface contaminants that would damage the semiconductor devices A and B after the manufacturing process, the cleaning process 11 is abrasive and can etch into the silicon along the sidewalls 4 and 5 of semiconductor device A and the sidewalls 8 and 10 of semiconductor device B, damaging the silicon. For example, as illustrated in Figure 1A, the cleaning process 11 can cause chip damage 15 (e.g., debris, cracks, cavities, and microcracks) in the sidewalls 8 and 10 of semiconductor device B.

[0019] Referring to Figure 1B, the first semiconductor device C and the second semiconductor device D are attached to the carrier substrate 1 by adhesive 2 and undergo a die pick-up process 9. The carrier substrate 1 may be, for example, a carrier disk or a glass substrate, which holds the semiconductor devices C and D for individual die pick-up processes 9. During the die pick-up process 9, the sidewalls 4 and 5 of semiconductor device C and the sidewalls 8 and 10 of semiconductor device D are subjected to additional forces that can cause damage to the sidewalls of the semiconductor devices. For example, as illustrated in Figure 1A, the die pick-up process 9 applies sufficient force to the sidewalls 4 and 5 of semiconductor device B to cause chip degradation 19 (e.g., particle contamination, tearing, and cracking).

[0020] Sidewall damage can develop throughout the manufacturing process and extend into the bonding and packaging of semiconductor devices. Microcracks can develop into fissures, cavities into debris, and so on. This damage to each individual semiconductor device can jeopardize the entire stack of packaged semiconductor device assemblies, leading to assembly failure and significant cost and time losses due to a single damaged semiconductor device.

[0021] Embodiments of this disclosure address these and other issues by using materials and processes compatible with subsequent hybrid bonding operations to provide sidewall protection for individual semiconductor devices. By protecting the sidewalls of individual devices after individualization but before removing them from the carrier wafer, the aforementioned difficulties in propagating microcracks, debris, and cavities can be avoided and / or mitigated, as described in more detail below.

[0022] Figures 2A to 2E This is a simplified schematic cross-sectional view of an exemplary semiconductor device processed with a polymer material according to embodiments of the present disclosure. (See reference...) Figure 2A As can be seen, the back-side processing of device wafer 293 is complete. Device wafer 293 includes a front side 201 and a back side 202. The front side 201 can be attached to the carrier substrate 290 by adhesive 291. Device wafer 293 may include a material layer 292 formed on the front side 201 and a plurality of metal interconnects 208, 209, 228 and 229 formed in the material layer 292. Conductive (e.g., metal) through-silicon vias (TSVs) 210, 211, 230 and 231 are formed in device wafer 293, extending through the front side 201 and back side 202 of device wafer 293, connecting each of the plurality of metal interconnects 212, 213, 232 and 233 formed on the back side 202 to a corresponding one of the plurality of metal interconnects 208, 209, 228 and 229 formed on the front side 201.

[0023] Examples of metals that can be used to form TSVs 210, 211, 230, and 231, front-side metal interconnects 208, 209, 228, and 229, and back-side metal interconnects 212, 213, 232, and 233 include copper, aluminum, tungsten, tin, silver, gold, or any one of the six platinum group metals (i.e., Ru, Rh, Pd, Os, Ir, or Pt). Any convenient deposition method can be used, including chemical vapor deposition (CVD), physical vapor deposition (PVD), such as sputtering or electroplating.

[0024] Examples of materials that can be used to form material layer 292 may be selected from one of silicon nitride, silicon carbide, silicide, silicon carbonitride, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene. Any convenient deposition method may be used, including spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor deposition polymerization (VDP), or physical vapor deposition (PVD).

[0025] For reference Figure 2B As can be seen, the device wafer 293 processing further includes cutting multiple semiconductor devices 203 and 223 to separate them from each other, removing material layer 292, forming serrations or scribing lines 281 and thereby exposing the sidewalls 205 and 207 of semiconductor device 203 and the sidewalls 225 and 227 of semiconductor device 223. Any convenient cutting method can be used, including one or more of plasma cutting, ion etching, laser cutting or blade cutting.

[0026] For reference Figure 2C As can be seen, the processing of device wafer 293 further includes depositing polymer material 294 on device wafer 293, including scribing lines 281, metal interconnects 212, 213, 232 and 233, and multiple individualized semiconductor devices (e.g., semiconductor devices 203 and 223). Polymer material 294 directly encapsulates the sidewalls 205, 207, 225 and 227 of semiconductor devices 203 and 223, respectively. In addition, polymer material 294 directly encapsulates metal interconnects 212, 213, 232 and 233. Polymer material 294 may further encapsulate the back surface 202 of device wafer 293 and the top surface of adhesive 291. Polymer material 294 may partially or wholly comprise a single polymer material or a composite polymer material, such as polyimide, polybenzoxazole, benzocyclobutene or combinations thereof.

[0027] Despite Figures 2A to 2ENot explicitly stated, but in some embodiments, the front side 201 of the device wafer 293 may also be provided with a single or composite polymer material that directly encapsulates the front side 201 of the device wafer 293, thereby exposing the front metal interconnects 208, 209, 228, and 229. For example, the metal interconnects 208, 209, 228, and 229 may be formed on the front side 201 of the device wafer 293, followed by deposition of polymer material as a material layer 292 for directly encapsulating the front side 201 of the device wafer 293 and the metal interconnects 208, 209, 228, and 229. The polymer material layer 292 and the metal interconnects 208, 209, 228, and 229 may then undergo a patterning process and planarization before being attached to the carrier substrate 291. Alternatively, the polymer material layer 292 and the metal interconnects 208, 209, 228, and 229 may be formed and processed on the front side 201 after the processing steps on the back side 202 have been completed. Any convenient polishing or planarization method can be used, including chemical mechanical polishing (CMP) or spin etch planarization (SEP). The thickness of the polymer material layer 292 is preferably in the range of 5 to 6 μm, and more preferably 3 to 4 μm. Partial removal of the polymer material layer 292 can be configured to allow a desired amount or thickness of polymer material to remain on the front side 201 of the device wafer 293 to protect the semiconductor device from damage during dicing, pick-and-place, stacking, and hybrid bonding processes, and to facilitate metal-to-metal interconnect connections during front-to-back semiconductor device hybrid bonding processes, such as in... Figure 3 As shown in the image.

[0028] For reference Figure 2DAs can be seen, the processing of device wafer 293 further includes removing a portion of polymer material 294 to expose the top surface of scribe line 283 and adhesive 291, while leaving remaining portions of polymer material 214 and 234 on the sidewalls 205, 207, 225, and 227 of semiconductor devices 203 and 223, respectively. Any convenient individualization method can be used to remove portions of the polymer material and thereby separate multiple semiconductor devices, including one or more of laser removal or patterning etching. The removal of portions of polymer material 294 can be configured to allow a desired amount or thickness of polymer material to remain on the sidewalls 205, 207, 225, and 227 to protect the semiconductor devices from dicing, pick-and-place, stacking, and hybrid bonding processes. For example, removing a portion of polymer material 294 from adjacent semiconductor devices 203, 223 or along scribing 283 can reduce the thickness of the remaining portions of polymer material 214 and 234 to a range of about 20 to 35 μm along the sidewalls 205, 207, 225, and 227 of each of the plurality of semiconductor devices 203 and 223. More specifically, the remaining portions 214 and 234 of polymer material along the sidewalls 205, 207, 225, and 227 of each of the plurality of semiconductor devices 203 and 223 can have a thickness in the range of 25 to 30 μm, and more preferably a thickness of about 30 μm.

[0029] For reference Figure 2E As can be seen, the processing of device wafer 293 may further include a planarization process to reduce the thickness of polymer materials 214 and 234 on the back surface 202 of device wafer 293 and expose and optionally planarize metal interconnects 212, 213, 232, and 233. Any convenient polishing or planarization method can be used, including chemical mechanical polishing (CMP) or spin etch planarization (SEP). The back surface thickness of polymer materials 214 and 234 is preferably in the range of 5 to 6 μm, and more preferably 3 to 4 μm. The partial removal of polymer materials 214 and 234 can be configured to allow a desired amount or thickness of polymer material to remain on the back surface 202 of device wafer 293 to protect the semiconductor device from damage during dicing, pick-and-place, stacking, and hybrid bonding processes, and to planarize metal interconnects 212, 213, 232, and 233 to facilitate metal-to-metal interconnect connections during the front-back semiconductor device hybrid bonding process, as described below. Figure 3 A more detailed presentation.

[0030] Polymer materials 214, 234, and polymer layer 292 are softer and more flexible than passivation layers, oxides, nitrides, and carbides (e.g., silicon nitride, silicon carbide, silicon carbonitride, silicides, silicon dioxide, etc.). Among other benefits, the flexibility of polymer materials 214, 234, and polymer layer 292 provides better tolerance to CMP dishing defects and over-planarization of metal (e.g., copper) interconnects. Polymer materials are more compatible with the CMP process and do not require precise or rigid planarization processes to prevent over-removal / planarization of metal interconnects. Regarding the extent to which some particles remain on the bonding surface, polymer materials can accommodate deformation around the particles without the risk of delamination. Furthermore, the polymer material can be spin-coated onto the device wafer 293, thereby facilitating easier deposition and better coverage of the device wafer 293 and encapsulating the sidewalls 205, 207, 225, and 227, the front metal interconnects 208, 209, 228, and 229, and the back metal interconnects 212, 213, 232, and 233 of the semiconductor devices 203 and 223. Moreover, due to its significantly lower operating temperature, lower pressure, lower load, and shorter time, the polymer material offers advantages over more commonly used thermal bonding methods using passivation layers, oxides, nitrides, and carbides (e.g., silicon nitride, silicon carbide, silicon carbonitride, silicides, and silicon dioxide). Furthermore, the polymer materials 214, 234, and polymer material layer 292 will conform around the bonding line during the hybrid bonding process. Additionally, the polymer materials 214, 234, and polymer material layer 292 are more resistant to trapped particles, contaminants, and residues in the polymer material throughout the entire dicing, pick-and-place, stacking, and hybrid bonding process.

[0031] Although the front side 201 and back side 202 of the device wafer 293 are described above as having polymer materials, the material layer 292 on the front side 201 can be made of any non-polymer material to obtain the benefits described above. The material layer 292 may include, for example, passivation layers, oxides, nitrides, and carbides, such as silicon nitride, silicon carbide, silicon carbonitride, silicides, and silicon dioxide, as needed to obtain the benefits described above. That is, the benefits described above can be obtained by depositing polymer materials on the back side 202 of the device wafer 293, wherein polymer materials 214 and 234 encapsulate the back side 202 of the device wafer 293 and the sidewalls 205, 207 and 225, 227 of the semiconductor devices 203 and 223, respectively.

[0032] Figure 3 This is an exemplary packaged semiconductor device assembly according to embodiments of the present disclosure. (See reference...) Figure 3As can be seen, multiple semiconductor devices are stacked and bonded together to form a packaged semiconductor assembly 300. The semiconductor assembly 300 includes a first semiconductor device 303 having sidewalls 305 and 307 directly encapsulated by a polymer material 314 and back metal interconnects 312 and 313. Front metal interconnects 308 and 309 of the first semiconductor device 303 are stacked over and connected to package contacts 394 and 395 of the package substrate 396, respectively. The first semiconductor device 303 further includes metal TSVs 310 and 311 connecting the front metal interconnects 308 and 309 to the back metal interconnects 312 and 313. The front metal interconnects 308 and 309 and the front surface are encapsulated by a material layer 302. As described above, the material layer 302 may be selected from one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene. The front and back sides of the first semiconductor device 303 may be planarized or polished to expose the front metal interconnects 308 and 309 and the back metal interconnects 312 and 313.

[0033] The semiconductor assembly 300 further includes a second semiconductor device 323 stacked above the first semiconductor device 303. Front-side metal interconnects 328 and 329 of the second semiconductor device 323 are stacked above and connected to the back-side metal interconnects 312 and 313 of the first semiconductor device 303, respectively. The second semiconductor device 323 has sidewalls 325 and 327 directly encapsulated by a polymer material 334, and back-side metal interconnects 332 and 333. The second semiconductor device 323 further includes metal TSVs 330 and 331 connecting the front-side metal interconnects 328 and 329 to the back-side metal interconnects 332 and 333. The front-side metal interconnects 328 and 329 and the front side are encapsulated by a material layer 322. As described above, the material layer 322 may be selected from one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene. The front and back sides of the first semiconductor device 323 may be planarized or polished to expose the front metal interconnects 328 and 329 and the back metal interconnects 332 and 333.

[0034] The semiconductor assembly 300 may further include a third semiconductor device 343 stacked above the second semiconductor device 323. Front-side metal interconnects 348 and 349 of the third semiconductor device 343 are stacked above and connected to the back-side metal interconnects 332 and 333 of the second semiconductor device 323, respectively. The third semiconductor device 343 has sidewalls 345 and 347 directly encapsulated by a polymer material 354, and back-side metal interconnects 352 and 353. The third semiconductor device 343 further includes metal TSVs 350 and 351 connecting the front-side metal interconnects 348 and 349 to the back-side metal interconnects 352 and 353. The front-side metal interconnects 348 and 349 and the front side are encapsulated by a material layer 342. As described above, the material layer 342 may be selected from one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene. The front and back sides of the first semiconductor device 343 may be planarized or polished to expose the front metal interconnects 348 and 349 and the back metal interconnects 352 and 353.

[0035] The semiconductor assembly 300 may further include a fourth semiconductor device 363 stacked above the third semiconductor device 343. Front-side metal interconnects 368 and 369 of the fourth semiconductor device 363 are stacked above and connected to the back-side metal interconnects 352 and 353 of the third semiconductor device 343, respectively. The fourth semiconductor device 363 has sidewalls 365 and 367 directly encapsulated by a polymer material 374. The front-side metal interconnects 368 and 369, as well as the front side, are encapsulated by a material layer 362. As described above, the material layer 362 may be selected from one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene. The front and back sides of the first semiconductor device 363 may be planarized or polished to expose the front-side metal interconnects 368 and 369 and to reduce the thickness of the polymer material 374 as needed.

[0036] Semiconductor devices 303, 323, 343, and 363 are bonded together, for example, by hybrid bonding and then encapsulated in encapsulant 398. Solder balls 397 are formed to contact the package contacts 394 and 395 of the package substrate 396 to form a packaged semiconductor device assembly 300.

[0037] Figure 4 This is a schematic diagram illustrating an exemplary system comprising a semiconductor device assembly configured according to embodiments of the present disclosure. (See above reference) Figures 2A to 2E Any of the exemplary semiconductor devices and semiconductor device assemblies described in 3 can be incorporated into any of a large number of larger and / or more complex systems, with representative examples being... Figure 4The system 400 is schematically shown in the diagram. System 400 may include a semiconductor device assembly (e.g., or discrete semiconductor device) 402, a power supply 404, a driver 406, a processor 408, and / or other subsystems or components 410. The semiconductor device assembly 402 may include components similar to those described above. Figures 2A to 2E The features are substantially similar to those of the semiconductor device described in section 3. The resulting system 400 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 400 may include, but are not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 400 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). Components of system 400 may also include remote devices and any of a wide variety of computer-readable media.

[0038] Figure 5 This is a flowchart illustrating an exemplary method for manufacturing a semiconductor device assembly. The exemplary method is provided by way of example because there are multiple ways to implement the method. Figure 5 Each box shown represents one or more processes, methods, or subroutines implemented in the exemplary method. Figures 2A to 2E and 3 demonstration implementation Figure 5 An exemplary embodiment of the method is provided. The exemplary method may begin at block 502. Further for illustrative purposes, the blocks of instance process 500 are described herein as occurring sequentially or linearly. However, multiple blocks of instance process 500 may occur in parallel. Additionally, the blocks of instance process 500 may be executed in a different order than shown and / or one or more blocks of instance process 500 may not be executed.

[0039] Figure 5 An exemplary method includes placing a device wafer comprising a plurality of semiconductor devices on a temporary carrier (box 502), wherein each of the plurality of semiconductor devices has a front side facing the temporary carrier and a back side opposite to the front side.

[0040] The method further includes forming a first plurality of metal interconnects on the back side of each of the plurality of semiconductor devices (box 504). In some exemplary embodiments, forming the metal interconnects may include depositing one or more of copper, aluminum, tungsten, tin, silver or gold.

[0041] The method further includes dicing multiple semiconductor devices to separate the semiconductor devices from each other and expose their sidewalls (box 506). In some exemplary embodiments, the dicing process may include one or more of plasma dicing, laser dicing, or blade dicing.

[0042] The method further includes depositing a first polymer material over a plurality of individualized semiconductor devices, such that the polymer material directly encapsulates the sidewalls, backsides, and first plurality of interconnects of each of the plurality of semiconductor devices (box 508). In some exemplary embodiments, the first polymer material may be selected from polyimide, polybenzoxazole, benzocyclobutene, or combinations thereof. Compared to non-organic passivation layers, polymer materials have higher elastic properties and greater tolerance to particles, surface roughness, and copper dish defects during chemical mechanical polishing. In addition to the sidewalls and backsides of the semiconductor devices, the polymer material may also be deposited on the front or top side of the semiconductor devices to provide greater tolerance to cracks, debris, and particulate contaminants in the semiconductor devices during manufacturing processes (e.g., dicing and pick-and-place processes) and to protect the semiconductor devices and assemblies from cracks or debris during stacking and hybrid bonding processes.

[0043] The method further includes individualizing the encapsulated semiconductor devices by removing portions of a first polymer material between adjacent devices in the plurality of semiconductor devices (block 510). In some exemplary embodiments, the first polymer material between each of the plurality of semiconductor devices can be removed by laser removal or patterned etching. Furthermore, the process of removing portions of the first polymer material reduces the thickness of the first polymer material along the sidewalls of each of the plurality of semiconductor devices to about 30 μm.

[0044] The method further includes exposing first plurality of interconnects in each of a plurality of semiconductor devices by planarizing the upper surface of a polymer material (box 512). The planarization process may use chemical mechanical polishing (CMP) or fly cutting to planarize the polymer surface and expose the metal interconnects. In some exemplary embodiments, planarizing the first polymer material reduces the thickness of the first polymer material above the back surface of the plurality of semiconductor devices to about 4 μm.

[0045] In some exemplary embodiments, the method may further include forming a second material on the front side of each of a plurality of semiconductor devices and forming a second plurality of metal interconnects in the second material, wherein each of the second plurality of metal interconnects is aligned with a corresponding one of the first plurality of metal interconnects. Furthermore, the second material may be selected from one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene.

[0046] The method may further include forming a semiconductor device assembly by stacking subgroups of multiple semiconductor devices through hybrid bonding. In some exemplary embodiments, individual semiconductor devices are removed from a temporary carrier substrate by adhesive debonding, followed by cleaning and pick-up for polymer hybrid bonding.

[0047] The devices discussed herein, including memory devices, can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0048] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be located in various locations, including portions distributed such that the functionality is implemented at different physical locations.

[0049] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be considered a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be considered in the same manner as the phrase "at least partially based on".

[0050] As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to a feature in a semiconductor device given the relative orientation or position shown in the figures. For example, “upper” or “topmost” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may depend on orientation interchange.

[0051] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods can be combined.

[0052] As will be understood from the foregoing, specific embodiments of this disclosure have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of this disclosure. Specifically, numerous specific details are set forth in the foregoing description in order to provide a comprehensive and advantageous description of embodiments of this disclosure. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, known structures or operations typically associated with memory systems and apparatuses have not been shown or described in detail to avoid obscuring other aspects of this disclosure. Generally, it should be understood that various other apparatuses, systems, and methods are within the scope of this disclosure, in addition to the specific embodiments disclosed herein.

Claims

1. A semiconductor device assembly comprising: A first semiconductor device, comprising: A first semiconductor substrate having (1) a front side, (2) a back side opposite to the front side, and (3) sidewalls. The first plurality of metal interconnects are formed on the back side, and A first polymer material encapsulates the sidewalls and the back surface, wherein the first polymer material on the sidewalls forms a first vertical outer surface corresponding to the peripheral boundary of the first semiconductor device. The first polymer material is planarized to expose the upper surface of the first plurality of metal interconnects; A second semiconductor device, comprising: A second semiconductor substrate having (1) a top side, (2) a bottom side opposite to the top side, and (3) a vertical wall. A second polymer material encapsulates the vertical wall and the bottom side, wherein the second polymer material on the vertical wall forms a second vertical outer surface corresponding to the peripheral boundary of the second semiconductor device; A third material is deposited on the top side of the second semiconductor device on which a second plurality of metal interconnects are formed; The second semiconductor device is stacked on top of the first semiconductor device, such that: Each of the second plurality of metal interconnects is aligned and electrically coupled to a corresponding one of the first plurality of metal interconnects, and The first vertical outer surface of the first semiconductor device is aligned with the second vertical outer surface of the second semiconductor device; and The first semiconductor device and the second semiconductor device are mixed and bonded together.

2. The semiconductor device assembly of claim 1, wherein the first polymer material and the second polymer material are selected from the group consisting of polyimide, polybenzoxazole and benzocyclobutene.

3. The semiconductor device assembly of claim 1, wherein the thickness of the first polymer material along the sidewall of the first semiconductor device and the second polymer material along the vertical wall of the second semiconductor device is about 30 μm.

4. The semiconductor device assembly of claim 1, wherein the thickness of the first polymer material above the back side of the first semiconductor device is about 4 μm, and the thickness of the second polymer material above the bottom side of the second semiconductor device is about 4 μm.

5. The semiconductor device assembly of claim 1, further comprising a fourth material deposited over the front side of the first semiconductor device and a third plurality of metal interconnects formed in the fourth material, wherein each of the third plurality of metal interconnects is aligned with a corresponding one of the first plurality of metal interconnects.

6. The semiconductor device assembly of claim 5, wherein the third material and the fourth material are one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene.

7. A semiconductor device comprising: A semiconductor substrate having (1) a front side, (2) a back side opposite to the front side and (3) a sidewall; Through-silicon vias (TSVs) that extend from the back side and at least partially penetrate the thickness of the semiconductor substrate; A plurality of metal interconnects are formed on the back side and are electrically coupled to and overlap with the TSV; A first polymer material is deposited above the semiconductor device to directly encapsulate the sidewalls and the back surface; The first polymer material is planarized to expose the upper surface of the first plurality of metal interconnects.

8. The semiconductor device of claim 7, wherein the first polymer material is selected from the group consisting of polyimide, polybenzoxazole and benzocyclobutene.

9. The semiconductor device of claim 7, wherein the thickness of the first polymer material along the sidewall of the semiconductor device is about 30 μm.

10. The semiconductor device of claim 7, wherein the thickness of the first polymer material above the back surface of the semiconductor device is about 4 μm.

11. The semiconductor device of claim 7, further comprising a second material deposited over the front side of the semiconductor device and a second plurality of metal interconnects formed in the second material, wherein each of the second plurality of metal interconnects is aligned with a corresponding one of the first plurality of metal interconnects.

12. The semiconductor device of claim 11, wherein the second material is one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene.

13. A method of manufacturing a semiconductor device assembly, the method comprising: A device wafer comprising multiple semiconductor devices is placed on a temporary carrier, each of the multiple semiconductor devices having a front side facing the temporary carrier and a back side opposite to the front side; A through-silicon via (TSV) is formed on the back side, and the TSV is extended to the front side; A first plurality of metal interconnects are formed on the back side of each of the plurality of semiconductor devices, the first plurality of metal interconnects being electrically coupled to and overlapping the TSV; The device wafer is cut to separate the semiconductor devices from each other and expose their sidewalls; A first polymer material is deposited over the plurality of individualized semiconductor devices, such that the polymer material directly encapsulates the sidewalls, the back surface, and the plurality of metal interconnects of each of the plurality of semiconductor devices. The first polymer material on the sidewalls forms the outer vertical wall of each of the semiconductor devices. The semiconductor device has a common width measured between the outer vertical walls; The encapsulated semiconductor devices are individualized by removing portions of the first polymer material from between the outer vertical walls of adjacent semiconductor devices; and The first plurality of metal interconnects of each of the plurality of semiconductor devices are exposed by planarizing the upper surface of the polymer material.

14. The method of claim 13, wherein the first polymer material is selected from the group consisting of polyimide, polybenzoxazole and benzocyclobutene.

15. The method of claim 13, wherein the first polymer material between each of the plurality of semiconductor devices is removed by laser removal or patterned etching.

16. The method of claim 13, wherein removing the portion of the first polymer material reduces the thickness of the first polymer material along the sidewall of each of the plurality of semiconductor devices to about 30 μm.

17. The method of claim 13, wherein planarizing the first polymer material reduces the thickness of the first polymer material above the back surface of the plurality of semiconductor devices to about 4 μm.

18. The method of claim 13, further comprising forming a second material on the front side of each of the plurality of semiconductor devices and forming a second plurality of metal interconnects in the second material, wherein each of the second plurality of metal interconnects is aligned with a corresponding one of the first plurality of metal interconnects.

19. The method of claim 18, wherein the second material is one of silicon nitride, silicon carbide, silicide, silicon dioxide, polyimide, polybenzoxazole, or benzocyclobutene.

20. The method of claim 18, further comprising stacking subgroups of the plurality of semiconductor devices by hybrid bonding.

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