Wafer alignment of stacked wafers and semiconductor device assemblies

Abstract

The present disclosure relates to wafer alignment for stacked wafer and semiconductor device assemblies. A semiconductor device assembly includes a first semiconductor wafer having a first side and a second side opposite the first side, the first semiconductor wafer including a first plurality of semiconductor devices at the first side, a plurality of non-metallic vias extending from the second side toward the first side, and a plurality of alignment marks each vertically aligned with a corresponding one or more of the plurality of non-metallic vias; a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of overlay marks each vertically aligned with a corresponding one or more of the plurality of alignment marks.

Description

Technical Field

[0001] This disclosure relates to wafer alignment, and more specifically, to wafer alignment for stacking wafers and semiconductor device assemblies. Background Technology

[0002] Conventional semiconductor wafer alignment for stacking typically requires viewing the semiconductor films on the wafers or viewing them at an angle between the wafers to properly align them before the stacking process. In this way, stacking marks cannot be used because the wafers are aligned before stacking and bonding, preventing the use of feedback / feedforward wafer handling methods. The trend towards manufacturing increasingly smaller electronic devices has led to a significant increase in semiconductor device density and the stacking of numerous semiconductor films and materials, making conventional wafer stacking processes impractical or infeasible. Furthermore, to reduce costs, larger wafers are used to produce more semiconductor devices, significantly reducing the alignment margin required using conventional wafer stacking processes. Therefore, conventional wafer alignment processes cannot achieve the alignment accuracy required by feedback / feedforward wafer handling methods. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device assembly is provided. The semiconductor device assembly includes: a first semiconductor wafer having a first side and a second side opposite to the first side, the first semiconductor wafer including a first plurality of semiconductor devices on the first side, a plurality of non-metallic vias extending from the second side toward the first side, and a plurality of alignment marks, each alignment mark being vertically aligned with one or more of the corresponding non-metallic vias; and a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of overlapping marks, each of the plurality of overlapping marks being vertically aligned with one or more of the corresponding alignment marks.

[0004] According to another aspect of this disclosure, a method for manufacturing a semiconductor device assembly is provided. The method includes: forming a first plurality of semiconductor devices on a first side of a first semiconductor wafer; forming a plurality of non-metallic vias extending from a second side of the first semiconductor wafer toward the first side, wherein the second side is opposite to the first side; forming a plurality of alignment marks, each alignment mark being vertically aligned with one or more corresponding non-metallic vias; forming a second plurality of semiconductor devices and a plurality of overlay marks on a second semiconductor wafer; and aligning the first semiconductor wafer with the second semiconductor wafer such that each of the plurality of overlay marks is vertically aligned with one or more corresponding alignment marks.

[0005] According to another aspect of this disclosure, a semiconductor device assembly is provided. The semiconductor device assembly includes: a first semiconductor wafer having a first side and a second side opposite to the first side, the first semiconductor wafer including a first plurality of semiconductor devices on the first side, a plurality of non-metallic vias extending from the second side toward the first side, and a plurality of alignment marks, wherein the width of each of the plurality of non-metallic vias is between 1 and 15 μm, and each alignment mark is vertically aligned with one or more corresponding of the plurality of non-metallic vias; a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of overlapping marks, each of the plurality of overlapping marks being vertically aligned with one or more corresponding of the plurality of alignment marks; wherein the periphery of each of the plurality of non-metallic vias overlaps the periphery of each of the plurality of overlapping marks, and wherein at least one of the plurality of non-metallic vias is formed between two adjacent coverage areas of the first plurality of semiconductor devices; wherein the plurality of overlapping marks are visible through the plurality of non-metallic vias in a wavelength spectrum in the range of 400 to 700 nm; and wherein the plurality of non-metallic vias are filled with a material selected from epoxy resin, silicon carbide, silicon oxide, silicon dioxide, or combinations thereof. Attached Figure Description

[0006] Figure 1A This is a plan view of exemplary overlay markings on a first semiconductor wafer according to an exemplary embodiment of the present disclosure.

[0007] Figure 1B yes Figure 1A An enlarged view of an example overlapping mark in the image.

[0008] Figure 1C It was cut from slice 1-Z. Figure 1A A simplified schematic cross-sectional view.

[0009] Figure 2A This is a plan view of exemplary alignment marks on a second semiconductor wafer according to an exemplary embodiment of the present disclosure.

[0010] Figure 2B yes Figure 2A An enlarged view of the exemplary alignment mark in the image.

[0011] Figure 2C It was cut from piece 2-Z. Figure 2A A simplified schematic cross-sectional view.

[0012] Figure 3A It is along Figure 2A A plan view of the non-metallic through-holes around the alignment mark.

[0013] Figure 3B By along Figure 3AA magnified view of the semiconductor device film stack, showing the non-metallic vias formed around the alignment marks.

[0014] Figure 3C It was cut from piece 3-Z. Figure 3A A simplified schematic cross-sectional view.

[0015] Figure 3D It was cut from piece 3-Z. Figure 3A Another simplified schematic cross-sectional view.

[0016] Figure 4A It is an exemplary embodiment of the present disclosure and Figure 1A The first semiconductor wafer is vertically aligned Figure 3A A perspective view of the second semiconductor wafer.

[0017] Figure 4B It was cut from slice 4-Y above slice 4-Z. Figure 4A A simplified schematic cross-sectional view.

[0018] Figure 4C It is along Figure 4B A magnified view of the non-metallic through-hole surrounding the alignment mark.

[0019] Figure 4D Through Figure 4C A magnified view of the overlapping markings on the non-metallic through-hole.

[0020] Figure 4E Through Figure 4D Another enlarged view of the overlapping markings for viewing the non-metallic through-hole.

[0021] Figure 5A This is a plan view of exemplary alignment marks and non-metallic vias on a second semiconductor wafer according to exemplary embodiments of the present disclosure.

[0022] Figure 5B Is with Figure 1A The first semiconductor wafer is vertically aligned and cut from cut 5-Z. Figure 5A A simplified schematic cross-sectional view.

[0023] Figure 5C Through Figure 5B A magnified view of the semiconductor device film stack as seen through a non-metallic via.

[0024] Figure 5D It is used for viewing Figure 5C An enlarged view of another exemplary non-metallic via in a semiconductor device film stack.

[0025] Figure 5E Through Figure 5D A magnified view of the overlapping markings on the non-metallic through-hole.

[0026] Figures 6A to 6E This is a simplified schematic cross-sectional view of an exemplary non-metallic through-hole processed without the use of metal filler, according to an exemplary embodiment of the present disclosure.

[0027] Figures 7A to 7E This is a simplified schematic cross-sectional view of an exemplary non-metallic through-hole using metal filling according to an exemplary embodiment of the present disclosure.

[0028] Figure 8 This is a schematic diagram of an exemplary system including a semiconductor device assembly configured according to exemplary embodiments of the present disclosure.

[0029] Figure 9 This is a flowchart illustrating an exemplary method for manufacturing a semiconductor device assembly according to exemplary embodiments of the present disclosure.

[0030] While various modifications and alternatives are permissible with respect to this disclosure, specific embodiments have been shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. In fact, it is intended to cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure as defined by the appended claims. Detailed Implementation

[0031] The following describes several embodiments of semiconductor devices and specific details of associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein can be performed at the wafer level or the die level. Therefore, depending on the context, the term "substrate" can refer to a wafer-level substrate or a die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques can be used to deposit materials. Similarly, for example, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques can be used to remove materials.

[0032] Numerous specific details are set forth in this disclosure to provide a thorough and illustrative description of embodiments thereof. Those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details described. Well-known structures and / or operations typically associated with semiconductor devices may not be shown and / or described in detail to avoid obscuring other aspects of this disclosure. In general, it should be understood that various other devices, systems, and / or methods may also be within the scope of this disclosure in addition to the specific embodiments disclosed herein.

[0033] The term "semiconductor device assembly" can refer to an assembly of one or more semiconductor devices, semiconductor device packages, and / or substrates, said substrates may include inserts, supports, and / or other suitable substrates. Semiconductor device assemblies can be manufactured in, but are not limited to, discrete package forms, strip or matrix forms, and / or wafer assemblies. The term "semiconductor device" generally refers to a solid-state device comprising semiconductor material. A semiconductor device may comprise, for example, a semiconductor substrate, a wafer, a liner, or a single die from a wafer or substrate. A semiconductor device may further comprise one or more device layers deposited on a substrate. A semiconductor device may refer herein to a semiconductor die, but a semiconductor device is not limited to a semiconductor die.

[0034] The term "semiconductor device package" can refer to an arrangement in which one or more semiconductor devices are incorporated into a common package. A semiconductor package may include a housing or enclosure that partially or completely encloses at least one semiconductor device. A semiconductor package may also include a substrate that carries one or more semiconductor devices. The substrate may be attached to or otherwise incorporated therein from the housing or enclosure.

[0035] As explained above, conventional wafer alignment processes cannot achieve the alignment accuracy required by feedback / feedforward wafer processing methods. Embodiments of this disclosure address this and other challenges by providing non-metallic vias for the wafer alignment process. The use of non-metallic vias allows features or markings formed on a second stacked wafer located below the first stacked wafer to be viewed through the vias (e.g., over a wide wavelength range including visible, infrared, and ultraviolet light). The non-metallic vias of the stacked wafers provide visual feedback for in-situ alignment of the first and second stacked wafers throughout the stacking process, allowing an operator to adjust either stacked wafer during stacking and bonding processes based on features or markings visible through the non-metallic vias. In this way, the stacked wafers can include alignment marks that allow for wafer alignment prior to stacking and bonding, enabling the use of feedback / feedforward wafer processing methods.

[0036] For reference Figures 1A to 1C As can be seen, an exemplary first stacked wafer 100 for forming the semiconductor device assembly of this disclosure may include a semiconductor wafer 107 having an active surface containing a semiconductor film stack 105 on a first side 103 and a passivation layer 102 disposed on a second side 101. The semiconductor wafer 107 may include a plurality of lamination marks, such as lamination marks 109, to facilitate wafer-level alignment processes.

[0037] Figure 1BThe exemplary overlay mark 109 is shown in detail. The overlay mark 109 may comprise an array of visible marks arranged in a predetermined pattern, such as a group of four squares arranged around a common center. Various other overlay marks (including lines, objects, polygons, and other geometric and non-geometric shapes) may be used to obtain the overlay mark 109 of the first stacked wafer 100 for alignment with the corresponding alignment mark of the second stacked wafer.

[0038] For reference Figure 1C An exemplary cross-sectional view of a first stacked wafer 100 cut along slice 1-Z is shown. As illustrated, the functional surface on the first side 103 includes a semiconductor film stack 105 having regions 105a, 105b, and 105c, wherein one or more regions 105a to 105c may contain one or more semiconductor devices, and a passivation layer 102 is formed on the second side 101. For example, multiple semiconductor devices may be formed only on region 105c, or multiple semiconductor devices may be formed on combinations such as regions 105a and 105b, regions 105a and 105c. Multiple stacking marks 109 may be formed on the semiconductor film stack 105, for example, but not limited to regions 105a and 105c, one or both regions may contain semiconductor devices.

[0039] For reference Figures 2A to 2C As can be seen, an exemplary second stacked wafer 200 with alignment marks 219 is provided for the process of forming non-metallic vias according to an exemplary embodiment of the present disclosure. An array of non-metallic vias (e.g., such as...) can be formed in the exemplary second stacked wafer 200. Figures 3A to 3C as well as Figures 5A to 5E (As shown), to allow visual feedback for in-situ alignment of the first stacked wafer 100 and the second stacked wafer 200 throughout the stacking process. An exemplary second stacked wafer 200 may include a semiconductor wafer 217 having an active surface containing a semiconductor film stack 215 on a first side 213 and a passivation layer 212 on a second side 211. The semiconductor wafer 217 may include multiple alignment marks, such as alignment marks 219, to facilitate the wafer-level alignment process.

[0040] Figure 2B An exemplary alignment mark 219 is shown in detail. The alignment mark 219 may comprise an array of visible marks arranged in a predetermined pattern, such as a cross or a "+" symbol. Various other alignment marks (including lines, objects, polygons, and other geometric and non-geometric shapes) may be used to produce alignment marks 219 on the second stacked wafer 200 corresponding to the overlap mark 109 of the first stacked wafer 100.

[0041] For reference Figure 2CAn exemplary cross-sectional view of the second stacked wafer 200, taken along cut 2-Z, is shown. As shown, the semiconductor wafer 217 includes an active surface with a semiconductor film stack 215 on a first side 213 and a passivation layer 212 formed on a second side 211. The passivation layer 212 has regions 212a, 212b, and 212c, wherein one or more regions 212a to 212c may cover one or more semiconductor devices formed in the semiconductor film stack 215. A plurality of alignment marks 219 may be formed on the passivation layer 212, in, for example but not limited to, regions 212a and 212c, one or both of which may cover semiconductor devices formed beneath the semiconductor film stack 215. For example, the plurality of semiconductor devices may be formed only beneath region 212c, or the plurality of semiconductor devices may be formed beneath combinations of regions 212a and 212b, regions 212a and 212c, etc.

[0042] For reference Figures 3A to 3D As can be seen, an exemplary stacked wafer 300 for forming the semiconductor device assembly of this disclosure may include a plurality of alignment marks 319 and one or more non-metallic vias 329, the one or more non-metallic vias being formed on the semiconductor wafer 317 and being close to, adjacent to, or intersecting with one or more edges or boundaries of each alignment mark 319, or being formed or intersecting along the closed boundary or periphery of each alignment mark 319. The semiconductor wafer 317 includes an active surface having a semiconductor film stack 315 on a first side 313, and a passivation layer 312 is formed on a second side 311.

[0043] For reference Figure 3B As can be seen, an exemplary alignment mark 319 and a non-metallic via 329 are shown. The non-metallic via 329 is formed between adjacent edges of the alignment mark 319. Various other alignment marks, including lines, objects, polygons, and other geometries and non-geometric shapes, can be used, provided that complementary or corresponding overlapping marks can be suitably formed on another stacked wafer and used for alignment with the stacked wafer 300. Furthermore, as Figure 3B to 3D As shown, the non-metallic via 329 can extend completely through the passivation layer 312 and the semiconductor wafer 317 to expose the semiconductor film stack 315.

[0044] For reference Figure 3C to 3D As can be seen, a non-metallic via 329 is formed on a passivation layer 312, which has regions 312a, 312b, and 312c, wherein none of the regions 312a to 312c covers the semiconductor device formed in the semiconductor film stack 315. The non-metallic via 329 extends through the passivation layer 312 and the first side 313 and the second side 311 of the semiconductor wafer 317.

[0045] Non-metallic vias 329 allow features or markings formed on a second stacked wafer located below the first stacked wafer 300 to be visible. The non-metallic vias 329 of the stacked wafer 300 provide visual feedback for in-situ alignment of the first and second stacked wafers throughout the stacking process, allowing an operator to adjust either stacked wafer based on features or markings visible through the non-metallic vias 329 during the stacking and bonding process. Features or markings formed on the second stacked wafer are visible or visible through multiple non-metallic vias 329 in wavelength spectra ranging from 400 to 700 nm, 700 to 2000 nm, or 2 to 50 μm. In this way, the stacked wafers can include stacking marks that allow wafer alignment prior to stacking and bonding, enabling the use of feedback / feedforward wafer handling methods.

[0046] For reference Figures 4A to 4E As can be seen, two exemplary stacked wafers for forming the semiconductor device assembly of this disclosure are illustrated. A first stacked wafer 400A may include a plurality of alignment marks 419 and one or more non-metallic vias 429, said non-metallic vias being formed on a semiconductor wafer 417 and close to, adjacent to, or intersecting with one or more edges or boundaries of each alignment mark 419, or formed or intersecting along the closed boundary or periphery of each alignment mark 419. The semiconductor wafer 417 includes an active surface having a semiconductor film stack 415 on a first side 413, and a passivation layer 412 is formed on a second side 411. A second stacked wafer 400B may include a plurality of stacking marks 409 formed on the semiconductor wafer 407, wherein each of the plurality of stacking marks 409 is vertically aligned with and corresponds to the plurality of alignment marks 419 of the first stacked wafer 400A. The second stacked wafer 400B further includes a semiconductor film stack 405 formed on a first side 403 of the semiconductor wafer 407. The stacking marks 409 may also be formed on the first side 403 of the semiconductor wafer 407. The overlay mark 409 may comprise an array of visible marks arranged in a predetermined pattern, such as a group of four squares arranged around a common center. Various other overlay marks (including lines, objects, polygons, and other geometric and non-geometric shapes) may be used to obtain the overlay mark 409 of the first stacked wafer 400A for alignment with the corresponding alignment mark 419 of the second stacked wafer 400B.

[0047] For reference Figure 4BAs can be seen, the first stacked wafer 400A and the second stacked wafer 400B are stacked and bonded together in a face-to-face arrangement (e.g., where the active surfaces face each other). The first stacked wafer 400A includes a semiconductor wafer 417 having an active surface containing a semiconductor film stack 415 on a first side 413 and a passivation layer 412 formed on a second side 411. The passivation layer 412 may include regions 412a, 412b, and 412c, wherein none of the regions 412a to 412c may cover the semiconductor devices formed in the semiconductor film stack 415. One or more non-metallic vias 429 are formed on one or more regions 412a to 412c that may cover the one or more semiconductor devices formed in the semiconductor film stack 415. The non-metallic vias 429 extend through the passivation layer 412 and the first side 413 to the second side 411 of the semiconductor wafer 417 to expose the surface of the semiconductor film stack 415. One or more non-metallic vias 429 may be formed on the semiconductor wafer 417 and close to, adjacent to or intersect with one or more edges or boundaries of each alignment mark 419, or formed or intersected along the closed boundary or periphery of each alignment mark 419.

[0048] like Figure 4B As shown, the non-metallic via 429 allows the portion beneath the semiconductor film stack 415 to be visible using, for example, the naked eye and / or magnifying optical instruments (e.g., a camera). Alignment marks 419 are made visible through the non-metallic via 429 in wavelength spectra ranging from, for example, 400 to 700 nm, 700 to 2000 nm, or 2 to 50 μm. Furthermore, the non-metallic via 429 allows features or markings formed on a second stacked wafer 400B located beneath the first stacked wafer 400A to be visible. The non-metallic via 429 of the first stacked wafer 400A provides visual feedback for in-situ alignment of the second stacked wafer 400B throughout the stacking process, allowing an operator to adjust either the first stacked wafer 400A or the second stacked wafer 400B based on features or markings visible through the non-metallic via 429 during the stacking and bonding process. In this way, stacked wafers may include stacking marks that allow wafer alignment prior to stacking and bonding, enabling the use of feedback / feedforward wafer handling methods.

[0049] The second stacked wafer 400B includes a semiconductor wafer 407 having an active surface containing a semiconductor film stack 405 on a first side 403 and a passivation layer 402 formed on a second side 401. The semiconductor film stack 405 has regions 405a, 405b, and 405c, wherein no region, region, or regions 405a to 405c covers the semiconductor device formed in the semiconductor film stack 405.

[0050] For reference Figures 4C to 4EAs can be seen, an exemplary alignment mark 419 and a non-metallic via 429 are shown. The non-metallic via 429 is formed between adjacent edges of the alignment mark 419. Various other alignment marks, including lines, objects, polygons, and other geometries and non-geometric shapes, can be used, as long as complementary or corresponding overlapping marks 409 can be suitably formed on the second stacked wafer 400B and used for alignment with the alignment mark 419 of the first stacked wafer 400A. Figures 4D to 4E As shown, the non-metallic via 429 can extend completely through the passivation layer 412 and the semiconductor wafer 417 to expose the semiconductor film stack 415. Furthermore, as... Figure 4E As shown, the overlay mark 409 is visible through the non-metallic via 429 and the semiconductor film stack 415, and can be used to align the first stacked wafer 400A with the second stacked wafer 400B. Figure 4E In this process, the overlap mark 409 may have different shapes or sizes, such that the area of ​​the overlap mark 409 only needs to be cut within the area of ​​the non-metallic via 429 so that the operator can confirm that the first stacked wafer 400A is aligned with the second stacked wafer 400B.

[0051] like Figures 4B to 4E As shown, the non-metallic via 429 allows the portion beneath the semiconductor film stack 415 to be visible to the naked eye, for example. This makes the overlay mark 409 visible through the non-metallic via 429 in wavelength spectra, for example, in the range of 400 to 700 nm, 700 to 2000 nm, or 2 to 50 μm, as well as other wavelengths including ultraviolet light.

[0052] For reference Figures 5A to 5E As can be seen, an exemplary stacked wafer 500 for forming the semiconductor device assembly of this disclosure may include a plurality of alignment marks 519 and one or more non-metallic vias 529, the one or more non-metallic vias being formed on the semiconductor wafer 517 and being close to, adjacent to, or intersecting with one or more edges or boundaries of each alignment mark 519, or being formed or intersecting along the closed boundary or periphery of each alignment mark 519. The semiconductor wafer 517 includes an active surface having a semiconductor film stack 515 on a first side 513, and a passivation layer 512 is formed on a second side 511.

[0053] For reference Figure 5BAs can be seen, the first stacked wafer 500A and the second stacked wafer 500B are stacked and bonded together in a face-to-face arrangement (e.g., where the active surfaces face each other). The first stacked wafer 500A includes a semiconductor wafer 517 having an active surface containing a semiconductor film stack 515 on a first side 513 and a passivation layer 512 formed on a second side 511. The passivation layer 512 may include regions 512a, 512b, and 512c, wherein none of the regions 512a to 512c may cover the semiconductor devices formed in the semiconductor film stack 515. One or more non-metallic vias 529 are formed on one or more regions 512a to 512c that may cover the one or more semiconductor devices formed in the semiconductor film stack 515. The non-metallic vias 529 extend through the passivation layer 512 and the first side 513 to the second side 511 of the semiconductor wafer 517 to expose the surface of the semiconductor film stack 515. One or more non-metallic vias 529 may be formed on the semiconductor wafer 517 and on or above each alignment mark 519.

[0054] like Figure 5B As shown, the non-metallic via 529 allows the portion beneath the semiconductor film stack 515 to be visible using, for example, the naked eye and / or magnifying optical instruments (e.g., a camera). Alignment marks 519 are made visible through the non-metallic via 529 in wavelength spectra ranging from, for example, 500 to 700 nm, 700 to 2000 nm, or 2 to 50 μm. Furthermore, the non-metallic via 529 allows features or markings formed on a second stacked wafer (e.g., semiconductor wafer 507) located beneath the first stacked wafer (e.g., semiconductor wafer 517) to be visible. The non-metallic via 529 of the first stacked wafer (semiconductor wafer 517) provides visual feedback for in-situ alignment of the second stacked wafer (semiconductor wafer 507) throughout the stacking process, allowing an operator to adjust either stacked wafer during the stacking and bonding process based on features or markings visible through the non-metallic via 529. In this way, the stacked wafers may include stacking marks that allow wafer alignment prior to stacking and bonding, enabling the use of feedback / feedforward wafer handling methods.

[0055] The second stacked wafer includes a semiconductor wafer 507 having an active surface containing a semiconductor film stack 505 on a first side 503 and a passivation layer 502 formed on a second side 501. The semiconductor film stack 505 has regions 505a, 505b, and 505c, wherein no region, region, or regions 505a to 505c covers the semiconductor device formed in the semiconductor film stack 505.

[0056] For reference Figures 5C to 5EAs can be seen, an exemplary alignment mark 519, a semiconductor film stack 515, and a non-metallic via 529 are shown. The non-metallic via 529 is formed on or above the alignment mark 519. Various other alignment marks, including lines, objects, polygons, and other geometric and non-geometric shapes, can be used, as long as complementary or corresponding overlapping marks 509 can be suitably formed on the second stacked wafer (e.g., on semiconductor wafer 507) and used for alignment with the alignment mark 519 on the first stacked wafer (e.g., on semiconductor wafer 517).

[0057] like Figure 5C As shown, the non-metallic via 529 allows a portion beneath the semiconductor film stack 515 to be visible using, for example, the naked eye and / or magnifying optical instruments (e.g., a camera). Alignment marks 519 are made visible through the non-metallic via 529 in wavelength spectra, for example, in the range of 400 to 700 nm, 700 to 2000 nm, or 2 to 50 μm. The non-metallic via 529 overlaps with the periphery of the alignment marks 519, thereby allowing areas outside the alignment marks 519 to be visible. Figure 5D As shown, the non-metallic through-hole 529 can be formed to overlap one or more edges of the alignment mark 519, while still allowing the alignment of the overlap mark 509 to be visible.

[0058] like Figure 5E As shown, the alignment mark 509 is visible through the non-metallic via 529 and can be used to align the first stacked wafer with the second stacked wafer (e.g., aligning semiconductor wafer 507 with semiconductor wafer 517). The alignment mark 509 can have different shapes or sizes such that the area of ​​the alignment mark 509 only needs to be cut within the area of ​​the non-metallic via 529 for an operator to confirm that the first and second stacked wafers are aligned. The alignment mark 509 can comprise an array of visible marks arranged in a predetermined pattern, such as a group of four squares arranged around a common center. Various other alignment marks (including lines, objects, polygons, and other geometric and non-geometric shapes) can be used to obtain the alignment mark 509 of the first stacked wafer 500A for alignment with the corresponding alignment mark 519 of the second stacked wafer 500B.

[0059] For reference Figures 6A to 6E As can be seen, non-photoresist lithography can be performed on non-metallic vias 629. Figure 6A For example, filler material can be added to form filler layer 631. Figure 6B This is used to fill the non-metallic via 629 and the semiconductor wafer 617, and to cover the passivation layer 612, the semiconductor film stack 615, and the first side 613 of the semiconductor wafer 617. (As shown) Figures 6C to 6EAs shown, once the non-metallic via 629 is filled, back-end processing can be performed without damaging or processing the second side 611 of the semiconductor wafer 617. For example, seed deposition is performed to form a seed layer 633. Figure 6C ), plated to form a conductive layer 635 ( Figure 6D ) and chemical mechanical polishing (CMP) carrier to remove passivation layer 612 ( Figure 6E Remove the seed layer 633 and the conductive layer 635.

[0060] For reference Figures 7A to 7E As can be seen, photoresist lithography can be performed on the non-metallic via 729, for example, depositing a conductive layer 735 over the filling layer 731 and the non-metallic via 729 to cover the passivation layer 712 and the first side 713 of the semiconductor wafer 717. Figures 7B to 7E As shown in the figure, once the conductive layer 735 is deposited... Figure 7A This allows for another line of back-end processing to be performed without damaging or processing the second side 711 of the semiconductor wafer 717. For example, adding a photoresist layer 737 ( Figure 7B ), treating / exposing the photoresist layer to form an absorption / exposure layer 739 ( Figure 7C Remove photoresist ( Figure 7D ) and removal of conductive layer 735 ( Figure 7E ).

[0061] The non-metallic vias 329, 429, 529, 629, and 729 of this disclosure may be filled with a rare or inert gas, air, or be empty (e.g., a vacuum). Non-metallic via 729 may be filled with, for example, hydrogen (H), nitrogen (N), oxygen (O), fluorine (F), chlorine (Cl), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), radon (Rn), or any combination or mixture of these gases. Furthermore, non-metallic via 729 may be empty or form a vacuum. In some embodiments, non-metallic via 729 may further contain other elements or particles used in the manufacture of semiconductor device assemblies; for example, oxides, nitrides, carbides, copper, or aluminum particles may be suspended in non-metallic via 729 and / or mixed with filling layers 631 or 731. Furthermore, each of the one or more non-metallic through-holes 329, 429, 529, 629, and 729 of this disclosure may be filled with different gases, materials (e.g., elements or particles), or any combination or mixture of the gases or materials presented above. For example, see [link to documentation]. Figure 5B The non-metallic through-hole 529 on the left may contain oxygen, while the adjacent non-metallic through-hole 529 may contain air.

[0062] Examples of materials that can be used to form filler layers 631 and 731 may include, for example, passivation layers, oxides, nitrides, and carbides, such as silicon nitride, silicon carbide, silicon carbonitride, silicides and silicon dioxide, epoxy resins, silicon oxides, or combinations thereof, which may be used to form protective layers, encapsulations, or passivations as needed. Any convenient deposition method may be used, including spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor deposition polymerization (VDP), or physical vapor deposition (PVD).

[0063] Examples of metals that can be used to form conductive layers 635 and 735 may include copper, aluminum, tungsten, tin, silver, gold, or any of the six platinum metals (i.e., Ru, Rh, Pd, Os, Ir, or Pt). Any convenient deposition method may be used, including chemical vapor deposition (CVD), physical vapor deposition (PVD), such as sputtering or electroplating.

[0064] The above reference Figures 1A to 7E Any of the exemplary semiconductor devices and semiconductor device assemblies described can be incorporated into any of a large number of larger and / or more complex systems, representative examples of which are... Figure 8 System 800 is schematically shown in the diagram. System 800 may include a semiconductor device assembly (e.g., or discrete semiconductor device) 802, a power supply 804, a driver 806, a processor 808, and / or other subsystems or components 810. Semiconductor device assembly 802 may include components similar to those referenced above. Figures 1A to 7E The described semiconductor devices are generally similar in characteristics. The resulting system 800 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 800 may include, but is not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. The components of system 800 may be housed in a single unit or (e.g., distributed across multiple interconnected units via a communication network). The components of system 800 may also include remote devices and any of a wide variety of computer-readable media.

[0065] Figure 9 This is a flowchart illustrating an exemplary method for manufacturing a semiconductor device assembly. The exemplary method is provided by way of example because various ways exist to perform the method. Figure 9 Each box shown represents one or more procedures, methods, or subroutines performed in the exemplary method. Figures 1A to 7E The exhibition is underway Figure 9An exemplary embodiment of the method is provided. An exemplary method may begin at block 902. Further for illustrative purposes, the blocks of instance procedure 900 are described herein as occurring sequentially or linearly. However, multiple blocks of instance procedure 900 may occur in parallel. Additionally, blocks of instance procedure 900 may be executed in a different order than shown, and / or one or more blocks of instance procedure 900 may not be executed.

[0066] Figure 9 An exemplary method includes forming a first plurality of semiconductor devices on a first side of a first semiconductor wafer (block 902). The method further includes forming a plurality of non-metallic vias extending from a second side of the first semiconductor wafer toward the first side, the second side being opposite to the first side (block 904). The method further includes forming a plurality of alignment marks, each alignment mark being vertically aligned with one or more of the corresponding non-metallic vias (block 906).

[0067] In some exemplary embodiments, one or more of the plurality of non-metallic vias may be formed along the periphery of each of the plurality of alignment marks to be vertically aligned and correspond to each of the plurality of overlapping marks. In some exemplary embodiments, one or more of the plurality of non-metallic vias may be formed along the periphery of each of the plurality of alignment marks to be vertically aligned and enclose the region of each of the plurality of overlapping marks corresponding to the alignment mark. The method may further include: forming at least one of the plurality of non-metallic vias within a coverage area of ​​one of the first plurality of semiconductor devices, forming at least one of the plurality of non-metallic vias between two adjacent coverage areas of the first plurality of semiconductor devices, or a combination thereof. The plurality of non-metallic vias may be formed along a dicing / cutting line to facilitate the separation of semiconductor devices, or the plurality of non-metallic vias may be formed on and held on a coverage area of ​​a semiconductor device via a separation of semiconductor device or semiconductor die.

[0068] In some exemplary embodiments, a plurality of alignment marks may be formed on a second side of the first semiconductor wafer. In some exemplary embodiments, and not limited to, the plurality of alignment marks may be formed on a surface of a first plurality of semiconductor devices, the surface being opposite to a first side of the first semiconductor wafer.

[0069] The method further includes forming a second plurality of semiconductor devices and a plurality of overlay marks on a second semiconductor wafer, wherein each of the plurality of overlay marks is vertically aligned with one or more of the plurality of alignment marks (box 908). The method further includes aligning the first semiconductor wafer over the second semiconductor wafer such that the plurality of overlay marks are visible through one or more of the plurality of non-metallic vias (box 910).

[0070] In some exemplary embodiments, the plurality of overlapping marks may be visible or visible through a plurality of non-metallic vias in a wavelength spectrum, for example, in the range of 400 to 700 nm, 700 to 2000 nm, or 2 to 50 μm.

[0071] The method further includes aligning a first semiconductor wafer with a second semiconductor wafer, wherein the periphery of each of the plurality of non-metallic vias partially overlaps with the periphery of each of the plurality of overlap marks (box 912). Therefore, aligning the plurality of non-metallic vias with the plurality of overlap marks allows for alignment of the first and second semiconductor wafers during stacking, thereby improving the alignment accuracy of the first plurality of semiconductor devices formed on the first semiconductor wafer to be optically aligned onto a second plurality of semiconductor devices to be stacked on the second semiconductor wafer.

[0072] In some exemplary embodiments, the method may further include aligning a first semiconductor wafer and a second semiconductor wafer, wherein the periphery of each of the plurality of non-metallic vias overlaps with the periphery of each of the plurality of alignment marks. The method may further include aligning the first semiconductor wafer and the second semiconductor wafer such that the periphery of each of the plurality of non-metallic vias overlaps with the periphery of each of the plurality of alignment marks.

[0073] The method further includes filling the plurality of non-metallic vias (frame 914) with a material selected from epoxy resin, silicon carbide, silicon oxide, silicon dioxide, or combinations thereof. In some exemplary embodiments, the width of each of the plurality of non-metallic vias may be between 1 and 15 μm, and the height of each of the plurality of non-metallic vias may be between 10 and 20 μm.

[0074] As shown in the figure Figures 6A to 6E As illustrated, the filled multiple non-metallic vias can be further processed, for example, by seed deposition, plating, chemical mechanical polishing (CMP), stacking, bonding, and individual semiconductor devices. Alternatively, as in... Figures 7A to 7E As explained, instead of filling multiple non-metallic vias, they can be processed by other photolithography processes, such as plating, seed deposition, adding / removing photoresist, and removing seed deposition, depending on the formation of the semiconductor device or design requirements. This allows multiple non-metallic vias to be used as, for example, dicing / cutting lines to facilitate the single stacking of semiconductor devices.

[0075] The devices discussed herein, including memory devices, can be formed on semiconductor substrates or dies, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0076] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributed configurations such that portions of the functionality are implemented in different physical locations.

[0077] As used herein, the "or" used in the claims (e.g., the list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0078] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, up / down, above / below, up / down, and left / right can be interchanged depending on the orientation.

[0079] It should be noted that the methods described above depict possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods can be combined.

[0080] As should be understood from the foregoing, specific embodiments of this disclosure have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of this disclosure. Indeed, numerous specific details are set forth in the foregoing description to provide a thorough and illustrative description of embodiments of this disclosure. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details described herein. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of this disclosure. Generally, it should be understood that various other devices, systems, and methods, besides those specific embodiments disclosed herein, may also be within the scope of this disclosure.

Claims

1. A semiconductor device assembly comprising: A first semiconductor wafer has a first side and a second side opposite to the first side; A first layer includes a first plurality of semiconductor devices located on the first side, wherein the outer surface of the first layer is continuous on the first semiconductor wafer; A plurality of non-metallic through holes extending from the second side toward the first side to the inner surface of the first layer; Multiple alignment marks, each alignment mark being vertically aligned with one or more of the corresponding non-metallic through holes; Second semiconductor chip; The second layer includes a second plurality of semiconductor devices, wherein the outer surface of the second layer is continuous on the second semiconductor wafer; as well as On the outer surface of the second layer, there are multiple overlapping marks, each of which is vertically aligned with one or more of the corresponding alignment marks.

2. The semiconductor device assembly of claim 1, wherein the plurality of overlapping marks are visible through the plurality of non-metallic vias and the first layer in a wavelength spectrum in the range of 400 to 700 nm.

3. The semiconductor device assembly of claim 2, wherein the periphery of each of the plurality of non-metallic vias overlaps with at least a portion of one or more of the plurality of overlapping marks.

4. The semiconductor device assembly of claim 2, wherein the periphery of each of the plurality of non-metallic vias overlaps with the periphery of each of the corresponding one or more of the plurality of overlapping marks.

5. The semiconductor device assembly of claim 1, wherein at least one of the plurality of alignment marks is formed on a surface of the plurality of semiconductor devices opposite to the first side of the first semiconductor wafer and is located within the coverage area of ​​one of the plurality of semiconductor devices.

6. The semiconductor device assembly of claim 1, wherein the plurality of alignment marks are formed on the second side of the first semiconductor wafer.

7. The semiconductor device assembly of claim 1, wherein at least one of the plurality of non-metallic vias is formed within a coverage area of ​​one of the plurality of semiconductor devices.

8. The semiconductor device assembly of claim 1, wherein one or more of the plurality of non-metallic vias are formed along the periphery of each of the plurality of alignment marks.

9. The semiconductor device assembly of claim 1, wherein the plurality of non-metallic vias are filled with a material selected from epoxy resin, silicon carbide, silicon oxide, silicon dioxide, or combinations thereof.

10. A method of manufacturing a semiconductor device assembly, comprising: A first plurality of semiconductor devices are formed in a first layer on a first side of a first semiconductor wafer, wherein the outer surface of the first layer is continuous on the first semiconductor wafer; A plurality of non-metallic vias are formed extending from a second side of the first semiconductor wafer toward the first side to the inner surface of the first layer, wherein the second side is opposite to the first side; Multiple alignment marks are formed, and each alignment mark is vertically aligned with one or more of the corresponding non-metallic through holes; A second plurality of semiconductor devices are formed in a second layer on a second semiconductor wafer, wherein the outer surface of the second layer is continuous on the second semiconductor wafer; Multiple overlapping marks are formed on the outer surface of the second layer; as well as Align the first semiconductor wafer with the second semiconductor wafer such that each of the plurality of overlapping marks is vertically aligned with one or more of the corresponding alignment marks.

11. The method of claim 10, wherein aligning the first semiconductor wafer with the second semiconductor wafer includes viewing one or more of the plurality of non-metallic vias in a wavelength spectrum in the range of 400 to 700 nm and viewing one or more of the plurality of overlapping marks through the first layer.

12. The method of claim 10, wherein aligning the first semiconductor wafer with the second semiconductor wafer includes aligning the periphery of each of the plurality of non-metallic vias to partially overlap the periphery of each of the plurality of overlapping marks.

13. The method of claim 10, wherein aligning the first semiconductor wafer with the second semiconductor wafer includes aligning the periphery of each of the plurality of non-metallic vias to overlap with the periphery of each of the plurality of overlapping marks.

14. The method of claim 10, wherein forming the plurality of alignment marks comprises forming the plurality of alignment marks on a surface of the plurality of semiconductor devices opposite to the first side of the first semiconductor wafer and within a coverage area of ​​one of the plurality of semiconductor devices.

15. The method of claim 10, wherein forming the plurality of alignment marks further comprises forming the plurality of alignment marks on the second side of the first semiconductor wafer.

16. The method of claim 14, wherein forming the plurality of non-metallic vias further comprises forming at least one of the plurality of non-metallic vias within the coverage area of ​​one of the plurality of semiconductor devices.

17. The method of claim 16, wherein forming the plurality of non-metallic vias further comprises forming one or more of the plurality of non-metallic vias along the periphery of each of the plurality of alignment marks to be vertically aligned and correspond to each of the plurality of overlapping marks.

18. The method of claim 17, further comprising filling the plurality of non-metallic through-holes with a material selected from epoxy resin, silicon carbide, silicon oxide, silicon dioxide, or combinations thereof.

19. A semiconductor device assembly comprising: A first semiconductor wafer has a first side and a second side opposite to the first side; A first plurality of semiconductor devices located on the first side; A plurality of non-metallic through holes extending from the second side toward the first side, wherein the width of each of the plurality of non-metallic through holes is between 1 and 15 μm; Multiple alignment marks, each alignment mark being vertically aligned with one or more of the corresponding non-metallic through holes; Second semiconductor chip; The second multiple semiconductor devices; as well as Multiple overlapping marks, each of which is vertically aligned with one or more of the corresponding alignment marks; The periphery of each of the plurality of non-metallic vias overlaps the periphery of each of the plurality of overlapping marks, and at least one of the plurality of non-metallic vias is formed between two adjacent coverage areas of the first plurality of semiconductor devices. The plurality of overlapping marks are visible through the plurality of non-metallic vias in a wavelength spectrum ranging from 400 to 700 nm, and The plurality of non-metallic through-holes are filled with a material selected from epoxy resin, silicon carbide, silicon oxide, silicon dioxide, or combinations thereof.

20. The semiconductor device assembly of claim 19, wherein the periphery of each of the plurality of non-metallic vias overlaps with at least a portion of one or more of the corresponding overlapping marks of the plurality of overlapping marks.

Images