Array substrate, manufacturing method and display panel

Abstract

This application relates to an array substrate, a fabrication method, and a display panel. The array substrate includes a substrate body, a connection layer, conductive lines, and a wiring layer. The substrate body includes a first surface and a second surface disposed opposite to each other, and a first side surface located between the first and second surfaces. The first surface is used to house micro-light-emitting units, and the second surface is used to house driving circuits. The connection layer is disposed on the first side surface and extends to a portion of the first surface and a portion of the second surface. The conductive lines are located on the outer surface of the connection layer away from the substrate body, and one end of the conductive lines is electrically connected to the micro-light-emitting units located on the first surface, and the other end of the conductive lines is electrically connected to the driving circuit located on the second surface. The wiring layer is located on the first surface and is used to connect the micro-light-emitting units and the conductive lines, and / or the wiring layer is located on the second surface and is used to connect the driving circuit and the conductive lines. This application can reduce fabrication difficulty and improve the yield of array substrates.

Description

Technical Field

[0001] This application relates to the field of microdisplay device technology, and in particular to array substrates, fabrication methods and display panels. Background Technology

[0002] Micro LED boasts advantages such as self-illumination, high efficiency, low power consumption, high integration, and high stability, offering broad market prospects. Currently, increasingly larger screens are a common pursuit, typically achieved through Micro LED splicing. To realize large-size splicing of micro-LED displays, an extremely narrow bezel on the back panel or side bezel wiring is required. However, in existing Micro LED display technologies, achieving extremely narrow or borderless bezels is difficult; side bezel wiring is prone to breakage or open circuits, affecting the display panel's performance. Summary of the Invention

[0003] In view of this, the main technical problem to be solved by this application is to provide an array substrate that can solve the problem of broken side traces on the array substrate and improve the stability of the array substrate in use.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing an array substrate, including a substrate body, a connection layer, conductive lines, and a wiring layer. The substrate body includes a first surface and a second surface disposed opposite to each other, and a first side surface located between the first surface and the second surface. The first surface is used to dispose of micro-light-emitting units, and the second surface is used to dispose of driving circuits. The connection layer is disposed on the first side surface and extends to a portion of the first surface and a portion of the second surface. The conductive lines are located on the outer surface of the connection layer away from the substrate body, and one end of the conductive lines is electrically connected to the micro-light-emitting units located on the first surface, and the other end of the conductive lines is electrically connected to the driving circuit located on the second surface. The wiring layer is located on the first surface and is used to connect the micro-light-emitting units and the conductive lines, and / or the wiring layer is located on the second surface and is used to connect the driving circuit and the conductive lines.

[0005] The wiring layer includes several intervals of wiring.

[0006] The conductive circuit includes a plurality of wires, which are spaced apart along a first direction and extend along a first surface to a first side surface and to a second surface.

[0007] The traces are connected to the corresponding conductors, and the traces are perpendicular to the first direction or at an acute angle.

[0008] The first surface includes a first sub-surface and a first step surface, and the distance between the first step surface and the second surface is less than the distance between the first sub-surface and the second surface.

[0009] The second surface includes a second sub-surface and a second step surface, and the distance between the second step surface and the first surface is less than the distance between the second sub-surface and the first surface.

[0010] The first surface includes a first sub-surface and a first stepped surface, and the distance between the first stepped surface and the second surface is less than the distance between the first sub-surface and the second surface; the second surface includes a second sub-surface and a second stepped surface, and the distance between the second stepped surface and the first surface is less than the distance between the second sub-surface and the first surface; the substrate body between the first stepped surface, the second stepped surface and the first side surface forms a boss structure.

[0011] The connecting layer comprises, in sequence, a first connecting portion, a second connecting portion, and a third connecting portion that are interconnected. The first connecting portion is disposed on a first stepped surface, the second connecting portion is disposed on a first side surface, and the third connecting portion is disposed on a second stepped surface.

[0012] The side of the first connecting portion facing away from the first step surface is on the same plane as at least a portion of the first sub-surface closest to the first step surface; and / or,

[0013] The side of the second connecting portion that faces away from the second step surface is on the same plane as at least a portion of the second sub-surface that is close to the second step surface.

[0014] The first sub-surface has a first end face between itself and the boss structure, and the second sub-surface has a second end face between itself and the boss structure; the first end face has a first gap with the connecting layer, and / or the second end face has a second gap with the connecting layer.

[0015] The array substrate also includes insulating layers disposed in the first gap and / or the second gap, respectively.

[0016] The array substrate also includes an adhesive layer, which is disposed between the connecting layer and the substrate body.

[0017] This application also includes a second technical solution: a display panel, comprising a micro-light-emitting unit, a driving circuit, and the aforementioned array substrate; the micro-light-emitting unit is disposed on a first surface of the array substrate; and the driving circuit is disposed on a second surface of the array substrate.

[0018] This application also includes a third technical solution, a method for fabricating an array substrate, including:

[0019] A connecting layer is sequentially disposed on a portion of the first surface, the first side surface, and the second surface of the substrate body. A conductive line is disposed on the connecting layer away from the substrate body. The conductive line extends along the first surface to the first side surface and the second surface. The first surface is used to support the micro-light-emitting unit, and the second surface is used to support the driving circuit.

[0020] A wiring layer is fabricated on a first surface and / or a second surface. The wiring layer is used to connect the micro-light-emitting unit and the conductive line, and / or the wiring layer is used to connect the driving circuit and the conductive line.

[0021] The connection layer is sequentially disposed on a portion of the first surface, the first side surface, and the second surface of the substrate body. Conductive lines are disposed on the connection layer away from the substrate body, extending along the first surface to the side surface and the second surface, including:

[0022] The first and second surfaces of the substrate body near the first side are etched to form a first step surface and a second step surface, such that the first surface includes a first sub-surface and a first step surface, and the second surface includes a second sub-surface and a second step surface.

[0023] A connecting layer with conductive lines is disposed on the first step surface, the first side surface, and the second step surface, such that the connecting layer is located between the conductive lines and the substrate body.

[0024] Fabricating a conductive layer on the first surface and / or the second surface includes:

[0025] A conductive layer is fabricated on the first sub-surface and / or the second sub-surface; the conductive layer is etched to form a trace layer with spaced traces.

[0026] The beneficial effects of this application are as follows: Unlike the prior art, the array substrate provided in this application can connect conductive lines and the substrate body by setting a connection layer. The conductive lines are located on a portion of the first surface, a portion of the first side, and a portion of the second surface of the substrate body. This allows the conductive lines to connect the micro-light-emitting units and driving circuits on opposite sides of the substrate body. The conductive lines in this embodiment are less prone to breakage, resulting in a high yield and a long service life for the array substrate. Furthermore, by setting a wiring layer, this application allows the wiring layer to connect one end of the conductive lines to the micro-light-emitting units, or / and the other end of the conductive lines to the driving circuit. This facilitates alignment of the conductive lines with the micro-light-emitting units and driving circuits during the fabrication process, improving the situation where the array substrate is difficult to connect with the micro-light-emitting units or driving circuits during fabrication. Simultaneously, by setting a wiring layer, the misalignment at the interface between the conductive lines and the micro-light-emitting units and / or driving circuits caused by material expansion during use can be mitigated, thereby reducing the fabrication difficulty of the array substrate and improving its stability in use. Attached Figure Description

[0027] Figure 1 This is a cross-sectional structural schematic diagram of the first embodiment of the display panel of this application;

[0028] Figure 2 This is a cross-sectional structural schematic diagram of the second embodiment of the display panel of this application;

[0029] Figure 3 This is a cross-sectional structural schematic diagram of the third embodiment of the display panel of this application;

[0030] Figure 4 This is a cross-sectional structural schematic diagram of the first embodiment of the array substrate of this application;

[0031] Figure 5 yes Figure 1 A top-view structural diagram;

[0032] Figure 6a This is a schematic diagram of a planar structure of an embodiment of a conductive circuit;

[0033] Figure 6b yes Figure 6a A cross-sectional structural schematic diagram of one embodiment;

[0034] Figure 7 This is a cross-sectional structural schematic diagram of the second embodiment of the array substrate of this application;

[0035] Figure 8 This is a cross-sectional structural schematic diagram of the fourth embodiment of the display panel of this application;

[0036] Figure 9 This is a cross-sectional structural schematic diagram of the fifth embodiment of the display panel of this application;

[0037] Figure 10 This is a cross-sectional structural schematic diagram of the sixth embodiment of the display panel of this application;

[0038] Figure 11 This is a cross-sectional structural schematic diagram of the seventh embodiment of the display panel of this application;

[0039] Figure 12 This is a cross-sectional structural schematic diagram of the eighth embodiment of the display panel of this application;

[0040] Figure 13a and Figure 13b This is a cross-sectional structural schematic diagram of an embodiment of the display panel manufacturing process of this application;

[0041] Figure 14 This is a flowchart of the method for manufacturing the display panel of this application;

[0042] Figure 15 This is a flowchart of the method for manufacturing the display panel in this application. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0044] Please see Figures 1-3This application provides an array substrate, including a substrate body 100, a connection layer 200, conductive lines 300, and a wiring layer 400. The substrate body 100 includes a first surface 110 and a second surface 120 disposed opposite to each other, and a first side surface 130 located between the first surface 110 and the second surface 120 (see...). Figure 4 The first surface 110 is used to house the micro-light-emitting unit 600, and the second surface 120 is used to house the driving circuit 700. The connecting layer 200 is disposed on the first side surface 130 and extends to a portion of the first surface 110 and a portion of the second surface 120. The conductive line 300 is located on the outer surface of the connecting layer 200 away from the substrate body 100, and one end of the conductive line 300 is electrically connected to the micro-light-emitting unit 600 located on the first surface 110, and the other end of the conductive line 300 is electrically connected to the driving circuit 700 located on the second surface 120. The wiring layer 400 is located on the first surface 110 and is used to connect the micro-light-emitting unit 600 and the conductive line 300, or / and the wiring layer 400 is located on the second surface 120 and is used to connect the driving circuit 700 and the conductive line 300.

[0045] In this embodiment, the conductive lines 300 and the substrate body 100 can be connected by the connection layer 200. The conductive lines 300 are disposed in a portion of the first surface 110, a portion of the first side surface 130, and a portion of the second surface 120 of the substrate body 100. The conductive lines 300 can connect the micro-light-emitting units 600 and the driving circuit 700 on opposite sides of the substrate body 100. The conductive lines 300 in this embodiment are not easily broken, resulting in a high yield of the array substrate and a long service life. In this embodiment, by providing a wiring layer 400, one end of the wiring layer 400 connecting the conductive line 300 can be connected to the micro-light-emitting unit 600, and / or the other end of the wiring layer 400 connecting the conductive line 300 to the driving circuit 700. This makes it easier for the conductive line 300 to align with the micro-light-emitting unit 600 and the driving circuit 700 during the fabrication process of the array substrate, improving the situation where it is difficult for the array substrate to connect with the micro-light-emitting unit 600 or the driving circuit 700 during the fabrication process. At the same time, by providing a wiring layer 400, the misalignment at the interface between the conductive line 300 and the micro-light-emitting unit 600 and / or the driving circuit 700 caused by the expansion of the material during the use of the array substrate can be improved, thereby reducing the fabrication difficulty of the array substrate and improving the stability of the array substrate in use.

[0046] In this embodiment, the micro-light-emitting unit 600 includes a light-emitting body (not shown) and an electrode (not shown). In this embodiment, the conductive line 300 is directly connected to the electrode of the micro-light-emitting unit 600. In another embodiment, the micro-light-emitting unit 600 further includes electrode lines (not shown). The electrode lines of several micro-light-emitting units 600 can be connected to each other or to the conductive line 300 or the wiring layer 400 respectively.

[0047] In the embodiments of this application, such as Figure 5 As shown, the wiring layer 400 includes a plurality of traces 430. As a preferred embodiment, the wiring layer 400 in this application embodiment is fabricated by a patterned conductive layer (not shown); more preferably, the wiring layer 400 is fabricated by etching a conductive layer. During the fabrication process of the wiring layer 400 of the array substrate in this application embodiment, see [link to documentation]. Figures 1-3 First, a conductive layer is deposited on the first surface 110 and / or the second surface 120. Then, the conductive layer is etched to form a wiring layer 400 with a plurality of traces 430. The shape and arrangement of the traces 430 fabricated by this method are easy to control, making it easy to align and connect the conductive lines 300 with the micro-light-emitting units 600, and / or make it easy to align and connect the conductive lines 300 with the driving circuit 700. The wiring layer 400 configuration of this embodiment can reduce the difficulty of fabricating and aligning the traces 430, thereby reducing the fabrication difficulty of the array substrate.

[0048] In this embodiment of the application, the following continues... Figures 1-3 As shown, for easy distinction, the wiring layer 400 includes a first wiring layer 410 and a second wiring layer 420. The first wiring layer 410 is located on the first surface 110 and is used to electrically connect the micro light-emitting unit 600 and the conductive line 300. The second wiring layer 420 is located on the second surface 120 and is used to electrically connect the driving circuit 700 and the conductive line 300.

[0049] In one embodiment of this application, during the fabrication of the array substrate, a first interval 510 is provided between the micro-light-emitting unit 600 and the conductive line 300 (see...). Figure 13b The first trace layer 410 is located within the first spacing 510; and / or the drive circuit 700 and the conductive line 300 have a second spacing 520 (see...). Figure 13b The second wiring layer 420 is located within the second interval 520.

[0050] In one embodiment of this application, during the fabrication process of the array substrate, such as Figure 2As shown, one end of the conductive line 300 is aligned and electrically connected to the micro-light-emitting unit 600, which increases the difficulty of aligning and connecting the other end of the conductive line 300 to the driving circuit 700. In this embodiment, a second gap 520 is provided between the other end of the conductive line 300 and the driving circuit 700 (see...). Figure 13b The second wiring layer 420 is located within the second spacing 520, electrically connecting the drive circuit 700 to the other end of the conductive line 300. In another embodiment, such as Figure 1 As shown, the other end of the conductive line 300 is aligned and electrically connected to the driving circuit 700, which increases the difficulty of aligning and connecting one end of the conductive line 300 with the micro-light-emitting unit 600. In this embodiment, a first gap 510 is provided between one end of the conductive line 300 and the micro-light-emitting unit 600 (see...). Figure 13b The first wiring layer 410 is located within the first spacing 510, electrically connecting the micro-light-emitting unit 600 to one end of the conductive line 300. In another embodiment, such as Figure 3 As shown, the array substrate includes both a first wiring layer 410 and a second wiring layer 420. The first wiring layer 410 is located at a first spacing 510 (see...). Figure 13b In the second wiring layer 420, the second wiring layer 420 is located in the second interval 520 (see...). Figure 13b In the first wiring layer 410, the micro-light-emitting unit 600 and one end of the conductive line 300 are electrically connected, and the second wiring layer 420 is electrically connected to the other end of the conductive line 300 and the driving circuit 700.

[0051] In the embodiments of this application, such as Figure 3 , Figure 5 and Figure 6a As shown, the conductive line 300 includes a plurality of wires 310, which are spaced apart along a first direction D1 and extend along a first surface 110 to a first side surface 130 and to a second surface 120. In this embodiment, the wires 310 extend along the first surface 110 to the first side surface 130, and their extension direction is perpendicular to the first direction D1; in this embodiment, the plurality of wires 310 do not contact each other.

[0052] In the embodiments of this application, such as Figure 5As shown, trace 430 is connected to wire 310, and the angle between trace 430 and the first direction D1 is an acute angle. In this embodiment, trace 430 is made by etching a conductive layer, which allows for diverse arrangement of trace 430. In this embodiment, the angle between trace 430 and the first direction D1 is an acute angle, so that if the micro-light-emitting unit 600 is misaligned with wire 310, or / and the driving circuit 700 is misaligned with wire 310, trace 430 can be tilted to connect micro-light-emitting unit 600 and wire 310, or / and the driving circuit 700 and wire 310. In this embodiment, wire 310 is set as a straight line. In other embodiments, wire 310 can also be set as a non-straight line, for example, as a curve. The angle between the overall extension direction of wire 310 and the first direction D1 is an acute angle, which can also be used to overcome the misalignment of micro-light-emitting unit 600 and wire 310, or / and the driving circuit 700 and wire 310. In another embodiment, the trace 430 is connected to the wire 310, and the trace 430 is perpendicular to the first direction D1. When the micro-light-emitting unit 600 is directly opposite the wire 310, and / or the driving circuit 700 is directly opposite the wire 310, the embodiment of this application may also provide a trace layer 400, so that the conductive line 300 does not need to precisely limit the length of the wire 310, thereby reducing the requirements for process precision during the fabrication of the array substrate and improving the yield of the array substrate.

[0053] In the embodiments of this application, such as Figure 7 and Figure 8As shown, the first surface 110 includes a first sub-surface 111 and a first stepped surface 112, and the distance between the first stepped surface 112 and the second surface 120 is less than the distance between the first sub-surface 111 and the second surface 120; the second surface 120 includes a second sub-surface 121 and a second stepped surface 122, and the distance between the second stepped surface 122 and the first surface 110 is less than the distance between the second sub-surface 121 and the first surface 110; the substrate body 100 between the first stepped surface 112, the second stepped surface 122 and the first side surface 130 forms a boss structure 140. In this embodiment, the first step surface 112 is used to reduce the height difference between the connection layer 200 and the first sub-surface 111, and the second step surface 122 is used to reduce the height difference between the connection layer 200 and the second sub-surface 121. By providing the boss structure 140, the array substrate of this embodiment can reduce the height difference between the connection layer 200 and the first sub-surface 111, as well as the height difference between the connection layer 200 and the second sub-surface 121, thereby reducing the height difference between the conductive line 300 and the first sub-surface 111 and the second sub-surface 121. This increases the contact surface at the connection between the conductive line 300 and the wiring layer 400, reducing the possibility of the conductive line 300 disconnecting from the wiring layer 400. This enhances the connection stability between the conductive line 300 and the wiring layer 400, and also reduces the possibility of the conductive line 300 disconnecting from the micro-light-emitting unit 600 or the driving circuit 700, improving the stability of the array substrate's circuit connections. On the other hand, it can also reduce the thickness of the array substrate.

[0054] In other embodiments, the first step surface 112 may be provided only on the first surface 110, and the second step surface 112 may not be provided on the second surface 120. That is, the first surface 110 includes a first sub-surface 111 and a first step surface 112, and the distance between the first step surface 112 and the second surface 120 is smaller than the distance between the first sub-surface 111 and the second surface 120. When the wiring layer 400 is provided on the first surface 110, the height difference between the connection layer 200 and the first sub-surface 111 can be reduced, reducing the possibility of the wiring layer 400 on the first sub-surface 111 being disconnected from the conductive line 300. In another embodiment, the second step surface 112 may be provided only on the second surface 120, and the first step surface 112 may not be provided on the first surface 110. That is, the second surface 120 includes a second sub-surface 121 and a second step surface 112, and the distance between the second step surface 112 and the first surface 110 is smaller than the distance between the second sub-surface 121 and the first surface 110. When the wiring layer 400 is disposed on the second surface 120, the height difference between the connection layer 200 and the second sub-surface 121 can be reduced, thereby reducing the possibility of the wiring layer 400 on the second sub-surface 121 being disconnected from the conductive line 300.

[0055] In this embodiment, a first recess (not shown) is provided on the first surface 110, with a through portion of the first side surface 130, and a second recess (not shown) is provided on the second surface 120, with a through portion of the first side surface 130, thereby forming a boss structure 140 on the substrate body 100 between the first and second recesses. The surface of the first recess forms a first step surface 112, and the surface of the second recess forms a second step surface 122. In this embodiment, only one first recess and one second recess are provided, so that the number of first step surfaces 112 on the first surface 110 is one, and the number of second step surfaces 122 on the second surface 120 is one. In other embodiments, the number of first recesses can be two or more, the number of second recesses can be two or more, the number of first step surfaces 112 can be two or more, and the number of second step surfaces 122 can be two or more. By providing two or more first step surfaces 112 and second step surfaces 122, the bonding strength between the connecting layer 200 and the substrate body 100 can be improved, thereby improving the bonding strength between the conductive line 300 and the substrate body 100.

[0056] In one embodiment of this application, the connecting layer 200 sequentially includes a first connecting portion 230, a second connecting portion 240, and a third connecting portion 250 that are interconnected. The first connecting portion 230 is disposed on a first step surface 112, the second connecting portion 240 is disposed on a first side surface 130, and the third connecting portion 250 is disposed on a second step surface 122. In this embodiment of the application, there is one first step surface 112 and one second step surface 122.

[0057] In one embodiment of this application, the side of the first connecting portion 230 facing away from the first step surface 112 is on the same plane as at least a portion of the first sub-surface 111 on the side close to the first step surface 112; the side of the second connecting portion 240 facing away from the second step surface 122 is on the same plane as at least a portion of the second sub-surface 121 on the side close to the second step surface 122. In this embodiment, by providing the boss structure 140, the height difference between the first connecting portion 230 and the first sub-surface 111 can be reduced. When the first connecting portion 230 is on the same plane as the first sub-surface 111, away from the first step surface 112, the height difference between the first connecting portion 230 and the first sub-surface 111 is zero. This makes one end of the conductive line 300 on the first connecting portion 230 and the first wiring layer 410 on the same horizontal plane, making the first wiring layer 410 easier to manufacture and resulting in higher connection stability between the manufactured first wiring layer 410 and the conductive line 300. Alternatively, one end of the conductive line 300 on the first connecting portion 230 can be on the same horizontal plane as the micro-light-emitting unit 600, resulting in higher connection stability between the conductive line 300 and the micro-light-emitting unit 600 and less likelihood of circuit breakage. In this embodiment, the first sub-surface 111 is parallel to the second sub-surface 121. Therefore, the first connecting portion 230 is on the same plane as the first sub-surface 111, away from the first step surface 112. In other embodiments, the first sub-surface 111 is not parallel to the second sub-surface 121, or the first sub-surface 111 is not planar. The side of the first connecting portion 230 that is away from the first step surface 112 only needs to be on the same horizontal plane as the part of the first sub-surface 111 that is close to the first step surface 112, thereby improving the connection stability between one end of the conductive line 300 and the first wiring layer 410 or the micro-light-emitting unit 600.

[0058] Similarly, in this embodiment, the boss structure 140 reduces the height difference between the third connecting portion 250 and the second sub-surface 121. When the third connecting portion 250 is on the same plane as the second sub-surface 121 and away from the second step surface 122, the height difference between the third connecting portion 250 and the second sub-surface 121 is zero. This makes the other end of the conductive line 300 on the third connecting portion 250 and the second wiring layer 420 on the same horizontal plane, making the second wiring layer 420 easier to manufacture and resulting in a higher connection stability between the manufactured second wiring layer 420 and the conductive line 300. Alternatively, the other end of the conductive line 300 on the third connecting portion 250 can be on the same horizontal plane as the driving circuit 700, resulting in a higher connection stability between the conductive line 300 and the driving circuit 700 and less likelihood of breakage. In this embodiment, the first sub-surface 111 is parallel to the second sub-surface 121; therefore, the third connecting portion 250 is on the same plane as the second sub-surface 121 and away from the second step surface 122. In other embodiments, the first sub-surface 111 and the second sub-surface 121 are not parallel, or the second sub-surface 121 is non-planar. The side of the third connecting portion 250 facing away from the second step surface 122 only needs to be on the same horizontal plane as a portion of the second sub-surface 121 near the second step surface 122, thus improving the connection stability between the other end of the conductive line 300 and the second wiring layer 420 or the driving circuit 700. In this embodiment, the side of the first connecting portion 230 facing away from the first step surface 112 is on the same plane as at least a portion of the first sub-surface 111 near the first step surface 112; simultaneously, the side of the second connecting portion 240 facing away from the second step surface 122 is on the same plane as at least a portion of the second sub-surface 121 near the second step surface 122. In other embodiments, it is also possible that the side of the first connecting portion 230 facing away from the first step surface 112 is on the same plane as at least a portion of the first sub-surface 111 on the side close to the first step surface 112, or the side of the second connecting portion 240 facing away from the second step surface 122 is on the same plane as at least a portion of the second sub-surface 121 on the side close to the second step surface 122.

[0059] In this embodiment, a first end face 150 is formed between the first sub-surface 111 and the boss structure 140, and a second end face 160 is formed between the second sub-surface 121 and the boss structure 140; a first gap 530 is formed between the first end face 150 and the connecting layer 200, and / or a second gap 540 is formed between the second end face 160 and the connecting layer 200; the array substrate further includes an insulating layer 550, which is respectively disposed in the first gap 530 and / or the second gap 540. In this embodiment, as... Figure 13a As shown, when the first gap 530 is present, the electrodes or electrode lines of the micro-light-emitting unit 600 are prone to tilting at the first gap 530, or the first wiring layer 410 is prone to breakage at the first gap 530; for example Figure 9 and Figure 10 As shown, by providing the insulating layer 550, the possibility of a break in the connection between one end of the conductive line 300 and the first trace layer 410, or the possibility of a break in the connection between one end of the conductive line 300 and the micro-light-emitting unit 600, can be reduced. Simultaneously, the insulating layer 550 ensures that there is no mutual interference between the first traces 410, between the micro-light-emitting units 600, or between the wires 310. Figure 13a As shown, when the second gap 540 is present, there is a second gap 520 between the drive circuit 700 and the conductive line 300 (see...). Figure 13b The drive circuit 700 and the conductive line 300 are connected by setting a second wiring layer 420, such as... Figure 11 and Figure 12 As shown, by setting an insulating layer 550 in the second spacing 520, the second wiring layer 420 is less prone to breakage, thereby improving the yield and stability of the array substrate. Figure 8 and Figure 9 As shown, in other embodiments, when there is a first gap 530 and no second gap 540, the insulating layer 550 is only disposed in the first gap 530; as Figure 11 As shown, or when there is a second gap 540 but no first gap 530, the insulating layer 550 is only disposed in the second gap 540.

[0060] In the embodiments of this application, such as Figures 11-12 As shown, the array substrate also includes an adhesive layer 800, which is disposed between the connecting layer 200 and the substrate body 100. In this embodiment, by providing the adhesive layer 800, the connecting layer 200 can be adhered to the substrate body 100. The connecting layer 200 is made of a heat-resistant and structurally robust material, so that the connecting layer 200 is not easily deformed when heat is generated during use of the array substrate, and the conductive lines 300 located on the connecting layer 200 are not easily lifted or misaligned. This makes it less likely for the conductive lines 300 to be disconnected from the micro-light-emitting unit 600 and the driving circuit 700, thereby improving the stability and service life of the array substrate. In this embodiment, the connecting layer 200 is made of PI material, and the adhesive layer 800 is made of photoresist. The above is only an example; in other embodiments, the materials of the connecting layer 200 and the adhesive layer 800 can be other materials. In other embodiments, the connecting layer 200 may also be a layer with a certain degree of adhesiveness, which can be directly adhered to the substrate body 100, or the connecting layer 200 may be disposed on the substrate body 100 in other ways.

[0061] This application also includes a second technical solution, a display panel, such as... Figure 1As shown, the display panel includes a micro-light-emitting unit 600, a driving circuit 700, and the aforementioned array substrate. The micro-light-emitting unit 600 is disposed on the first surface 110 of the array substrate; the driving circuit 700 is disposed on the second surface 120 of the array substrate. In this embodiment, the display panel, by employing the aforementioned array substrate, allows for side bezel wiring 430 to connect the micro-light-emitting units 600 and the array substrate disposed on opposite surfaces, resulting in a narrower bezel. The display panel in this embodiment, using the aforementioned array substrate, exhibits good stability as the conductive lines 300 are less prone to breakage, and the array substrate has a high yield and long service life.

[0062] This application also includes a third technical solution, such as Figure 14 As shown, the method for fabricating the array substrate includes:

[0063] S110: As Figure 1 , Figure 6a and Figure 4 As shown, a connecting layer 200 is sequentially disposed on a portion of the first surface 110, the first side surface 130, and the second surface 120 of the substrate body 100. A conductive line 300 is disposed on the connecting layer 200 away from the substrate body 100. The conductive line 300 extends along the first surface 110 to the first side surface 130 and the second surface 120. The first surface 110 is used to support the micro-light-emitting unit 600, and the second surface 120 is used to support the driving circuit 700.

[0064] In this embodiment of the application, the substrate body 100 includes a first surface 110 and a second surface 120 disposed opposite to each other, and includes a plurality of side surfaces perpendicular to the first surface 110 and the second surface 120, for example, including four side surfaces. In this embodiment of the application, one of the side surfaces is selected as the first side surface 130.

[0065] In the embodiments of this application, during the manufacturing process, such as Figure 6a , Figure 6b and Figure 1As shown, the conductive lines 300 can be pre-formed on the planar connecting layer 200. Since the conductive lines 300 only need to be formed on a planar plate, their fabrication is easier, resulting in higher flatness. It also eliminates the need to form continuous conductive lines 300 on a three-dimensional surface, making the fabricated conductive lines 300 less prone to breakage. Specifically, in one embodiment of this application, the conductive lines 300 consist of several conductors 310, and are directly disposed on the planar connecting layer 200. In another embodiment of this application, the conductive lines 300 can also be formed by deposition and etching on the planar connecting layer 200. In this embodiment, when the conductive lines 300 are fabricated by deposition and etching on the planar connecting layer 200, the conductors 310 in the conductive lines 300 are less prone to breakage, resulting in high integrity.

[0066] In this embodiment, by further disposing the connecting layer 200 on a portion of the first surface 110, the first side surface 130, and the second surface 120 of the substrate body 100, the connecting layer 200 extends along the first surface 110 to the first side surface 130 and further to the second surface 120. At this time, a conductive line 300 is disposed on the connecting layer 200, which means that the conductive line 300 can be disposed on a portion of the first surface 110, the first side surface 130, and the second surface 120 of the substrate body 100. At this time, the conductive line 300 is located on the side of the connecting layer 200 away from the substrate body 100, so that the connecting layer 200 and the substrate body 100 are well disposed. In another embodiment, an adhesive layer 800 is provided on a surface of the connecting layer 200 away from the conductive layer. The connecting layer 200 can be adhered to the outer periphery of one end of the substrate body 100 through the adhesive layer 800, so that the conductive lines 300 can be disposed on a portion of the first surface 110, the first side surface 130 and a portion of the second surface 120 of the substrate body 100. In this case, the material selection range of the connecting layer 200 is wider, and the stability of the connecting layer 200 on the array substrate can be higher, so that the conductive lines 300 are less likely to shift during the use of the array substrate.

[0067] In another embodiment of this application, the connecting layer 200 may be disposed on a portion of the first surface 110, a portion of the first side surface 130, and a portion of the second surface 120 of the substrate body 100, and then the conductive line 300 may be disposed on the surface of the connecting layer 200 away from the substrate body 100, such that the conductive line 300 extends along a portion of the first surface 110 of the substrate body 100 to the first side surface 130 and to a portion of the second surface 120.

[0068] S120: As Figure 1 , Figure 2 , Figure 3 and Figure 5 As shown, a wiring layer 400 is formed on the first surface 110 and / or the second surface 120. The wiring layer 400 is used to connect the micro-light-emitting unit 600 and the conductive line 300, and / or, the wiring layer 400 is used to connect the driving circuit 700 and the conductive line 300.

[0069] In this embodiment, when the connecting layer 200 is disposed on the substrate body 100, during the docking of the connecting layer 200 with the micro-light-emitting unit 600 on the first surface 110 or the driving circuit 700 on the second surface 120 of the substrate body 100, it is easy for one end to be docked well while the other end is difficult to dock, or for both ends to be docked poorly. This can easily cause the conductive line 300 to fail to electrically connect with the micro-light-emitting unit 600 or the driving circuit 700, or for the conductive line 300 to fail to electrically connect with both the micro-light-emitting unit 600 and the driving circuit 700 simultaneously. That is, it causes a first gap 510 (see...) between one end of the conductive line 300 and the micro-light-emitting unit 600. Figure 13b ), or / and the other end of the conductive line 300 has a first gap 510 with the driving circuit 700. In this embodiment of the application, by further fabricating a wiring layer 400, the wiring layer 400 is located at the first gap 510 or the second gap 520 (see Figure 13b Alternatively, wiring layers 400 may be fabricated in the first interval 510 and the second interval 520 respectively, such that one end of the wiring layer 400 and the conductive line 300 is connected to the micro-light-emitting unit 600, or the other end of the wiring layer 400 and the conductive line 300 is connected to the driving circuit 700, thereby realizing the electrical connection between the micro-light-emitting units 600 on the two opposite surfaces of the substrate body 100 and the driving circuit 700.

[0070] In this embodiment, the method for manufacturing the array substrate can reduce the requirements for the manufacturing process, making the array substrate easier to manufacture. The array substrate has a high yield and good stability, and is less prone to short circuits between the micro-light-emitting unit 600 and the driving circuit 700 caused by line breakage or misalignment. The side frame wiring of the manufactured array substrate can be used for splicing large screens.

[0071] In one embodiment of this application, as Figure 15 As shown, the method for fabricating the array substrate includes:

[0072] S210: As Figure 4 and Figure 7 As shown, the first surface 110 and the second surface 120 of the etched substrate body 100 near the first side surface 130 form a first step surface 112 and a second step surface 122, such that the first surface 110 includes a first sub-surface 111 and a first step surface 112, and the second surface 120 includes a second sub-surface 121 and a second step surface 122.

[0073] In this embodiment, the substrate body 100 is made of glass. In other embodiments, the substrate body may be made of other materials.

[0074] In this embodiment, the first surface 110 and the second surface 120 of the substrate body 100 are laser-etched respectively, so that a first recess is formed on the first surface 110 and a second recess is formed on the second surface 120, wherein both the first recess and the second recess penetrate the first side surface 130. This results in the first surface 110 forming a first stepped surface 112 and the second surface 120 forming a second stepped surface 122.

[0075] S220: As Figure 7 and Figure 8 As shown, a connection layer 200 with conductive lines 300 is disposed on the first step surface 112, the first side surface 130 and the second step surface 122, such that the connection layer 200 is located between the conductive lines 300 and the substrate body 100.

[0076] In the embodiments of this application, such as Figure 6a and Figure 6b As shown, the conductive lines 300 are pre-formed on the planar connecting layer 200. Since the conductive lines 300 only need to be formed on the planar plate, their fabrication is easier, resulting in higher flatness. It eliminates the need to form continuous conductive lines 300 on a three-dimensional surface, making the fabricated conductive lines 300 less prone to breakage. Specifically, in one embodiment of this application, the conductive lines 300 comprise a plurality of wires 310, and are directly disposed on the planar connecting layer 200. In another embodiment of this application, the conductive lines 300 can also be formed by deposition and etching on the planar connecting layer 200. In this embodiment, when the conductive lines 300 are fabricated by deposition and etching on the planar connecting layer 200, the wires 310 in the conductive lines 300 are less prone to breakage, resulting in high integrity.

[0077] like Figure 7 and Figure 13a As shown, in this embodiment of the application, by further disposing the connecting layer 200 on the first step surface 112, the first side surface 130, and the second step surface 122 of the substrate body 100, the connecting layer 200 extends along the first step surface 112 to the first side surface 130 and further extends to the second step surface 122; at this time, a conductive line 300 is disposed on the connecting layer 200, which means that the conductive line 300 can be disposed on a portion of the first surface 110, the first side surface 130, and the second surface 120 of the substrate body 100.

[0078] In this embodiment of the application, by setting the connecting layer 200 on the first step surface 112 and the second step surface 122, it is beneficial to reduce the height difference between the connecting layer 200 and the first sub-surface 111 and the second sub-surface 121.

[0079] like Figure 7 and Figure 13b As shown in the embodiment of this application, a first end face 150 is provided between the first sub-surface 111 and the boss structure 140, and a second end face 160 is provided between the second sub-surface 121 and the boss structure 140; a first gap 530 is provided between the first end face 150 and the connecting layer 200, and / or a second gap 540 is provided between the second end face 160 and the connecting layer 200; an insulating layer 550 is further provided in the first gap 530 and / or the second gap 540.

[0080] S230: A conductive layer is formed on the first sub-surface 111 and / or the second sub-surface 121.

[0081] In this embodiment, if the micro-light-emitting unit 600 on the first sub-surface 111 and one end of the conductive line 300 have a first gap 510, a conductive layer can be deposited on the first sub-surface 111, such that the conductive layer is located in the first gap 510. If the driving circuit 700 on the second sub-surface 121 and the other end of the conductive line 300 have a second gap 520, a conductive layer can be deposited on the second sub-surface 121, such that the conductive layer is located in the second gap 520. If the micro-light-emitting unit 600 on the first sub-surface 111 and one end of the conductive line 300 have a first gap 510, and the driving circuit 700 on the second sub-surface 121 and the other end of the conductive line 300 have a second gap 520, conductive layers can be deposited on both the first sub-surface 111 and the second sub-surface 121, such that the conductive layers are located in the first gap 510 and the second gap 520, respectively.

[0082] In this embodiment, the conductive layer can be metal or other conductive materials.

[0083] S240: As Figure 12 As shown, a conductive layer is etched to form a wiring layer 400 with spaced traces 430. The wiring layer 400 is used to connect the micro-light-emitting unit 600 and the conductive line 300, and / or, the wiring layer 400 is used to connect the driving circuit 700 and the conductive line 300.

[0084] In this embodiment, a patterned conductive layer is used to form a wiring layer 400 with spaced traces 430. Specifically, in this embodiment, the wiring layer 400 can be formed by laser etching or by wet etching of the conductive layer; the traces 430 formed by this method (see...) Figure 4The shape and arrangement of the traces 430 are easy to control, making it easy to align and connect the conductive lines 300 and the micro-light-emitting units 600, and / or make it easy to align and connect the conductive lines 300 and the driving circuit 700. The arrangement of the trace layer 400 in this embodiment can reduce the difficulty of fabricating and aligning the traces 430, thereby reducing the difficulty of fabricating the array substrate.

[0085] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array substrate, characterized in that, include: The substrate body includes a first surface and a second surface disposed opposite to each other, and a first side surface located between the first surface and the second surface. The first surface is used to dispose of micro-light-emitting units, and the second surface is used to dispose of driving circuits. A connecting layer is disposed on the first side and extends to a portion of the first surface and a portion of the second surface; A conductive line is located on the outer surface of the connection layer away from the substrate body, and one end of the conductive line is electrically connected to the micro-light-emitting unit located on the first surface, and the other end of the conductive line is electrically connected to the driving circuit located on the second surface. A wiring layer is located on the first surface for connecting the micro-light-emitting unit and the conductive line, or / and the wiring layer is located on the second surface for connecting the driving circuit and the conductive line; The first surface includes a first sub-surface and a first stepped surface, and the distance between the first stepped surface and the second surface is less than the distance between the first sub-surface and the second surface; the second surface includes a second sub-surface and a second stepped surface, and the distance between the second stepped surface and the first surface is less than the distance between the second sub-surface and the first surface; the substrate body between the first stepped surface, the second stepped surface and the first side surface forms a boss structure; The connecting layer includes a first connecting part, a second connecting part, and a third connecting part that are connected to each other. The first connecting part is disposed on the first step surface, the second connecting part is disposed on the first side surface, and the third connecting part is disposed on the second step surface.

2. The array substrate according to claim 1, characterized in that, The wiring layer includes a number of wirings spaced apart; The conductive line includes a plurality of wires, which are spaced apart along a first direction and extend along the first surface to the first side surface and to the second surface; The trace is connected to the conductor, and the trace is perpendicular to the first direction or forms an acute angle with it.

3. The array substrate according to claim 1, characterized in that, The side of the first connecting portion facing away from the first step surface is on the same plane as at least a portion of the first sub-surface closest to the first step surface; and / or, The side of the second connecting portion facing away from the second step surface is on the same plane as at least a portion of the second sub-surface on the side closest to the second step surface.

4. The array substrate according to claim 1, characterized in that, The first sub-surface has a first end face between itself and the boss structure, and the second sub-surface has a second end face between itself and the boss structure; the first end face has a first gap between itself and the connecting layer, and / or the second end face has a second gap between itself and the connecting layer; The array substrate further includes: An insulating layer is disposed in the first gap and / or the second gap, respectively.

5. The array substrate according to claim 1, characterized in that, It also includes an adhesive layer disposed between the connecting layer and the substrate body.

6. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-5; A micro-light-emitting unit, wherein the micro-light-emitting unit is disposed on the first surface of the array substrate; A driving circuit is disposed on the second surface of the array substrate.

7. A method for fabricating an array substrate, characterized in that, include: A connecting layer is sequentially disposed on a portion of the first surface, the first side surface, and the second surface of the substrate body. The connecting layer has conductive lines disposed away from the substrate body, and the conductive lines extend along the first surface to the first side surface and the second surface. The first surface is used to support the micro-light-emitting unit, and the second surface is used to support the driving circuit. A wiring layer is formed on the first surface and / or the second surface, the wiring layer being used to connect the micro-light-emitting unit and the conductive line, and / or, the wiring layer being used to connect the driving circuit and the conductive line; The connection layer is sequentially disposed on a portion of the first surface, the first side surface, and the second surface of the substrate body. The connection layer has conductive lines disposed opposite to the substrate body, and these conductive lines extend along the first surface to the first side surface and the second surface, including: The first and second surfaces of the substrate body near the side are etched to form a first step surface and a second step surface, such that the first surface includes a first sub-surface and the first step surface, and the second surface includes a second sub-surface and a second step surface. The connecting layer, on which the conductive lines are provided, is disposed on the first step surface, the first side surface, and the second step surface, such that the connecting layer is located between the conductive lines and the substrate body.

8. The method for fabricating an array substrate according to claim 7, characterized in that, The fabrication of a wiring layer on the first surface and / or the second surface includes: A conductive layer is formed on the first surface and / or the second surface; The conductive layer is etched to form a trace layer with spaced traces.

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