Piezoelectric snubber absorbing circuit and mosfet power module

Abstract

The present application belongs to the technical field of power semiconductor devices, and particularly relates to a piezoelectric buffer absorption circuit and a MOSFET power module. The piezoelectric buffer absorption circuit comprises a PZT piezoelectric ceramic and a bondable resistor in communication with each other, and the bondable resistor is arranged on the surface of the PZT piezoelectric ceramic. The MOSFET power module comprises a MOSFET chip and the aforementioned piezoelectric buffer absorption circuit, and the piezoelectric buffer absorption circuit is connected between the drain and the source of the MOSFET chip. The technical problem that the parasitic parameters of the buffer absorption circuit itself in the prior art have a great influence on the performance of the MOSFET power module and limit the optimal layout design of the circuit and the DBC is solved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and specifically relates to a piezoelectric buffer absorption circuit and a MOSFET power module. Background Technology

[0002] The rapid switching transients of MOSFET devices make them more sensitive to parasitic parameters and subject to greater electrical stress. Under harsh conditions, this can lead to device failure or even damage. Generally, a snubber circuit is added to regulate the switching behavior.

[0003] Snubber circuits are often used as peripheral circuits for MOSFET devices in MOSFET power modules. The optimal adjustment of the switching behavior of MOSFET devices is inevitably affected by the parasitic parameters of the current path of the snubber circuit itself.

[0004] Furthermore, existing snubber circuits are typically implemented using surface-mount resistors and multilayer ceramic capacitors in series. When applied to power modules, connection positions need to be reserved on the metal layer covering the DBC. The metal layer covering the DBC cannot remain intact, which introduces unfavorable factors that need to be considered, greatly limiting the optimal layout design of the circuit and the DBC. Summary of the Invention

[0005] One of the objectives of this invention is to provide a piezoelectric buffer absorption circuit to solve the technical problem that the parasitic parameters of the current path of the buffer absorption circuit itself have a significant impact on the performance of the MOSFET power module, and limit the optimal layout design of the circuit and DBC.

[0006] The piezoelectric buffer absorption circuit of the present invention includes interconnected PZT piezoelectric ceramics and bondable resistors, wherein the bondable resistors are disposed on the surface of the PZT piezoelectric ceramics.

[0007] Furthermore, the PZT piezoelectric ceramic is in the form of a single-layer sheet.

[0008] Furthermore, the PZT piezoelectric ceramic has a positive and negative electrode eccentric structure.

[0009] Furthermore, the thickness of the PZT piezoelectric ceramic is 0.2–2 mm.

[0010] Furthermore, the material of the PZT piezoelectric ceramic is selected from any one of PZT-2, PZT-4, PZT-5A, PZT-5 or PZT-8.

[0011] Furthermore, the bondable resistance is welded or sintered onto the PZT piezoelectric ceramic.

[0012] Another object of the present invention is to provide a MOSFET power module, including a MOSFET chip.

[0013] And the aforementioned piezoelectric buffer absorption circuit;

[0014] The piezoelectric buffer absorption circuit is connected between the drain and source of the MOSFET chip.

[0015] Furthermore, the MOSFET chip is a silicon carbide MOSFET chip.

[0016] Furthermore, the piezoelectric buffer absorption circuit is located on the metal layer where the drain of the MOSFET chip is located.

[0017] Furthermore, the bondable resistor on the piezoelectric buffer absorption circuit is connected to the metal layer to which the source of the MOSFET chip is connected via a bonding wire.

[0018] The principle of this invention is that the PZT piezoelectric ceramic can be equivalent to a capacitor, and it is stacked with bondable resistors to form a piezoelectric buffer absorption circuit. Compared with the RC buffer absorption circuit composed of surface-mount resistors and multilayer ceramic capacitors in series, it has the following advantages:

[0019] (1) The piezoelectric snubber circuit in this invention adopts a stacked structure. When installing the power module, it is only necessary to connect the PZT piezoelectric ceramic to the DBC overlay metal layer. The bonding resistor can be connected to other components through bonding wires. Compared with the traditional RC snubber circuit applied in the power module, the piezoelectric snubber circuit of this invention not only occupies a smaller area, but also does not require the reservation of additional lone copper connection snubber resistors and snubber capacitors on the DBC overlay metal layer, ensuring the integrity of the DBC overlay metal layer and not destroying the layout of the DBC overlay metal layer. Accordingly, the MOSFET power module in this invention, due to the adoption of this piezoelectric snubber circuit, can retain a relatively complete DBC overlay metal layer, ensuring the integrity of the current flowing through it, reducing the limiting factors that need to be considered, and making the layout optimization design for reducing module parasitic parameters more flexible.

[0020] (2) The piezoelectric snubber circuit in this invention adopts a stacked structure. Compared with the traditional RC snubber circuit used in power modules, it eliminates the connection lines between the snubber resistor and the snubber capacitor, greatly shortening the current path between the snubber circuit and the MOSFET chip. Compared with the traditional RC snubber circuit, it reduces the parasitic inductance of the loop by more than 50%, which can better suppress voltage overshoot and ringing. Accordingly, the parasitic inductance of the loop in the MOSFET power module of this invention is greatly reduced due to the use of this piezoelectric snubber circuit.

[0021] (3) The PZT piezoelectric ceramic used in the piezoelectric buffer absorption circuit of this invention can withstand higher temperatures compared to multilayer ceramic capacitors with various dielectrics, making it more suitable for high-temperature applications. The capacitance of PZT piezoelectric ceramic is positively correlated with temperature. Compared to the widely used X7R multilayer ceramic capacitor, it will not experience a drop in capacitance due to temperature increases, ensuring the suppression of voltage overshoot and ringing under various conditions. Consequently, the MOSFET power module of this invention, due to the use of this piezoelectric buffer absorption circuit, eliminates the need for a high-temperature resistant end plate required by traditional buffer absorption circuits, enabling it to adapt to higher temperatures. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall structure of the MOSFET power module packaging structure provided in an embodiment of the present invention;

[0023] Figure 2 This is a three-dimensional structural diagram of the power module body provided in an embodiment of the present invention;

[0024] Figure 3 yes Figure 2 A top view of the main body of the power module;

[0025] Figure 4 yes Figure 2 A front view of the main body of the power module;

[0026] Figure 5 This is a three-dimensional structural schematic diagram of the piezoelectric buffer absorption circuit provided in an embodiment of the present invention;

[0027] Figure 6 This is a circuit diagram of the main body of the power module provided in an embodiment of the present invention.

[0028] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures.

[0029] The reference numerals in the accompanying drawings include: 1. Kelvin source lead-out bonding wire; 2. Kelvin source busbar; 3. Gate busbar; 4. PZT piezoelectric ceramic; 5. Bondable resistor; 6. Gate lead-out bonding wire; 7. DC+ power terminal; 8. Source lead-out bonding wire; 9. DC- power terminal; 10. AC power terminal; 11. Gate terminal; 12. Kelvin source terminal; 13. Bondable resistor lead-out bonding wire; 14. MOSFET chip; 15. Test terminal; 16. Fixed terminal; 17. Package housing; 18. DBC upper metal layer; 19. DBC ceramic layer; 20. DBC lower metal layer. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0031] In the embodiments of this application, the same reference numerals are used to represent the same component or the same part. For the same part in the embodiments of this application, the reference numerals may only be used to mark one part or component as an example in the figure. It should be understood that the reference numerals are also applicable to other identical parts or components.

[0032] It should be understood that in this invention, the upper half-bridge arm and the lower half-bridge arm are symmetrical in layout and connection. Corresponding parts such as "upper half-bridge arm gate terminal" and "lower half-bridge arm gate terminal" are only marked as "gate terminal" in the drawings.

[0033] like Figure 1 As shown, the MOSFET power module packaging structure provided in this embodiment includes a packaging housing and a power module body packaged in the packaging housing; the packaging housing has a corresponding through hole so that the end of the terminal away from the upper metal layer extends to the outside of the packaging housing; the packaging housing is equipped with a fixed terminal to facilitate connection with a heat sink. Figure 2 The middle section shows the three-dimensional structure of the power module body.

[0034] like Figure 3 As shown, the main body of the power module includes a DBC component and terminals; as Figure 4 The DBC component shown includes an upper DBC metal layer, a DBC ceramic layer, and a lower DBC metal layer; the MOSFET chip and PZT piezoelectric ceramic are disposed on the upper DBC metal layer. In this embodiment, the MOSFET chip is a silicon carbide (SiC) MOSFET chip, and the upper and lower DBC metal layers are made of copper.

[0035] like Figure 5 As shown, a bondable resistor is disposed on and connected to the PZT piezoelectric ceramic, forming the piezoelectric buffer absorption circuit of this invention. In this embodiment, the bondable resistor can be connected to the PZT piezoelectric ceramic by welding or sintering, but is not limited to this method. Due to the stacked structure, compared with the traditional RC buffer absorption circuit applied in power modules, the connection lines between the buffer resistor and the buffer capacitor are eliminated, greatly shortening the current path between the buffer absorption circuit and the MOSFET chip. Compared with the traditional RC buffer absorption circuit, the parasitic inductance of the loop is reduced by more than 50%, which can better suppress voltage overshoot and ringing. Correspondingly, the parasitic inductance of the loop in the MOSFET power module is greatly reduced due to the use of this piezoelectric buffer absorption circuit.

[0036] In this embodiment, the PZT piezoelectric ceramic material can be selected from, but is not limited to, any one of PZT-2, PZT-4, PZT-5A, PZT-5, or PZT-8. Compared to multilayer ceramic capacitors with various dielectrics, PZT piezoelectric ceramics can withstand higher temperatures, making them more suitable for the high-temperature applications of silicon carbide MOSFET chips. The capacitance of PZT piezoelectric ceramics exhibits a positive correlation with temperature. Compared to traditional ceramic capacitors such as the widely used X7R multilayer ceramic capacitors, the capacitance will not drop due to temperature increases, ensuring effective suppression of voltage overshoot and ringing under various conditions. Consequently, because the MOSFET power module uses this piezoelectric buffer absorption circuit, it eliminates the need for a high-temperature resistant end plate required by traditional buffer absorption circuits, allowing it to adapt to higher temperatures overall.

[0037] like Figure 3 As shown, the Kelvin sources of all MOSFET chips in each bridge arm are connected to the Kelvin source busbar of each bridge arm via Kelvin source lead-out bonding wires. The Kelvin source terminals of each bridge arm are led out from the Kelvin source busbar. The Kelvin source reduces the common-source parasitic inductance while decoupling the drive circuit from the power circuit, increasing switching speed and mitigating gate voltage distortion caused by high current change rates. The gates of all MOSFET chips in each bridge arm are connected to the gate busbar of that bridge arm, and the gate terminals of each bridge arm are led out from the gate busbar.

[0038] The drains of all the silicon carbide MOSFET chips in the upper half of the bridge are connected together through a DBC overlay metal layer. Correspondingly, the silicon carbide MOSFET chip body of the upper half of the bridge is located on this DBC overlay metal layer, and the DC+ power terminal is led out from this DBC overlay metal layer.

[0039] The sources of all the silicon carbide MOSFET chips in the upper half of the bridge are connected to a DBC overlay metal layer via source lead-out bonding wires, and AC power terminals are led out from the DBC overlay metal layer; the drains of all the silicon carbide MOSFET chips in the lower half of the bridge are also connected to the DBC overlay metal layer, and correspondingly, the silicon carbide MOSFET chip bodies of the lower half of the bridge are located on this DBC overlay metal layer.

[0040] The sources of all the silicon carbide MOSFET chips in the lower half of the bridge are connected to a metal layer on top of a DBC via source lead-out bonding wires, and DC-power terminals are led out from the metal layer on top of the DBC.

[0041] To ensure current carrying capacity, the DC+ power terminal, AC power terminal, and DC- power terminal are composed of four copper pillars; the gate terminal and Kelvin source terminal of each bridge arm are composed of one copper pillar.

[0042] The upper and lower bridge arms are each provided with a piezoelectric buffer absorption circuit. In order to ensure performance and size, the PZT piezoelectric ceramic in this embodiment is preferably a single-layer sheet with opposite positive and negative electrode structures. The thickness of the PZT piezoelectric ceramic is preferably 0.2 to 2 mm, but is not limited to this.

[0043] The bondable resistors on each bridge arm are connected via bonding wires to the DBC metal layer, which is connected to the source of the MOSFET chip on each bridge arm. The PZT piezoelectric ceramics on each bridge arm are directly connected to the DBC metal layer containing the drain of the silicon carbide MOSFET chip in each bridge arm. The two silicon carbide MOSFET chips of each bridge arm are evenly arranged on the left and right sides of the piezoelectric snubber circuit. It is easy to see that, compared with the traditional RC snubber circuit used in power modules, this embodiment does not require additional lone copper connection snubber resistors and snubber capacitors on the DBC metal layer, ensuring the integrity of the DBC metal layer and not disrupting the original DBC layout. Because the MOSFET power module uses this piezoelectric snubber circuit, it retains the complete DBC metal layer, ensuring the integrity of the current flow and reducing the limiting factors that need to be considered in the layout optimization design to reduce module parasitic parameters.

[0044] The circuit formed by connecting various components is as follows Figure 6 As shown in the figure:

[0045] The drain and source of the two MOSFET chips (Q1, Q2) in the upper half of the bridge arm, as well as the piezoelectric snubber circuit, are connected in parallel between the DC+ power terminal (DC+) and the AC power terminal. The piezoelectric snubber circuit is an RC circuit formed by a bonding resistor (R1) and a PZT piezoelectric ceramic (C1) connected in series. The bonding resistor is directly connected to the DC+ power terminal, and the PZT piezoelectric ceramic is directly connected to the AC power terminal.

[0046] The drain and source of the two MOSFET chips (Q3, Q4) in the lower half of the bridge arm, as well as the piezoelectric snubber circuit, are connected in parallel between the AC power terminal and the DC- power terminal (DC-). The piezoelectric snubber circuit is an RC circuit formed by a bonding resistor (R2) and a PZT (C2) piezoelectric ceramic connected in series. The bonding resistor is directly connected to the AC power terminal, and the PZT piezoelectric ceramic is directly connected to the DC- power terminal.

[0047] The gates of both MOSFET chips in the upper half of the bridge are connected to gate terminal G1, and the gates of both MOSFET chips in the upper half of the bridge are connected to gate terminal G2.

[0048] In this embodiment, insulating adhesive is provided inside the encapsulation housing to achieve sealing and electrical insulation protection inside the power module. Preferably, the insulating adhesive is silicone or resin.

[0049] The embodiments described in the specific implementation of this invention are all preferred embodiments of this invention and are not intended to limit the scope of protection of this invention. Therefore, all equivalent changes made in accordance with the structure, shape, and principle of this invention should be covered within the scope of protection of this invention.

Claims

1. A piezoelectric buffer absorption circuit, characterized in that, It includes interconnected PZT piezoelectric ceramics and bondable resistors, wherein the bondable resistors are disposed on the surface of the PZT piezoelectric ceramics; The PZT piezoelectric ceramic is in the form of a single-layer sheet; The PZT piezoelectric ceramic has a positive and negative electrode eccentric structure. The thickness of the PZT piezoelectric ceramic is 0.2~2mm; The material of the PZT piezoelectric ceramic is selected from any one of PZT-2, PZT-4, PZT-5A, PZT-5 or PZT-8; The bondable resistance is welded or sintered onto the PZT piezoelectric ceramic.

2. A MOSFET power module, comprising a MOSFET chip, characterized in that, It also includes the piezoelectric buffer absorption circuit as described in any of claims 1; The piezoelectric buffer absorption circuit is connected between the drain and source of the MOSFET chip.

3. The MOSFET power module according to claim 2, characterized in that, The MOSFET chip is a silicon carbide MOSFET chip.

4. The MOSFET power module according to claim 2, characterized in that, The piezoelectric buffer absorption circuit is located on the metal layer where the drain of the MOSFET chip is located.

5. The MOSFET power module according to claim 2, characterized in that, The bondable resistor on the piezoelectric buffer absorption circuit is connected to the metal layer to which the source of the MOSFET chip is connected via a bonding wire.

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