Display module and display panel

Abstract

The application provides a display module and a display panel, wherein the display module integrates and encapsulates a pixel driving module and a light emitting element to form the display module, and the display module has a lower process cost compared with a structure of a silicon-based micro chip, so that the cost of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display module and a display panel. Background Technology

[0002] Currently, most mainstream mini-LED backlight products, mini-LED direct-view products, and micro-LED direct-view products employ active driving. One type is an active driving structure based on a glass or flexible backplane: This structure utilizes low-temperature polycrystalline silicon or indium gallium zinc oxide thin-film transistor (IGaZN) backplane technology. After the array fabrication process is completed, the metal anode and cathode driving the LEDs in the pixel circuit are exposed on the backplane surface. Then, through a bonding process, the P and N electrodes of the mini-LED are electrically connected to the metal anode and cathode of the LED in the pixel circuit on the substrate, respectively. Alternatively, through mass transfer and metal bonding or other bonding processes, the P and N electrodes of the micro-LED are electrically connected to the metal anode and cathode of the LED in the pixel circuit on the substrate, respectively. Ultimately, this allows mini-LEDs or micro-LEDs to be actively driven via the backplane circuit.

[0003] In mini-LED direct-view products with larger pixel pitch, the active driving structure is generally based on a silicon-based microchip: that is, a silicon-based microchip is used to replace the original pixel driving module to drive one or more LEDs. The LEDs are bonded to the active driving trace substrate by a bonding method to realize the electrical connection between the LED and the driving circuit of the silicon-based microchip and form an array structure.

[0004] Currently, due to the high cost of silicon-based microchips and the limited wafer size, the number of chips that can be fabricated from a single wafer is limited, which leads to a high cost for high-resolution display panels. Summary of the Invention

[0005] This application provides a display module and a display panel to solve the problem of high cost of display panels.

[0006] This application provides a display module, comprising: a substrate, a pixel driving module, a light-emitting element, an encapsulation film layer, a scan signal terminal, a data signal terminal, a first-level terminal, and a second-level terminal. The pixel driving module is disposed on one side of the substrate; the light-emitting element is disposed on the side of the pixel driving module away from the substrate, and the pixel driving module is electrically connected to the light-emitting element; the encapsulation film layer is disposed on the side of the light-emitting element away from the substrate; the scan signal terminal is disposed on the side of the substrate away from the encapsulation film layer, and the scan signal terminal is electrically connected to the pixel driving module through an opening in the substrate; the data signal terminal is disposed on the side of the substrate away from the encapsulation film layer, and the data signal terminal is electrically connected to the pixel driving module through an opening in the substrate; the first-level terminal is disposed on the side of the substrate away from the encapsulation film layer, and the first-level terminal is electrically connected to the light-emitting element or the pixel driving module through an opening in the substrate; the second-level terminal is disposed on the side of the substrate away from the encapsulation film layer, and the second-level terminal is electrically connected to the pixel driving module or the light-emitting element through an opening in the substrate.

[0007] Optionally, in some embodiments of this application, the display module further includes: a sensor and a signal reading terminal, wherein the sensor is disposed between the substrate and the encapsulation film layer; the signal reading terminal is disposed on the side of the substrate away from the encapsulation film layer, the signal reading terminal is electrically connected to the sensor through an opening on the substrate, and the scan signal terminal is electrically connected to the sensor through an opening on the substrate.

[0008] Optionally, in some embodiments of this application, the pixel driving module includes: a first transistor and a second transistor, wherein the source, drain, and light-emitting element of the first transistor are connected in series between the first level terminal and the second level terminal; the gate of the second transistor is electrically connected to the scan signal terminal, the source of the second transistor is electrically connected to the data signal terminal, and the drain of the second transistor is electrically connected to the gate of the first transistor.

[0009] Optionally, in some embodiments of this application, the source of the first transistor is electrically connected to the first level terminal, the drain of the first transistor is electrically connected to the second electrode of the light-emitting element, and the first electrode of the light-emitting element is electrically connected to the second level terminal.

[0010] Optionally, in some embodiments of this application, the source of the first transistor is electrically connected to the first electrode of the light-emitting element, the drain of the first transistor is electrically connected to the second level terminal, and the second electrode of the light-emitting element is electrically connected to the first level terminal.

[0011] Optionally, in some embodiments of this application, the pixel driving module further includes: a holding capacitor, wherein the first plate of the holding capacitor is electrically connected to the gate of the first transistor, and the second plate of the holding capacitor is electrically connected to the first level terminal.

[0012] Optionally, in some embodiments of this application, the sensor includes: a common electrode, a photodiode, and a third transistor, wherein the first electrode of the photodiode is electrically connected to the common electrode; the drain of the third transistor is electrically connected to the second electrode of the photodiode; the source of the third transistor is electrically connected to the signal readout terminal; and the gate of the third transistor is electrically connected to the scan signal terminal.

[0013] Optionally, in some embodiments of this application, the display module further includes: an active layer disposed between the substrate and the encapsulation film layer, the active layer including the semiconductor portion of the first transistor, the semiconductor portion of the second transistor, the semiconductor portion of the photodiode, and the semiconductor portion of the third transistor.

[0014] Optionally, in some embodiments of this application, the display module further includes: a first electrode layer disposed between the substrate and the encapsulation film layer, the first electrode layer including the gate of the first transistor, the gate of the second transistor and the gate of the third transistor.

[0015] Optionally, in some embodiments of this application, the first electrode layer further includes a first wiring electrode, the first end of which is electrically connected to the gate of the first transistor and the gate of the third transistor, respectively, and the second end of which is electrically connected to the scan signal terminal through an opening on the substrate.

[0016] Optionally, in some embodiments of this application, the display module further includes: a second electrode layer, the second electrode layer being disposed between the substrate and the encapsulation film layer, the second electrode layer including the source and drain of the first transistor, the source and drain of the second transistor, and the source and drain of the third transistor.

[0017] Optionally, in some embodiments of this application, the second electrode layer further includes a second wiring electrode, the first end of which is electrically connected to the source of the first transistor, and the second end of which is electrically connected to the first level terminal through an opening on the substrate.

[0018] Optionally, in some embodiments of this application, the second electrode layer further includes a third wiring electrode, the first end of which is electrically connected to the source of the second transistor, and the second end of which is electrically connected to the data signal terminal through an opening on the substrate.

[0019] Optionally, in some embodiments of this application, the second electrode layer further includes a fourth wiring electrode, the first end of which is electrically connected to the drain of the third transistor, and the second end of which is electrically connected to the signal readout terminal through an opening on the substrate.

[0020] On the other hand, this application also provides a display panel, which includes: a display module as described above and a substrate, wherein the display module is arrayed on the substrate, and the substrate is provided with scan lines, data lines, a first level signal line, a second level signal line and a signal reading line; the scan lines are electrically connected to the scan signal terminal, the data lines are electrically connected to the data signal terminal, the first level signal line is electrically connected to the first level terminal, the second level signal line is electrically connected to the second level terminal, and the signal reading line is electrically connected to the signal reading terminal.

[0021] This application provides a display module and a display panel. The display module includes: a substrate, a pixel driving module, a light-emitting element, an encapsulation film layer, a scan signal terminal, a data signal terminal, a first-level terminal, and a second-level terminal. The pixel driving module is disposed on one side of the substrate; the light-emitting element is disposed on the side of the pixel driving module away from the substrate, and the pixel driving module is electrically connected to the light-emitting element; the encapsulation film layer is disposed on the side of the light-emitting element away from the substrate; the scan signal terminal is disposed on the side of the substrate away from the encapsulation film layer, and the scan signal terminal is electrically connected to the pixel driving module through an opening in the substrate; the data signal terminal is disposed on the side of the substrate away from the encapsulation film layer, and the data signal terminal is electrically connected to the pixel driving module through an opening in the substrate; the first-level terminal is disposed on the side of the substrate away from the encapsulation film layer, and the first-level terminal is electrically connected to the light-emitting element or the pixel driving module through an opening in the substrate; the second-level terminal is disposed on the side of the substrate away from the encapsulation film layer, and the second-level terminal is electrically connected to the pixel driving module or the light-emitting element through an opening in the substrate. This application integrates a pixel driving module and a light-emitting element into a package to form a display module. Compared with the structure of silicon-based microchips, the display module of this application has a lower manufacturing cost, thereby reducing the cost of the display panel. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the display module provided in this application;

[0024] Figure 2 for Figure 1 Sectional view of AA;

[0025] Figure 3 This is a schematic diagram illustrating the manufacturing process of the display module of this application;

[0026] Figure 4 This is a circuit connection diagram of the first embodiment of the display module of this application;

[0027] Figure 5 A schematic diagram of the specific structure of the first embodiment of the display module of this application;

[0028] Figure 6 This is a first structural schematic diagram of the display panel of this application;

[0029] Figure 7 This is a schematic diagram of the second structure of the display panel of this application;

[0030] Figure 8 This is a circuit connection diagram of a second embodiment of the display module of this application;

[0031] Figure 9 This is a schematic diagram illustrating the specific structure of the second embodiment of the display module of this application;

[0032] Figure 10 This is a schematic diagram of a third embodiment of the display module of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second," etc., may explicitly or implicitly include one or more features, and thus should not be construed as limiting this application.

[0035] The transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source and the other the drain. According to the configuration shown in the accompanying drawings, the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the output terminal is the drain. Furthermore, the transistors used in the embodiments of this application can include both P-type and N-type transistors. The P-type transistor conducts when the gate is low and is cut off when the gate is high, while the N-type transistor conducts when the gate is high and is cut off when the gate is low. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the output terminal is the drain.

[0036] This application provides a display module and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application.

[0037] It should be noted that since the source and drain of the transistor used in this application are symmetrical, their source and drain are interchangeable.

[0038] The transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source and the other the drain. According to the configuration shown in the accompanying drawings, the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the output terminal is the drain. Furthermore, the transistors used in the embodiments of this application can include both P-type and N-type transistors. The P-type transistor conducts when the gate is low and is cut off when the gate is high, while the N-type transistor conducts when the gate is high and is cut off when the gate is low. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the output terminal is the drain.

[0039] This application provides a display module and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application.

[0040] It should be noted that since the source and drain of the transistor used in this application are symmetrical, their source and drain are interchangeable.

[0041] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the display module 100 provided in this application. Figure 2 for Figure 1 Cross-sectional view (AA). This application provides a display module 100, which includes: an encapsulation film layer 10, a substrate 20, a pixel driving module 30, a light-emitting element 40, a scan signal terminal 101, a data signal terminal 102, a first level terminal 103, and a second level terminal 104;

[0042] A pixel driving module 30 is disposed on one side of the substrate 20; a light-emitting element 40 is disposed on the side of the pixel driving module 30 away from the substrate 20, and the pixel driving module 30 is electrically connected to the light-emitting element 40; an encapsulation film layer 10 is disposed on the side of the light-emitting element 40 away from the substrate 20; a scan signal terminal 101 is disposed on the side of the substrate 20 away from the encapsulation film layer 10, and the scan signal terminal 101 is electrically connected to the pixel driving module 30 through an opening in the substrate 20; a data signal terminal 102 is disposed on the side of the substrate 20 away from the encapsulation film layer 10. On one side, the data signal terminal 102 is electrically connected to the pixel driving module 30 through an opening on the substrate 20; the first level terminal 103 is located on the side of the substrate 20 away from the encapsulation film layer 10, and the first level terminal 103 is electrically connected to the light-emitting element 40 or the pixel driving module 30 through an opening on the substrate 20; the second level terminal 104 is located on the side of the substrate 20 away from the encapsulation film layer 10, and the second level terminal 104 is electrically connected to the pixel driving module 30 or the light-emitting element 40 through an opening on the substrate 20.

[0043] This application integrates the pixel driving module 30 and the light-emitting element 40 into a display module 100. Compared with the structure of silicon-based microchips, the display module 100 of this application has a lower manufacturing cost, thereby reducing the cost of the display panel.

[0044] Furthermore, the display module 100 also includes:

[0045] Sensor 50 is disposed between substrate 20 and encapsulation film layer 10;

[0046] The signal reading terminal 105 is located on the side of the substrate 20 away from the encapsulation film layer 10. The signal reading terminal 105 is electrically connected to the sensor 50 through an opening in the substrate 20. The scan signal terminal 101 is also electrically connected to the sensor 50 through an opening in the substrate 20. In some embodiments, the sensor 50 is a fingerprint sensor.

[0047] Specifically, sensor 50 is used to acquire touch signals and transmits the touch signals to signal reading terminal 105 under the control of scan signal terminal 101. This application, by simultaneously packaging pixel driving module 30, light-emitting element 40 and sensor 50 together, and by using the same scan signal terminal 101 for wiring, helps to further reduce the cost of display panel.

[0048] Furthermore, in some embodiments, the orthographic projection of the light-emitting element 40 onto the substrate 20 is located within the range of the orthographic projection of the pixel driving module 30 onto the substrate 20. The orthographic projection of the light-emitting element 40 onto the substrate 20 does not overlap with the orthographic projection of the sensor 50 onto the substrate 20.

[0049] Specifically, the encapsulation film layer 10 is an encapsulation shell with an opening; the substrate 20 is sealed at the opening of the encapsulation film layer 10; the pixel driving module 30 is disposed on the substrate 20 and located inside the encapsulation film layer 10; the light-emitting element 40 is disposed on the side of the pixel driving module 30 away from the substrate 20 and located inside the encapsulation film layer 10, and the pixel driving module 30 is electrically connected to the light-emitting element 40; the scan signal terminal 101 is disposed on the side of the substrate 20 away from the encapsulation film layer 10, and the scan signal terminal 101 is electrically connected to the pixel driving module through an opening on the substrate 20; the data signal terminal... 102 is located on the side of the substrate 20 away from the encapsulation film layer 10, and the data signal terminal 102 is electrically connected to the pixel driving module 30 through an opening on the substrate 20; the first level terminal 103 is located on the side of the substrate 20 away from the encapsulation film layer 10, and the first level terminal 103 is electrically connected to the light-emitting element 40 or the pixel driving module 30 through an opening on the substrate 20; the second level terminal 104 is located on the side of the substrate 20 away from the encapsulation film layer 10, and the second level terminal 104 is electrically connected to the pixel driving module 30 or the light-emitting element 40 through an opening on the substrate 20.

[0050] The scanning signal terminal 101, data signal terminal 102, first level terminal 103, and second level terminal 104 are respectively located on the side of the substrate 20 away from the encapsulation film layer 10. The scanning signal terminal 101 is used to electrically connect to the scanning signal line, the data signal terminal 102 is used to electrically connect to the data signal line, the first level terminal 103 is used to connect to a high level or a low level, and the second level terminal 104 is used to connect to a low level or a high level. Under the control of the scanning signal terminal 101, data signal terminal 102, first level terminal 103, and second level terminal 104, the pixel driving module 30 drives the light-emitting element 40 to emit light, and the light from the light-emitting element 40 is emitted through the encapsulation film layer 10.

[0051] In some embodiments, the display module 100 includes a pixel driving module 30 and a light-emitting element 40. In other embodiments of this application, the display module 100 may include a plurality of pixel driving modules 30 and a plurality of light-emitting elements 40.

[0052] Please refer to Figures 1 to 3 , Figure 3 This is a schematic diagram illustrating the manufacturing process of the display module 100 of this application. Furthermore, the specific manufacturing method of the display module 100 of this application is as follows:

[0053] On one side of the substrate 20, a pixel driving module 30 is fabricated to form a plurality of display modules 100, with each display module 100 being a unit. The plurality of display modules 100 form an array of display modules 100, and a cutting gap is left between adjacent display modules 100. A light-emitting element 40 is correspondingly formed on each pixel driving module 30. A scan signal terminal 101, a data signal terminal 102, a first level terminal 103, and a second level terminal 104 are formed on the side of the substrate 20 away from the pixel driving module 30. Holes are drilled by laser and filled with metal. The process, or a process of etching deep holes and then filling them with metal, electrically connects the pixel driving module 30 and the light-emitting element 40 to the scan signal terminal 101, the data signal terminal 102, the first level terminal 103, and the second level terminal 104; forming an encapsulation film layer 10, which covers the pixel driving module 30 and the light-emitting element 40 of the display module 100, and the encapsulation film layer 10 is sealed to the substrate 20. Specifically, the encapsulation film layer 10 is formed using transparent adhesive; the display module 100 array is cut to obtain multiple display modules 100.

[0054] Furthermore, in some embodiments, the display module 100 further includes:

[0055] Sensor 50 is disposed on substrate 20 and located within encapsulation film layer 10;

[0056] The signal reading terminal 105 is located on the side of the substrate 20 away from the encapsulation film layer 10. The signal reading terminal 105 is electrically connected to the sensor 50 through an opening on the substrate 20. The scan signal terminal 101 is electrically connected to the sensor 50 through an opening on the substrate 20.

[0057] Please refer to Figure 1 , Figure 2 and Figure 4 , Figure 4 This is a circuit connection diagram of the first embodiment of the display module 100 of this application. Specifically, the pixel driving module 30 includes:

[0058] The first transistor T1, the source, drain and light-emitting element 40 of the first transistor T1 are connected in series between the first level terminal 103 and the second level terminal 104;

[0059] The second transistor T2 has its gate electrically connected to the scan signal terminal 101, its source electrically connected to the data signal terminal 102, and its drain electrically connected to the gate of the first transistor T1.

[0060] That is, when the signal at the scan signal terminal 101 turns on the second transistor T2, the signal at the data signal terminal 102 is transmitted to the gate of the first transistor T1 through the second transistor T2, and turns on the first transistor T1. The turning on of the first transistor T1 turns on the circuit connected in series between the first level terminal 103 and the second level terminal 104, thereby causing the light-emitting element 40 to emit light.

[0061] Furthermore, in some embodiments of this application, the source of the first transistor T1 is electrically connected to the first level terminal 103, the drain of the first transistor T1 is electrically connected to the second electrode 42 of the light-emitting element 40, and the first electrode 41 of the light-emitting element 40 is electrically connected to the second level terminal 104.

[0062] In some embodiments, the pixel driving module 30 further includes:

[0063] Hold capacitor C, keep the first plate of capacitor C electrically connected to the gate of the first transistor T1, and keep the second plate of capacitor C electrically connected to the first level terminal 103.

[0064] In some embodiments, sensor 50 includes:

[0065] Common electrode 58;

[0066] Photodiode L, the first electrode of photodiode L is electrically connected to the common electrode 58;

[0067] The third transistor T3 has its drain electrically connected to the second electrode of the photodiode L, its source electrically connected to the signal readout terminal 105, and its gate electrically connected to the scan signal terminal 101. The first electrode of the photodiode L is the anode, and the second electrode is the cathode.

[0068] When a finger is pressed on the position corresponding to sensor 50, the incident light from the light source shines on the finger. Different areas of the fingerprint produce different reflected light. The different reflected light reaches photodiode L and generates leakage current of different magnitudes. The third transistor T3 is turned on under the signal control of scanning signal terminal 101 to read the leakage current of photodiode L. Then, fingerprint imaging is performed according to the different currents corresponding to different areas read.

[0069] Please refer to Figure 1 , Figure 2 , Figure 4 and Figure 5 , Figure 5 The first embodiment of the display module 100 of this application is shown in the schematic diagram. In some embodiments, the display module 100 further includes:

[0070] The active layer 201 is disposed between the substrate 20 and the encapsulation film layer 10. The active layer 201 includes the semiconductor part of the first transistor T1, the semiconductor part of the second transistor T2, the semiconductor part of the photodiode L, and the semiconductor part of the third transistor T3.

[0071] In other words, in this application, the semiconductor portions of the first transistor, the second transistor, the photodiode, and the third transistor are disposed on the same active layer, which helps to reduce the number of active layers, thereby reducing cost and thickness.

[0072] In some embodiments, the display module 100 further includes:

[0073] The first electrode layer 203 is disposed between the substrate 20 and the encapsulation film layer 10. The first electrode layer 203 includes the gate of the first transistor T1, the gate of the second transistor T2, and the gate of the third transistor T3.

[0074] In other words, in this application, the gates of the first transistor, the second transistor, and the third transistor are disposed on the same electrode layer, which helps to reduce the number of metal layers, thereby reducing cost and thickness.

[0075] Furthermore, the first electrode layer 203 also includes a first wiring electrode 310. The first end of the first wiring electrode 310 is electrically connected to the gate of the first transistor T1 and the gate of the third transistor T3, respectively. The second end of the first wiring electrode 310 is electrically connected to the scan signal terminal 101 through an opening on the substrate 20. In this application, the scan signal terminal, by electrically connecting the first wiring electrode to the gate of the first transistor and the gate of the third transistor, and by having the first wiring electrode and the gates of the first and third transistors disposed on the same layer, helps to reduce the number of metal layers, thereby reducing cost and thickness.

[0076] In some embodiments, the display module 100 further includes:

[0077] The second electrode layer 205 is disposed between the substrate 20 and the encapsulation film layer 10. The second electrode layer 205 includes the source and drain of the first transistor T1, the source and drain of the second transistor T2, and the source and drain of the third transistor T3.

[0078] In other words, in this application, the source and drain of the first transistor, the source and drain of the second transistor, and the source and drain of the third transistor are disposed on the same electrode layer, which helps to reduce the number of metal layers, thereby reducing cost and thickness.

[0079] Furthermore, the second electrode layer 205 also includes a second wiring electrode 320. The first end of the second wiring electrode 320 is electrically connected to the source of the first transistor T1, and the second end of the second wiring electrode 320 is electrically connected to the first level terminal 103 through an opening on the substrate 20. The second wiring electrode and the source of the first transistor are disposed on the same layer, which can reduce the number of metal layers.

[0080] In some embodiments, the second electrode layer 205 further includes a third wiring electrode 330. The first end of the third wiring electrode 330 is electrically connected to the source of the second transistor T2, and the second end of the third wiring electrode 330 is electrically connected to the data signal terminal 102 through an opening on the substrate 20. The third wiring electrode and the source of the second transistor are disposed on the same layer, which can reduce the number of metal layers.

[0081] In some embodiments, the second electrode layer 205 further includes a fourth wiring electrode 340. The first end of the fourth wiring electrode 340 is electrically connected to the drain of the third transistor T3, and the second end of the fourth wiring electrode 340 is electrically connected to the signal readout terminal 105 through an opening on the substrate 20. The fourth wiring electrode and the source of the third transistor are disposed on the same layer, which can reduce the number of metal layers.

[0082] Specifically, the display module 100 also includes:

[0083] An active layer 201 is disposed on a substrate 20, and the active layer 201 includes a first semiconductor portion 31 and a second semiconductor portion 35.

[0084] The first insulating layer 202 is disposed on the active layer 201;

[0085] The first electrode layer 203 is disposed on the first insulating layer 202. The first electrode layer 203 includes a first gate 32 and a second gate 36. The orthographic projection of the first gate 32 on the substrate 20 overlaps with the orthographic projection of the first semiconductor portion 31 on the substrate 20. The orthographic projection of the second gate 36 on the substrate 20 overlaps with the orthographic projection of the second semiconductor portion 35 on the substrate 20. The second gate 36 is electrically connected to the scan signal terminal 101.

[0086] The second insulating layer 204 is disposed on the first electrode layer 203;

[0087] The second electrode layer 205 is disposed on the second insulating layer 204. The second electrode layer 205 includes a first drain 34, a second drain 38, a first source 33, and a second source 37. The first drain 34 and the first source 33 are electrically connected to the first semiconductor section 31 through openings on the first insulating layer 202 and the second insulating layer 204, respectively. The second drain 38 and the second source 37 are electrically connected to the second semiconductor section 35 through openings on the first insulating layer 202 and the second insulating layer 204, respectively. The second drain 38 is electrically connected to the first gate 32. The second source 37 is electrically connected to the data signal terminal 102. The first source 33 is electrically connected to the first level terminal 103.

[0088] A first planarization layer 206 is disposed on a second electrode layer 205;

[0089] The light-emitting unit 40 is disposed on the first planarization layer 206. The first drain 34 is electrically connected to the first electrode 41 of the light-emitting element 40 through an opening in the first planarization layer 206. The second electrode 42 of the light-emitting unit 40 is electrically connected to the second level terminal 104. The first electrode is one of the anode and the cathode, and the second electrode is the other of the anode and the cathode.

[0090] The first semiconductor section 31, the first gate 32, the first drain 34 and the first source 33 form the first transistor T1, and the second semiconductor section 35, the second gate 36, the second drain 38 and the second source 37 form the second transistor T2.

[0091] Furthermore, in some embodiments, the active layer 201 further includes a third semiconductor section 51, a fourth semiconductor section 55, a fifth semiconductor section 57 and an intrinsic semiconductor section 56, wherein the fourth semiconductor section 55, the intrinsic semiconductor section 56 and the fifth semiconductor section 57 are connected in sequence.

[0092] The first electrode layer 203 also includes a third gate 52, the orthographic projection of the third gate 52 on the substrate 20 and the orthographic projection of the third semiconductor portion 51 on the substrate 20 overlap, and the third gate 52 is electrically connected to the scan signal terminal 101.

[0093] The second electrode layer 205 also includes a third drain 54 and a third source 53. The third drain 54 and the third source 53 are electrically connected to the third semiconductor section 51 through openings on the first insulating layer 202 and the second insulating layer 204, respectively. The third drain 54 is electrically connected to the fifth semiconductor section 57, and the third source 53 is electrically connected to the signal reading terminal 105.

[0094] The display module 100 also includes:

[0095] The third electrode layer 207 is disposed on the first planarization layer 206. The third electrode layer 207 includes a common electrode 58. The common electrode 58 is electrically connected to the fourth semiconductor section 55 through openings in the first insulating layer 202, the second insulating layer 204 and the first planarization layer 206.

[0096] The second planarization layer 208 is disposed on the third electrode layer 207, and the light-emitting unit 40 is disposed on the second planarization layer 208. Furthermore, the fourth semiconductor section 55 is a P-type semiconductor, and the fifth semiconductor section 57 is an N-type semiconductor.

[0097] In this configuration, the fourth semiconductor section 55, the intrinsic semiconductor section 56, and the fifth semiconductor section 57 are sequentially connected to form a photodiode L, and the third semiconductor section 51, the third gate 52, the third drain 54, and the third source 53 form a third transistor T3.

[0098] Further, the substrate 20 includes a first buffer layer 21, a third insulating layer 22, a first barrier layer 23, a fourth insulating layer 24, a second barrier layer 25, and a second buffer layer 26 stacked sequentially. An active layer 201 is disposed on the side of the second buffer layer 26 away from the first buffer layer 21. Further, the display module 100 also includes a sixth electrode layer 302, disposed on the side of the second buffer layer 26 away from the first buffer layer 21. The active layer 201 is disposed on the sixth electrode layer 302. The sixth electrode layer 302 includes a light-shielding electrode 510, and the orthographic projection of the electrode of the sixth electrode layer 302 onto the substrate 20 overlaps with the orthographic projection of the intrinsic semiconductor portion 56 onto the substrate 20. By blocking the light incident on the intrinsic semiconductor portion 56 through the light-shielding electrode 510, the operating accuracy of the photodiode L is improved.

[0099] Furthermore, the orthographic projection of one end of the first source electrode 33 on the substrate 20 does not overlap with the orthographic projection of the first semiconductor part 31 on the substrate 20, and one end of the first source electrode 33 is electrically connected to the first level terminal 103 through the first insulating layer 202, the second insulating layer 204 and the opening on the substrate 20.

[0100] The orthographic projection of one end of the second source electrode 37 on the substrate 20 does not overlap with the orthographic projection of the second semiconductor part 35 on the substrate 20. One end of the second source electrode 37 is electrically connected to the data signal terminal 102 through the first insulating layer 202, the second insulating layer 204 and the opening on the substrate 20.

[0101] In some embodiments, the second electrode layer 205 further includes a fifth wiring electrode 350, the orthographic projection of the fifth wiring electrode 350 on the substrate 20 and the orthographic projection of the first wiring electrode 310 on the substrate 20 overlap, and the fifth wiring electrode 350 and the first wiring electrode 310 form a holding capacitor C.

[0102] In some embodiments, the second electrode layer 205 further includes:

[0103] The first connecting electrode 59 is electrically connected to the fifth semiconductor part 57 through openings in the first insulating layer 202 and the second insulating layer 204, and is electrically connected to the third drain electrode 54.

[0104] In some embodiments, the third electrode layer 207 further includes:

[0105] The second connection electrode 39 is electrically connected to the first gate electrode 32 through openings in the second insulating layer 204 and the first planarization layer 206, and is also electrically connected to the second drain electrode 38 through openings in the first planarization layer 206. The orthographic projection of the second connection electrode 39 onto the substrate 20 overlaps with the orthographic projections of the second drain electrode 38 and the first gate electrode 32 onto the substrate 20.

[0106] In some embodiments, the orthographic projection of one end of the third source electrode 53 on the substrate 20 does not overlap with the orthographic projection of the third semiconductor portion 51 on the substrate 20, and one end of the third source electrode 53 is electrically connected to the signal reading terminal 105 through the first insulating layer 202, the second insulating layer 204 and the opening on the substrate 20.

[0107] In some embodiments, the light-emitting unit 40 includes a light-emitting diode;

[0108] The display module 100 also includes:

[0109] The fourth electrode layer 209 is disposed on the second planarization layer 208. The fourth electrode layer 209 includes the anode and cathode of the light-emitting diode; that is, the first electrode 41 of the light-emitting element 40 is the anode and the second electrode 42 of the light-emitting element 40 is the cathode.

[0110] A pixel definition layer 301 is provided on the fourth electrode layer 209. The pixel definition layer 301 has a pixel opening. The light-emitting diode chip 43 of the light-emitting diode is provided in the pixel opening. The anode and cathode are electrically connected to the light-emitting diode chip 43 of the light-emitting diode, respectively.

[0111] The first drain 34 is electrically connected to the anode of the light-emitting diode through openings on the first planarization layer 206 and the second planarization layer 208, and the cathode of the light-emitting diode is electrically connected to the second level terminal 104 through openings on the first insulating layer 202, the second insulating layer 204, the first planarization layer 206 and the second planarization layer 208.

[0112] The display module 100 also includes:

[0113] The third planarization layer 303 is disposed on the fourth electrode layer 209. The pixel definition layer 301 is disposed on the third planarization layer 303. The pixel definition layer 301 has a pixel opening. The light-emitting diode chip 43 of the light-emitting diode is disposed in the pixel opening. The third planarization layer has an opening that exposes the first electrode 41 and the second electrode 42 of the light-emitting element 40. The light-emitting diode chip 43 of the light-emitting diode is electrically connected to the first electrode 41 and the second electrode 42 of the light-emitting element 40 through the opening on the third planarization layer, respectively. The encapsulation film layer 10 is disposed on the side of the pixel definition layer 301 away from the substrate.

[0114] Please refer to Figure 6 and Figure 7 , Figure 6 This is a first structural schematic diagram of the display panel of this application. Figure 7 This is a second structural schematic diagram of the display panel of this application. Correspondingly, embodiments of this application also provide a display panel 200, which includes the display module 100 as described above;

[0115] The substrate 210 has an array of display modules 100 on it, and the substrate 210 has scan lines 220, data lines 230, first level signal lines, second level signal lines and signal reading lines.

[0116] Scan line 220 is electrically connected to scan signal terminal 101, data line 230 is electrically connected to data signal terminal 102, first level signal line is electrically connected to first level terminal 103, second level signal line is electrically connected to second level terminal 104, and signal reading line is electrically connected to signal reading terminal 105.

[0117] Compared with the prior art, the beneficial effects of the array substrate provided in this application embodiment are the same as the beneficial effects of the display module 100 provided in the above technical solution, and will not be repeated here.

[0118] After completing the display module 100, a display panel with an array of display modules 100 is then fabricated. If the gate driving circuit is not located on the display panel, scan lines 220, data lines 230, first-level signal lines, second-level signal lines, and signal readout lines are first fabricated on the substrate. The signal traces can be fabricated using exposure, development, and etching processes common in the panel industry, or thick metal fabrication processes such as electroplating / chemical plating or printing can be used to form thick metal lines on the substrate surface. If the gate driving circuit is located on the display panel, the gate driving circuit and signal traces also need to be fabricated on the substrate. After the gate driving circuit and signal traces are fabricated, the fabricated display modules are then installed in their corresponding positions using soldering or bonding processes to form an array structure of display modules. Subsequently, the pads on the flexible circuit board / crystal film are made conductive with the pads on the display panel using metal soldering or bonding processes, connecting the signals corresponding to the external system circuits to the signal traces on the display panel. Finally, a thick layer of transparent silicone can be coated on the substrate to fill the gap between the substrate and the display modules, thus completing the fabrication of the entire display panel.

[0119] Correspondingly, embodiments of this application also provide a display device, which includes the display panel described above. Please refer to... Figure 6 In some embodiments, the display device further includes an emissive controller, a column driver, and a GOA unit. The emissive controller is electrically connected to the column driver and the GOA unit respectively. GOA units are provided on both sides of the display panel. The GOA units are electrically connected to the scan line 220, and the column driver is electrically connected to the data line 230.

[0120] Please refer to Figure 7 In other embodiments of this application, the display device further includes a light-emitting controller, a column driver, and a row driver. The light-emitting controller is electrically connected to the column driver and the row driver, respectively. The row driver is electrically connected to the scan line 220, and the column driver is electrically connected to the data line 230.

[0121] Compared with the prior art, the beneficial effects of the display device provided in this application embodiment are the same as the beneficial effects of the display module 100 provided in the above technical solution, and will not be repeated here.

[0122] Please refer to Figure 8 and Figure 9 , Figure 8 This is a circuit connection diagram of a second embodiment of the display module of this application. Figure 9 This is a schematic diagram illustrating the specific structure of a second embodiment of the display module of this application. This embodiment is similar to... Figure 5The provided embodiment differs in that the source of the first transistor T1 is electrically connected to the first electrode 41 of the light-emitting element 40, the drain of the first transistor T1 is electrically connected to the second level terminal 104, and the second electrode 42 of the light-emitting element 40 is electrically connected to the first level terminal 103.

[0123] Furthermore, the second electrode layer 205 also includes a second wiring electrode 320. The first end of the second wiring electrode 320 is electrically connected to the drain of the first transistor T1, and the second end of the second wiring electrode 320 is electrically connected to the second level terminal 104 through an opening on the substrate 20. The second wiring electrode is disposed on the same layer as the source of the first transistor, which can reduce the number of metal layers.

[0124] In some embodiments, the pixel driving module 30 further includes:

[0125] Hold capacitor C, keep the first plate of capacitor C electrically connected to the gate of the first transistor T1, and keep the second plate of capacitor C electrically connected to the second level terminal 104.

[0126] The display module 100 also includes:

[0127] An active layer 201 is disposed on a substrate 20, and the active layer 201 includes a first semiconductor portion 31 and a second semiconductor portion 35.

[0128] The first insulating layer 202 is disposed on the active layer 201;

[0129] The first electrode layer 203 is disposed on the first insulating layer 202. The first electrode layer 203 includes a first gate 32 and a second gate 36. The orthographic projection of the first gate 32 on the substrate 20 overlaps with the orthographic projection of the first semiconductor portion 31 on the substrate 20. The orthographic projection of the second gate 36 on the substrate 20 overlaps with the orthographic projection of the second semiconductor portion 35 on the substrate 20. The second gate 36 is electrically connected to the scan signal terminal 101.

[0130] The second insulating layer 204 is disposed on the first electrode layer 203;

[0131] The second electrode layer 205 is disposed on the second insulating layer 204. The second electrode layer 205 includes a first drain 34, a second drain 38, a first source 33, and a second source 37. The first drain 34 and the first source 33 are electrically connected to the first semiconductor section 31 through openings on the first insulating layer 202 and the second insulating layer 204, respectively. The second drain 38 and the second source 37 are electrically connected to the second semiconductor section 35 through openings on the first insulating layer 202 and the second insulating layer 204, respectively. The second drain 38 is electrically connected to the first gate 32. The second source 37 is electrically connected to the data signal terminal 102. The first drain 34 is electrically connected to the second level terminal 104.

[0132] A first planarization layer 206 is disposed on a second electrode layer 205;

[0133] The light-emitting unit 40 is disposed on the first planarization layer 206. The first source electrode 33 is electrically connected to the second electrode 42 of the light-emitting element 40 through an opening on the first planarization layer 206. The first electrode of the light-emitting unit 40 is electrically connected to the first level terminal 103.

[0134] Furthermore, in some embodiments, the active layer 201 further includes a third semiconductor section 51, a fourth semiconductor section 55, a fifth semiconductor section 57 and an intrinsic semiconductor section 56, wherein the fourth semiconductor section 55, the intrinsic semiconductor section 56 and the fifth semiconductor section 57 are connected in sequence.

[0135] The first electrode layer 203 also includes a third gate 52, the orthographic projection of the third gate 52 on the substrate 20 and the orthographic projection of the third semiconductor portion 51 on the substrate 20 overlap, and the third gate 52 is electrically connected to the scan signal terminal 101.

[0136] The second electrode layer 205 also includes a third drain 54 and a third source 53. The third drain 54 and the third source 53 are electrically connected to the third semiconductor section 51 through openings on the first insulating layer 202 and the second insulating layer 204, respectively. The third drain 54 is electrically connected to the fifth semiconductor section 57, and the third source 53 is electrically connected to the signal reading terminal 105.

[0137] The display module 100 also includes:

[0138] The third electrode layer 207 is disposed on the first planarization layer 206. The third electrode layer 207 includes a common electrode 58. The common electrode 58 is electrically connected to the fourth semiconductor section 55 through openings in the first insulating layer 202, the second insulating layer 204 and the first planarization layer 206.

[0139] The second planarization layer 208 is disposed on the third electrode layer 207, and the light-emitting unit 40 is disposed on the second planarization layer 208. Furthermore, the fourth semiconductor section 55 is a P-type semiconductor, and the fifth semiconductor section 57 is an N-type semiconductor.

[0140] In this configuration, the fourth semiconductor section 55, the intrinsic semiconductor section 56, and the fifth semiconductor section 57 are sequentially connected to form a photodiode L, and the third semiconductor section 51, the third gate 52, the third drain 54, and the third source 53 form a third transistor T3.

[0141] Furthermore, in some embodiments, the light-emitting unit 40 includes a light-emitting diode;

[0142] The display module 100 also includes:

[0143] The fourth electrode layer 209 is disposed on the second planarization layer 208. The fourth electrode layer 209 includes the anode and cathode of the light-emitting diode; that is, the first electrode 41 of the light-emitting element 40 is the anode and the second electrode 42 of the light-emitting element 40 is the cathode.

[0144] A pixel definition layer 301 is provided on the fourth electrode layer 209. The pixel definition layer 301 has a pixel opening. The light-emitting diode chip 43 of the light-emitting diode is provided in the pixel opening. The anode and cathode are electrically connected to the light-emitting diode chip 43 of the light-emitting diode, respectively.

[0145] The first source electrode 33 is electrically connected to the cathode of the light-emitting diode through openings on the first planarization layer 206 and the second planarization layer 208, and the anode of the light-emitting diode is electrically connected to the first level terminal 103 through openings on the first insulating layer 202, the second insulating layer 204, the first planarization layer 206 and the second planarization layer 208.

[0146] The display module 100 also includes:

[0147] The third planarization layer 303 is disposed on the fourth electrode layer 209. The pixel definition layer 301 is disposed on the third planarization layer 303. The pixel definition layer 301 has a pixel opening. The light-emitting diode chip 43 of the light-emitting diode is disposed in the pixel opening. The third planarization layer has an opening that exposes the first electrode 41 and the second electrode 42 of the light-emitting element 40. The light-emitting diode chip 43 of the light-emitting diode is electrically connected to the first electrode 41 and the second electrode 42 of the light-emitting element 40 through the opening on the third planarization layer, respectively. The encapsulation film layer 10 is disposed on the side of the pixel definition layer 301 away from the substrate.

[0148] Please refer to Figure 10 , Figure 10 This is a schematic diagram of a third embodiment of the display module of this application. This embodiment is related to... Figure 5 The difference in the provided embodiments is that the light-emitting unit 40 includes an organic light-emitting diode;

[0149] The display module 100 also includes:

[0150] The fourth electrode layer 209 is disposed on the second planarization layer 208 and includes the anode of the organic light-emitting diode; that is, the first electrode 41 of the light-emitting element 40 is the anode.

[0151] A pixel definition layer 301 is disposed on the fourth electrode layer 209. The pixel definition layer 301 has a pixel opening located above the anode. The light-emitting layer 43 of the organic light-emitting diode is disposed in the pixel opening and electrically connected to the anode.

[0152] The fifth electrode layer 302 is disposed on the pixel definition layer 301. The fifth electrode layer 302 includes the cathode of the organic light-emitting diode. The cathode is electrically connected to the light-emitting layer 43 through the pixel opening. The second electrode 42 of the light-emitting element 40 is the cathode.

[0153] The first drain 34 is electrically connected to the anode through openings on the first planarization layer 206 and the second planarization layer 208, and the second electrode is electrically connected to the second level terminal 104 through openings on the first insulating layer 202, the second insulating layer 204, the first planarization layer 206, the second planarization layer 208 and the pixel definition layer 301.

[0154] The third planarization layer 303 is disposed on the fifth electrode layer 302, and the encapsulation film layer 10 is disposed on the side of the third planarization layer 303 away from the substrate.

[0155] The above provides a detailed description of a display module and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, Includes a display module and a substrate; the display module includes: Substrate; A pixel driving module, wherein the pixel driving module is disposed on one side of the substrate; A light-emitting element is disposed on the side of the pixel driving module away from the substrate, and the pixel driving module is electrically connected to the light-emitting element; An encapsulation film layer is disposed on the side of the light-emitting element away from the substrate; the encapsulation film layer is an encapsulation housing with an opening, the substrate is sealed at the opening of the encapsulation film layer, and the pixel driving module and the light-emitting element are located inside the encapsulation housing; The scanning signal terminal is located on the side of the substrate away from the encapsulation film layer, and is electrically connected to the pixel driving module through an opening on the substrate. The data signal terminal is located on the side of the substrate away from the encapsulation film layer, and is electrically connected to the pixel driving module through an opening on the substrate. A first-level terminal is located on the side of the substrate away from the encapsulation film layer, and the first-level terminal is electrically connected to the light-emitting element or the pixel driving module through an opening on the substrate. The second level terminal is located on the side of the substrate away from the encapsulation film layer, and the second level terminal is electrically connected to the pixel driving module or the light-emitting element through an opening on the substrate. The display module is arrayed on the substrate, and the substrate is provided with scan lines, data lines, first level signal lines, second level signal lines and signal reading lines; The scan line is electrically connected to the scan signal terminal, the data line is electrically connected to the data signal terminal, the first level signal line is electrically connected to the first level terminal, the second level signal line is electrically connected to the second level terminal, and the signal reading line is electrically connected to the signal reading terminal.

2. The display panel according to claim 1, characterized in that, The display module further includes: The sensor is disposed between the substrate and the encapsulation film layer; The signal reading terminal is located on the side of the substrate away from the encapsulation film layer. The signal reading terminal is electrically connected to the sensor through an opening on the substrate. The scan signal terminal is also electrically connected to the sensor through an opening on the substrate.

3. The display panel according to claim 2, characterized in that, The pixel driving module includes: The first transistor, the source and drain of the first transistor and the light-emitting element are connected in series between the first level terminal and the second level terminal; The second transistor has its gate electrically connected to the scan signal terminal, its source electrically connected to the data signal terminal, and its drain electrically connected to the gate of the first transistor.

4. The display panel according to claim 3, characterized in that, The source of the first transistor is electrically connected to the first level terminal, the drain of the first transistor is electrically connected to the second electrode of the light-emitting element, and the first electrode of the light-emitting element is electrically connected to the second level terminal.

5. The display panel according to claim 3, characterized in that, The source of the first transistor is electrically connected to the first electrode of the light-emitting element, the drain of the first transistor is electrically connected to the second level terminal, and the second electrode of the light-emitting element is electrically connected to the first level terminal.

6. The display panel according to claim 4, characterized in that, The pixel driving module also includes: A holding capacitor is provided, wherein the first plate of the holding capacitor is electrically connected to the gate of the first transistor, and the second plate of the holding capacitor is electrically connected to the first level terminal.

7. The display panel according to claim 3, characterized in that, The sensor includes: Common electrode; A photodiode, wherein the first electrode of the photodiode is electrically connected to the common electrode; The third transistor has its drain electrically connected to the second electrode of the photodiode, its source electrically connected to the signal readout terminal, and its gate electrically connected to the scan signal terminal.

8. The display panel according to claim 7, characterized in that, The display module further includes: An active layer is disposed between the substrate and the encapsulation film layer, and the active layer includes a semiconductor portion of the first transistor, a semiconductor portion of the second transistor, a semiconductor portion of the photodiode, and a semiconductor portion of the third transistor.

9. The display panel according to claim 7, characterized in that, The display module further includes: A first electrode layer is disposed between the substrate and the encapsulation film layer, and the first electrode layer includes the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor.

10. The display panel according to claim 9, characterized in that, The first electrode layer further includes a first wiring electrode, the first end of which is electrically connected to the gate of the first transistor and the gate of the third transistor, respectively, and the second end of which is electrically connected to the scan signal terminal through an opening on the substrate.

11. The display panel according to claim 7, characterized in that, The display module further includes: The second electrode layer is disposed between the substrate and the encapsulation film layer, and the second electrode layer includes the source and drain of the first transistor, the source and drain of the second transistor, and the source and drain of the third transistor.

12. The display panel according to claim 11, characterized in that, The second electrode layer further includes a second wiring electrode, the first end of which is electrically connected to the source of the first transistor, and the second end of which is electrically connected to the first level terminal through an opening on the substrate.

13. The display panel according to claim 11, characterized in that, The second electrode layer further includes a third wiring electrode, the first end of which is electrically connected to the source of the second transistor, and the second end of which is electrically connected to the data signal terminal through an opening on the substrate.

14. The display panel according to claim 11, characterized in that, The second electrode layer further includes a fourth wiring electrode, the first end of which is electrically connected to the drain of the third transistor, and the second end of which is electrically connected to the signal readout terminal through an opening on the substrate.

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