Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate has a first area and a second area surrounding the first area at least partially. The array substrate comprises a substrate, a first metal layer, a first insulating layer and a first electrode layer. The first metal layer is located on one side of the substrate. The first metal layer comprises a first part located in the first area and a second part located in the second area. The first insulating layer is located on the side of the first metal layer away from the substrate. The first electrode layer is insulated from the first metal layer by the first insulating layer. The first electrode layer comprises a first sub-electrode located in the first area and a second sub-electrode located in the second area. The first sub-electrode and the second part maintain the same potential. In the embodiment of the application, the breakdown of the first insulating layer does not cause the transmission signal in the second sub-electrode and the second part to change, thereby improving the reliability of signal transmission and reducing the probability of display abnormalities.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the rapid development of the display industry, people have increasingly higher requirements for the bezel size and image quality of display products. At the same time, ensuring a high yield rate in the display panel manufacturing process has also brought great challenges to product performance and manufacturing processes.

[0003] During the manufacturing process, the inherent properties of the equipment used to produce display panels cannot be changed, and some properties of the equipment can easily have an adverse effect on the production of display panels, resulting in a decrease in product yield or problems with display quality. Summary of the Invention

[0004] This application provides an array substrate and a display panel that can improve display reliability.

[0005] This application provides an array substrate having a first region and a second region at least partially surrounding the first region. The array substrate includes a substrate, a first metal layer, a first insulating layer, and a first electrode layer. The first metal layer is located on one side of the substrate and includes a first portion located in the first region and a second portion located in the second region.

[0006] The first insulating layer is located on the side of the first metal layer facing away from the substrate. The first electrode layer is insulated from the first metal layer by the first insulating layer. The first electrode layer includes a first sub-electrode located in a first region and a second sub-electrode located in a second region. The first sub-electrode and the second sub-electrode maintain the same potential.

[0007] In some embodiments, the first sub-pole corresponds to a display pixel setting for driving light emission, and the second sub-pole corresponds to a virtual pixel setting.

[0008] In some embodiments, the array substrate further includes a second sub-electrode electrically connected to the first signal line;

[0009] The second part is connected to the first signal line or the second sub-pole.

[0010] In some embodiments, the first signal line is located within the second region, and at least a portion of the first signal line is located on the side of the second sub-pole opposite to the first sub-pole.

[0011] In some embodiments, a first through-hole is provided on the first insulating layer along the thickness direction of the substrate, and the second sub-electrode and the second portion are connected through the first through-hole.

[0012] In some embodiments, the number of first through holes is multiple.

[0013] In some embodiments, the array substrate further includes a second signal line and a first connection portion, wherein at least a portion of the second signal line is projected onto the substrate between the second portion and the first signal line.

[0014] One end of the first connector is connected to the first signal line, and the other end of the first connector is connected to the second part.

[0015] In some embodiments, the voltage of the first signal line is lower than the voltage of the second signal line.

[0016] In some embodiments, the second signal line and the first signal line are located in different film layers, and the first signal line, the second portion, and the first connecting portion are disposed in the same layer.

[0017] In some embodiments, at least one of the first signal line and the second portion is located in the same film layer as the second signal line;

[0018] The first connection portion is located on one side of the second signal line in the substrate thickness direction.

[0019] In some embodiments, the array substrate further includes a second metal layer disposed between the first metal layer and the substrate, and the first connection portion is located within the second metal layer.

[0020] In some embodiments, the first signal line is located within the second metal layer.

[0021] In some embodiments, the distance between the first signal line and the second portion is less than the distance between any other signal line and the second portion, and the second portion is connected to the first signal line.

[0022] In some embodiments, the array substrate further includes a third signal line, the first sub-electrode is connected to the third signal line, and the voltage of the third signal line is higher than the voltage of the first signal line.

[0023] In some embodiments, the distance between the second sub-pole and the first region is L, where L satisfies: L≥10μm.

[0024] Secondly, embodiments of this application provide a display panel, including the array substrate in any of the foregoing embodiments.

[0025] In some embodiments, the display panel further includes a second electrode layer disposed on the side of the first electrode layer away from the substrate, the second electrode layer including a third sub-electrode located in the first region, the first sub-electrode and the third sub-electrode being used to drive the display pixels to emit light;

[0026] The third sub-pole is connected to the second sub-pole.

[0027] Thirdly, embodiments of this application provide a display device, including the display panel in any of the foregoing embodiments.

[0028] This application provides an array substrate and a display panel. The array substrate sets the second sub-electrode and the second portion to maintain the same potential, meaning that the signal magnitude transmitted by both at different times is the same. In this case, even if the first insulating layer is broken down under electrostatic discharge, causing the second sub-electrode and the second portion to connect, because the second sub-electrode and the second portion have the same potential, the breakdown of the first insulating layer will not cause a change in the transmitted signal within the second sub-electrode and the second portion, and therefore will not affect the signal lines connected to the second sub-electrode or the signal lines connected to the second portion. This design can improve the reliability of signal transmission and reduce the probability of display abnormalities. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a top view schematic diagram of an array substrate provided in an embodiment of this application;

[0031] Figure 2 yes Figure 1 A magnified schematic diagram of the local structure of region Q in the middle region;

[0032] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at point AA;

[0033] Figure 4 This is an enlarged view of a partial structure in another array substrate provided in the embodiments of this application;

[0034] Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure at point BB;

[0035] Figure 6 This is a cross-sectional structural diagram of an array substrate provided in an embodiment of this application;

[0036] Figure 7 This is a cross-sectional structural diagram of an array substrate provided in an embodiment of this application;

[0037] Figure 8 This is a cross-sectional structural diagram of an array substrate provided in an embodiment of this application;

[0038] Figure 9This is an enlarged view of a partial structure in an array substrate provided in an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0040] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0041] Marker explanation:

[0042] 10. Substrate;

[0043] 20. First metal layer; 21. First part; 22. Second part;

[0044] 30. First insulating layer;

[0045] 40. First electrode layer; 41. First sub-electrode; 42. Second sub-electrode;

[0046] 50. Second metal layer;

[0047] 60. Second insulating layer;

[0048] 70. Second electrode layer; 71. Third sub-electrode;

[0049] X1, first signal line; X2, second signal line;

[0050] J1, First connecting part;

[0051] H, First through hole;

[0052] A1, Zone 1; A2, Zone 2;

[0053] Y, thickness direction. Detailed Implementation

[0054] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0055] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0056] In related technologies, display panels typically include a display area and a non-display area. The display area contains display pixels for displaying functions, while the non-display area is mainly used for wiring and other structures. Display pixels consist of multiple stacked film layers, with most of these layers typically formed using vapor deposition.

[0057] To ensure the uniformity of film layer dimensions among the display pixels within the display area and improve the yield of the fabrication process, virtual pixels are typically formed in the non-display area surrounding the display area. Virtual pixels have a similar film layer structure to display pixels, but unlike display pixels, they lack a light-emitting layer; that is, they cannot emit light. During fabrication, the film layer located at the virtual pixel position in the non-display area is fabricated simultaneously with the film layer in the display pixels within the display area, thus creating similar or identical film layers.

[0058] Specifically, the metal structure corresponding to the virtual pixel location is disposed in the same layer as the metal structure corresponding to the display pixel location, and both are formed in the same fabrication process. Similarly, the electrode structure corresponding to the virtual pixel location is disposed in the same layer as the electrode structure corresponding to the display pixel location, and both are formed in the same fabrication process.

[0059] Furthermore, to improve the anti-static capability of the display panel, the metal structure located at the virtual pixel position is typically electrically connected to a fixed potential to reduce the risk of static electricity entering the display area. To reduce the difficulty of crossing lines, the electrode structure located at the virtual pixel position is electrically connected to a fixed potential, and the electrode structure is also electrically connected to some structures located within the display area.

[0060] Through research, the inventors discovered that during the vapor deposition process, because the edge of the mask is located near the boundary between the display area and the non-display area, and the mask itself carries static electricity, the static electricity generated at the edge of the mask during the mask alignment process can break down the film layer located between the electrode structure and the metal structure at the virtual pixel position. This causes a short circuit between the electrode structure and the metal structure at the virtual pixel position, resulting in crosstalk between different signals and thus causing display abnormalities.

[0061] To solve the above problems, firstly, please refer to [the relevant information]. Figures 1 to 3 This application provides an array substrate having a first region A1 and a second region A2 that at least partially surrounds the first region A1. The array substrate includes a substrate 10, a first metal layer 20, a first insulating layer 30, and a first electrode layer 40. The first metal layer 20 is located on one side of the substrate 10 and includes a first portion 21 located in the first region A1 and a second portion 22 located in the second region A2.

[0062] The first insulating layer 30 is located on the side of the first metal layer 20 facing away from the substrate 10. The first electrode layer 40 is insulated from the first metal layer 20 through the first insulating layer 30. The first electrode layer 40 includes a first sub-electrode 41 located in the first region A1 and a second sub-electrode 42 located in the second region A2. The first sub-electrode 41 and the second sub-electrode 22 maintain the same potential.

[0063] An array substrate can be used to form a display panel, and the array substrate has at least two regions: a first region A1 and a second region A2. The first region A1 of the array substrate corresponds to the display area of ​​the display panel, and the second region A2 corresponds to the non-display area of ​​the display panel. In other words, the display panel can have multiple display pixels arranged at the position corresponding to the first region A1, and drive traces arranged at the position corresponding to the second region A2.

[0064] The array substrate includes a substrate 10, which mainly serves as a support and carrier. Other film layers are stacked sequentially on the substrate 10. The stacking here refers to the other film layers being arranged sequentially along the thickness direction Y of the substrate 10.

[0065] A first metal layer 20 is disposed on one side of the substrate 10. The first metal layer 20 includes a first portion 21 located in a first region A1 and a second portion 22 located in a second region A2. The first portion 21 and the second portion 22 are made of the same material and are located in the same film layer. During the fabrication process, the first portion 21 and the second portion 22 of the first metal layer 20 are formed together in the same fabrication step.

[0066] The first insulating layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10. The first insulating layer 30 is used to insulate and separate the first metal layer 20 from the first electrode layer 40, thereby reducing the risk of signal crosstalk between the first electrode layer 40 and the first metal layer 20.

[0067] The first electrode layer 40 includes a first sub-electrode 41 and a second sub-electrode 42. The first sub-electrode 41 is located in the first region A1. In the subsequently formed display panel, the first sub-electrode 41 serves as the anode of the display pixel to drive the display pixel to emit light. That is, the first sub-electrode 41 corresponds to the display pixel setting in the display panel. The second sub-electrode 42 is located in the second region A2. The second sub-electrode 42 corresponds to the virtual pixel setting in the display panel.

[0068] The first sub-electrode 41 and the second sub-electrode 42 are made of the same material and are located in the same film layer. During the fabrication process, the first sub-electrode 41 and the second sub-electrode 42 are formed together in the same fabrication step. Exemplarily, the materials of the first sub-electrode 41 and the second sub-electrode 42 include at least one of indium tin oxide (ITO), indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.

[0069] In this embodiment of the application, a virtual pixel is set in the second region A2, that is, a second part 22 and a second sub-electrode 42 are set so that the film layer conditions at the edge of the display area are consistent with the film layer conditions at other locations in the display area, thereby ensuring that the film layer structure size of the display pixel formed by vapor deposition at the edge of the display area is similar or the same as that of the display pixel formed by vapor deposition at other locations in the display area.

[0070] As can be seen from the foregoing, since the edge of the mask is located near the boundary between the display area and the non-display area, and the mask itself carries static electricity, the static electricity generated at the edge of the mask during the mask alignment process will break down the first insulating layer 30 between the first metal layer 20 and the first electrode layer 40, thereby causing the second part 22 and the second sub-electrode 42 to short-circuit.

[0071] Based on this, in this embodiment, the second sub-electrode 42 and the second portion 22 are configured to maintain the same potential, meaning that the signal magnitude transmitted by both at different times is the same. In this case, even if the first insulating layer 30 is broken down under electrostatic discharge, causing the second sub-electrode 42 and the second portion 22 to connect, because the second sub-electrode 42 and the second portion 22 have the same potential, the breakdown of the first insulating layer 30 will not cause any change in the transmitted signal within the second sub-electrode 42 and the second portion 22, and therefore will not affect the signal lines connected to the second sub-electrode 42 or the signal lines connected to the second portion 22. This design improves the reliability of signal transmission and reduces the probability of display abnormalities.

[0072] Furthermore, in the display panel formed using the array substrate provided in the embodiments of this application, since a specific signal is transmitted within the second part 22, compared to the case where the second part 22 is not connected to a potential, the second part 22 in the embodiments of this application can more easily discharge or neutralize static electricity, thereby reducing the impact of static electricity on the display effect and improving display reliability.

[0073] It should be noted that, for the first sub-electrode 41 and the second sub-electrode 42, the signal transmitted by the second sub-electrode 42 can be the same as or different from the signal transmitted by the first sub-electrode 41. Similarly, for the first part 21 and the second part 22, the signal transmitted by the second part 22 can be the same as or different from the signal transmitted by the first part 21. Furthermore, the second sub-electrode 42 and the second part 22 can be connected to the same signal line or to different signal lines, as long as the second sub-electrode 42 and the second part 22 can maintain the same potential.

[0074] In some embodiments, the array substrate further includes a first signal line X1, a second sub-electrode 42 electrically connected to the first signal line X1, and a second portion 22 connected to the first signal line X1 or the second sub-electrode 42.

[0075] The first signal line X1 can be located within the first region A1 or the second region A2. Exemplarily, the first signal line X1 is located within the second region A2, and at least partially located on the side of the second sub-electrode 42 opposite to the first sub-electrode 41. Furthermore, the first signal line X1 can be used to transmit either a high-level signal or a low-level signal; this embodiment does not limit the type of signal transmitted by the first signal line X1. Exemplarily, the first signal line X1 can be a power line used to drive the display pixels to emit light.

[0076] The second sub-electrode 42 is electrically connected to the first signal line X1. The second sub-electrode 42 can be connected to the first signal line X1 through the cooperation of the wiring and vias. The signal in the first signal line X1 can be transmitted to the second sub-electrode 42 so that the second sub-electrode 42 transmits the same signal as the first signal line X1.

[0077] Based on this, the second part 22 can be directly connected to the first signal line X1, and the signal in the first signal line X1 is directly transmitted to the second part 22, so that the second part 22 and the second sub-electrode 42 both transmit the same signal as the first signal line X1, that is, all three can maintain the same potential.

[0078] Alternatively, the second part 22 can also be directly connected to the second sub-pole 42. The signal in the first signal line X1 is first transmitted to the second sub-pole 42, and then transmitted to the second part 22 together with the second sub-pole 42. This design also allows the second part 22 and the second sub-pole 42 to transmit the same signal as the first signal line X1.

[0079] In summary, by connecting the second part 22 to the first signal line X1 or connecting the second part 22 to the second sub-electrode 42, the second part 22 and the second sub-electrode 42 maintain the same potential. Even if the first insulating layer 30 between the second part 22 and the second sub-electrode 42 breaks down, it will not cause the transmission signal in the second sub-electrode 42 and the second part 22 to change, and thus will not affect the first signal line X1, ensuring the reliability of signal transmission inside the first signal line X1.

[0080] In some embodiments, such as Figure 3 As shown, along the thickness direction Y of the substrate 10, a first through hole H is provided on the first insulating layer 30, and the second sub-electrode 42 and the second part 22 are connected through the first through hole H.

[0081] The orthographic projection of the first via H onto the substrate 10 overlaps with the orthographic projections of the second sub-electrode 42 and the second portion 22 onto the substrate 10. The first via H penetrates the first insulating layer 30 along the thickness direction Y, and a conductive material is disposed within the first via H to enable signal transmission between the second sub-electrode 42 and the second portion 22. The conductive material within the first via H may be the same as the material of either the second portion 22 or the second sub-electrode 42, or it may be different from the materials of both the second portion 22 and the second sub-electrode 42.

[0082] In this embodiment, to ensure that the second portion 22 and the second sub-electrode 42 maintain the same potential, the second sub-electrode 42 and the second portion 22 are electrically connected through a first via H, enabling signal transmission between them. This design eliminates the need for additional wiring structures, thereby indirectly reducing the complexity of the internal wiring of the array substrate.

[0083] In some embodiments, there are multiple first through holes H, which are arranged side by side and are all used to connect the second sub-electrode 42 and the second part 22. The presence of multiple first through holes H can improve the reliability of signal transmission between the second sub-electrode 42 and the second part 22, thereby ensuring that the second part 22 can be maintained at a constant potential and improving the electrostatic blocking effect of the second part 22.

[0084] In some embodiments, please refer to Figure 4 and Figure 5The array substrate also includes a second signal line X2 and a first connection portion J1. At least a portion of the second signal line X2 is projected onto the substrate 10 between the second portion 22 and the first signal line X1. One end of the first connection portion J1 is connected to the first signal line X1, and the other end of the first connection portion J1 is connected to the second portion 22.

[0085] The second signal line X2 transmits different signals from the first signal line X1. The voltages transmitted by the two lines can be the same or different. For example, the voltage of the first signal line X1 is lower than the voltage of the second signal line X2, that is, the first signal line X1 transmits a low-level voltage, and the second signal line X2 transmits a high-level signal.

[0086] Compared to the first signal line X1, the second signal line X2 is closer to the virtual pixel setting. Therefore, in related technologies, the second part 22 is often connected to the second signal line X2. However, due to the needs of signal transmission, the second sub-electrode 42 is connected to the first signal line X1, thereby enabling the second part 22 and the second sub-electrode 42 to transmit different signals.

[0087] In this embodiment, to ensure that the second sub-electrode 42 and the second portion 22 maintain the same potential, a first connection portion J1 is provided within the array substrate. The first connection portion J1 is a conductive structure used to connect the second portion 22 and the first signal line X1. The material of the first connection portion J1 can be the same as or different from the material of the second portion 22. The first connection portion J1 can be a straight structure, a curved structure, or a broken line structure; this embodiment does not impose any limitations on this.

[0088] The first connecting portion J1 has two opposing ends in its extending direction. One end is connected to the first signal line X1. When the first signal line X1 and the first connecting portion J1 are located in the same film layer, the first connecting portion J1 can be directly connected to the first signal line X1. However, when the first signal line X1 and the first connecting portion J1 are located in different film layers, they need to be connected through a via. The other end of the first connecting portion J1 is connected to the second portion 22. When the second portion 22 and the first connecting portion J1 are located in the same film layer, the first connecting portion J1 can be directly connected to the second portion 22. However, when the second portion 22 and the first connecting portion J1 are located in different film layers, they need to be connected through a via.

[0089] In some embodiments, please refer to Figure 6 The second signal line X2 and the first signal line X1 are located in different film layers, and the first signal line X1, the second part 22 and the first connecting part J1 are arranged in the same layer.

[0090] Since at least a portion of the second signal line X2 is projected onto the substrate 10 between the second portion 22 and the first signal line X1, the presence of the second signal line X2 may hinder the connection between the first signal line X1 and the second portion 22.

[0091] Based on this, in this embodiment of the application, the second signal line X2 and the first signal line X1 are disposed on different film layers, while the first signal line X1 and the second part 22 are located on the same film layer. Therefore, the first connecting part J1 used to connect the first signal line X1 and the second part 22 can be disposed on the same layer as the first signal line X1 and the second part 22. Furthermore, the connection between the first connecting part J1 and the first signal line X1 or the second part 22 does not need to be through a via, thereby optimizing the wiring layout inside the array substrate.

[0092] In some embodiments, please refer to Figure 7 At least one of the first signal line X1 and the second part 22 is located in the same film layer as the second signal line X2, and the first connection part J1 is located on one side of the second signal line X2 in the thickness direction Y of the substrate 10.

[0093] At least one of the first signal line X1 and the second part 22 is located in the same film layer as the second signal line X2. If the first connection part J1 is set to be in the same layer as the first signal line X1 and the second part 22, it will cause physical interference between the first connection part J1 and the second signal line X2, which will easily lead to the risk of signal crosstalk.

[0094] Therefore, in this embodiment of the application, the first connection part J1 is disposed on one side of the second signal line X2 in the thickness direction Y of the substrate 10, so that the first connection part J1 and the second signal line X2 will not physically interfere, thus ensuring the reliability of the signal transmission between the first connection part J1 and the second signal line X2.

[0095] It should be noted that the specific position of the first connection portion J1 relative to the second signal line X2 is not limited in this embodiment. The first connection portion J1 may be located on the side of the second signal line X2 closer to the substrate 10, or it may be located on the side of the second signal line X2 away from the substrate 10.

[0096] In some embodiments, such as Figure 7 As shown, the array substrate also includes a second metal layer 50 disposed between the first metal layer 20 and the substrate 10, and the first connection portion J1 is located within the second metal layer 50.

[0097] The second metal layer 50 is located on the side of the first metal layer 20 facing the substrate 10. A second insulating layer 60 can be disposed between the second metal layer 50 and the first metal layer 20 to achieve mutual insulation between them. Based on this, in this embodiment, the first connecting portion J1 is disposed within the second metal layer 50, so that the first connecting portion J1 is disposed in the same layer as other metal structures within the second metal layer 50. Therefore, it is not necessary to add other film layers to accommodate the first connecting portion J1, which can reduce the thickness of the array substrate to a certain extent and improve the tactile feel of the subsequently formed display panel. At the same time, the first connecting portion J1 can be formed simultaneously with other metal materials within the second metal layer 50 in the same process, thereby simplifying the manufacturing process.

[0098] In some embodiments, please refer to Figure 8 The first signal line X1 is located within the second metal layer 50, that is, the first signal line X1 and the first connection part J1 are disposed on the same layer, and the connection between them can be achieved without the need to provide vias. Furthermore, the first signal line X1 and the first connection part J1 can be formed synchronously in the same manufacturing process.

[0099] In some embodiments, please refer to Figure 9 The distance between the first signal line X1 and the second part 22 is less than the distance between any other signal line and the second part 22, and the second part 22 is connected to the first signal line X1. Figure 9 In the middle, the second part 22 is shown in the form of a dotted line.

[0100] Since the distance between the first signal line X1 and the second part 22 is less than the distance between any other signal line and the second part 22, there are no other signal lines between the first signal line X1 and the second part 22. Specifically, in one case, in related technologies, the second sub-pole 42 is not connected to the first signal line X1, but is connected to other signal lines. However, in this embodiment, the second sub-pole 42 and the second part 22 are both connected to the first signal line X1, thereby ensuring that the second sub-pole 42 and the second part 22 can transmit the same signal.

[0101] Alternatively, in related technologies, the first signal line X1 is located at a position far from the second part 22, the second sub-electrode 42 is connected to the first signal line X1, while the second part 22 is not connected to the first signal line X1. However, in this embodiment, by adjusting the position of the first signal line X1, the first signal line X1 is positioned closest to the second part 22 and electrically connected to both the second sub-electrode 42 and the second part 22, thereby ensuring that the second sub-electrode 42 and the second part 22 can transmit the same signal.

[0102] In this embodiment of the application, by placing the first signal line X1 at the position closest to the second part 22, the second part 22 can more easily connect with the first signal line X1, reducing the difficulty of wiring.

[0103] In some embodiments, the array substrate further includes a third signal line, and the first sub-electrode 41 is connected to the third signal line (not shown in the figure), and the voltage of the third signal line is higher than the voltage of the first signal line X1.

[0104] The first signal line X1 and the third signal line transmit different signals. Therefore, the two sub-electrodes connected to the first signal line X1 and the first sub-electrode 41 connected to the third signal line transmit different signals. The first sub-electrode 41 can be used as an anode in the display pixel, while the second sub-electrode 42 is not used to form a display pixel, but is used to realize the signal transmission function.

[0105] Optionally, the second sub-electrode 42 can be connected to the cathode of the display pixel. That is, the first signal line X1 is a power signal line used to drive the transmission of signals to the cathode, and the second sub-electrode 42 is used to transfer the signal transmitted by the first signal line X1 to the cathode, thereby reducing the difficulty of crossing the line.

[0106] In some embodiments, such as Figure 9 As shown, the distance between the second sub-pole 42 and the first region A1 is L, and L satisfies: L≥10μm.

[0107] The first sub-pole 41 is located in the first region A1, and the second sub-pole 42 is located in the second region A2. They transmit different signals. Therefore, in order to reduce the risk of signal interference between the second sub-pole 42 and the first sub-pole 41, it is necessary to control the distance between the first sub-pole 41 and the second sub-pole 42. More specifically, it is necessary to control the distance between the second sub-pole 42 and the first region A1.

[0108] In this embodiment, the distance between the second sub-electrode 42 and the first region A1 is set to be no less than 10 μm, thereby ensuring that there is a certain gap between the first sub-electrode 41 and the second sub-electrode 42 and reducing the risk of signal interference between the first sub-electrode 41 and the second sub-electrode 42.

[0109] Secondly, please refer to Figure 10 This application provides a display panel that includes the array substrate of any of the foregoing embodiments.

[0110] It should be noted that the display panel provided in this application embodiment has the beneficial effects of the array substrate in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the array substrate. This application embodiment will not repeat the details.

[0111] In some embodiments, such as Figure 10As shown, the display panel also includes a second electrode layer 70 disposed on the side of the first electrode layer 40 away from the substrate 10. The second electrode layer 70 includes a third sub-electrode 71 located in the first region A1. The first sub-electrode 41 and the third sub-electrode 71 are used to drive the display pixels to emit light, wherein the third sub-electrode 71 is connected to the second sub-electrode 42.

[0112] The second electrode layer 70 includes a third sub-electrode 71. The first sub-electrode 41 and the third sub-electrode 71 overlap in their orthogonal projections onto the substrate 10. Multiple film structures are sandwiched between the first sub-electrode 41 and the third sub-electrode 71 to form a display pixel. Exemplarily, the space between the first sub-electrode 41 and the third sub-electrode 71 includes an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer, etc.

[0113] The first sub-electrode 41 and the third sub-electrode 71 are the anode and cathode of the display pixel, respectively, and they transmit different signals. Normally, the first sub-electrode 41 transmits a high-level signal, and the third sub-electrode 71 transmits a low-level signal.

[0114] To reduce the difficulty of routing the traces corresponding to the third sub-pole 71, this embodiment connects the second sub-pole 42 to the first signal line X1 used to transmit signals to the third sub-pole 71, and connects the third sub-pole 71 to the second sub-pole 42. Signal transmission between the first signal line X1 and the third sub-pole 71 is achieved through the second sub-pole 42. Compared to a scheme where the first signal line X1 and the third sub-pole 71 are connected via routing, this method reduces the difficulty of routing and improves the reliability of signal transmission.

[0115] Thirdly, please refer to Figure 11 This application provides a display device, including the display panel in any of the foregoing embodiments.

[0116] It should be noted that the display device provided in this application embodiment has the beneficial effects of the display panel in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the display panel. This application embodiment will not repeat the details.

[0117] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0118] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. An array substrate, characterized in that, The array substrate has a first region and a second region at least partially surrounding the first region, the array substrate comprising: Substrate; A first metal layer is located on one side of the substrate, the first metal layer comprising a first portion located in the first region and a second portion located in the second region; A first insulating layer is located on the side of the first metal layer that faces away from the substrate; The first electrode layer is insulated from the first metal layer by the first insulating layer, and the first electrode layer includes a first sub-electrode located in the first region and a second sub-electrode located in the second region; The second sub-electrode maintains the same potential as the second part, the first sub-electrode corresponds to the display pixel setting and is used to drive light emission, and the second sub-electrode corresponds to the virtual pixel setting.

2. The array substrate according to claim 1, characterized in that, It also includes a first signal line, and the second sub-electrode is electrically connected to the first signal line; The second part is connected to the first signal line or the second sub-pole.

3. The array substrate according to claim 2, characterized in that, The first signal line is located within the second region, and at least a portion of the first signal line is located on the side of the second sub-electrode opposite to the first sub-electrode.

4. The array substrate according to claim 2, characterized in that, Along the thickness direction of the substrate, a first through hole is provided on the first insulating layer, and the second sub-electrode and the second portion are connected through the first through hole.

5. The array substrate according to claim 4, characterized in that, The number of the first through holes is multiple.

6. The array substrate according to claim 2, characterized in that, It also includes a second signal line and a first connection portion, wherein at least a portion of the second signal line's orthographic projection on the substrate lies between the second portion and the first signal line's orthographic projection on the substrate; One end of the first connector is connected to the first signal line, and the other end of the first connector is connected to the second part.

7. The array substrate according to claim 6, characterized in that... The voltage of the first signal line is lower than the voltage of the second signal line.

8. The array substrate according to claim 6, characterized in that... The second signal line and the first signal line are located in different film layers, and the first signal line, the second part, and the first connecting part are disposed in the same layer.

9. The array substrate according to claim 6, characterized in that, At least one of the first signal line and the second portion is located in the same film layer as the second signal line; The first connection portion is located on one side of the second signal line in the thickness direction of the substrate.

10. The array substrate according to claim 9, characterized in that... The array substrate further includes a second metal layer disposed between the first metal layer and the substrate, and the first connection portion is located within the second metal layer.

11. The array substrate according to claim 10, characterized in that... The first signal line is located within the second metal layer.

12. The array substrate according to claim 2, characterized in that, The distance between the first signal line and the second part is less than the distance between any other signal line and the second part, and the second part is connected to the first signal line.

13. The array substrate according to claim 2, characterized in that, It also includes a third signal line, to which the first sub-electrode is connected, and the voltage of the third signal line is higher than that of the first signal line.

14. The array substrate according to claim 13, characterized in that, The distance between the second sub-pole and the first region is L, where L satisfies: L ≥ 10μm.

15. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 14.

16. The display panel according to claim 15, characterized in that, It also includes a second electrode layer disposed on the side of the first electrode layer opposite to the substrate, the second electrode layer including a third sub-electrode located in the first region, the first sub-electrode and the third sub-electrode being used to drive the display pixels to emit light; The third sub-pole is connected to the second sub-pole.

Images