Oxide thin film transistor and method for manufacturing the same, electronic device

Abstract

Embodiments of the present disclosure provide an oxide thin film transistor and a preparation method thereof and an electronic device, the oxide thin film transistor comprising: a substrate substrate; a gate and a metal oxide semiconductor layer which are sequentially stacked on the substrate substrate; a gate insulating layer provided between the metal oxide semiconductor layer and the gate, wherein the gate insulating layer comprises a silicon oxide insulating layer and a silicon nitride layer which are sequentially stacked, the silicon nitride layer is a single layer structure or comprises a plurality of silicon nitride sub-layers which are sequentially stacked, and the silicon oxide insulating layer is provided between the silicon nitride layer and the metal oxide semiconductor layer; and at least part of the silicon nitride layer satisfies: a percentage content of Si-H bonds in a total of Si-N bonds, N-H bonds and Si-H bonds in the at least part of the silicon nitride layer is not greater than 7%, and the thin film transistor can solve the problem of bulging of the gate insulating layer by adjusting the structure of the gate insulating layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an oxide thin-film transistor, a method for fabricating an oxide thin-film transistor, and an electronic device. Background Technology

[0002] Oxide semiconductor thin-film transistors have advantages such as high mobility, good stability, and simple fabrication process. Oxide semiconductor materials, represented by indium gallium zinc oxide (IGZO), are widely used in thin-film transistor liquid crystal displays (TFT-LCD) and active-matrix organic light-emitting diode panels (AMOLED).

[0003] Thin-film transistors (TFTs) can be classified into top-gate and bottom-gate structures based on the position of the gate electrode relative to the active region, and into top-contact and bottom-contact structures based on the position of the source and drain electrodes relative to the active region. In other words, the four common structures of TFTs are bottom-gate top contact (interleaved bottom-gate), bottom-gate bottom contact (coplanar bottom-gate), top-gate top contact (coplanar top-gate), and top-gate bottom contact (interleaved top-gate). Currently, the structures of oxide semiconductor layer TFTs mainly include three types: etch-block type, back-channel etch type, and coplanar type. The fabrication process for back-channel etch type metal oxide TFTs is relatively simple, requiring one less photolithography step than etch-block type, which reduces equipment investment and improves production efficiency. Summary of the Invention

[0004] This disclosure provides at least one embodiment of an oxide thin-film transistor, a method for fabricating an oxide thin-film transistor, and an electronic device. The thin-film transistor can solve the problem of gate insulating layer bulging by adjusting the structure of the gate insulating layer.

[0005] At least one embodiment of this disclosure provides an oxide thin-film transistor, which includes: a substrate; a gate and a metal oxide semiconductor layer sequentially stacked on the substrate; and a gate insulating layer disposed between the metal oxide semiconductor layer and the gate, wherein the gate insulating layer includes a silicon oxide insulating layer and a silicon nitride layer stacked on top of each other, the silicon nitride layer being a single-layer structure or including a plurality of silicon nitride sublayers stacked on top of each other, and the silicon oxide insulating layer being disposed between the silicon nitride layer and the metal oxide semiconductor layer; and at least a portion of the silicon nitride layer satisfies the following condition: the percentage of Si-H bonds in the sum of Si-N bonds, NH bonds, and Si-H bonds is not greater than 7%.

[0006] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, at least a portion of the silicon nitride layer satisfies the following condition: the percentage of Si-H bonds in the total of Si-N bonds, NH bonds, and Si-H bonds is 0.5% to 7%.

[0007] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, the silicon nitride layer is a single-layer structure, the percentage content of Si-H bonds in at least a portion of the region of the silicon nitride layer is positively correlated with the percentage content of Si-H bonds in at least a portion of the region of the silicon oxide insulating layer, and the stress difference between the gate and the silicon nitride layer is 400 MPa to 950 MPa, and the stress difference between the silicon nitride layer and the silicon oxide insulating layer is 50 MPa to 400 MPa.

[0008] For example, in at least one embodiment of the oxide thin-film transistor provided in this disclosure, the silicon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer stacked together. The first silicon nitride sublayer is in contact with the silicon oxide insulating layer, and the second silicon nitride sublayer is disposed on the side of the first silicon nitride sublayer away from the silicon oxide insulating layer and in contact with the gate; the thickness of the second silicon nitride sublayer is [missing information]. to The stress of the second silicon nitride sublayer is -400 MPa to -600 MPa, and the stress difference between the second silicon nitride sublayer and the gate is 670 MPa to 870 MPa; the thickness of the first silicon nitride sublayer is... to The stress of the first silicon nitride sublayer is -400 MPa to -800 MPa, and the stress difference between the first silicon nitride sublayer and the second silicon nitride sublayer is 0 MPa to 200 MPa. The stress difference between the first silicon nitride sublayer and the silicon oxide insulating layer is 50 MPa to 400 MPa, and the stress difference between any adjacent film layers does not exceed 1000 MPa.

[0009] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, the thicknesses of the silicon nitride layer and the silicon oxide insulating layer are d1 and d2, respectively, and the thickness of the gate insulating layer is d, where 3500 angstroms < d1 + d2 = d < 5000 angstroms, and 200 angstroms < d2 < 2000 angstroms, and 4% < d2 / d < 57%.

[0010] For example, in at least one embodiment of the oxide thin-film transistor provided in this disclosure, a source and a drain are disposed on the side of the metal oxide semiconductor layer away from the substrate, spaced apart from each other; the capacitance between the metal oxide semiconductor layer and the gate is C; and the current between the source and the drain is I when the thin-film transistor is turned on. DS The dielectric constant of the silicon oxide insulating layer is less than that of the metal oxide semiconductor layer, and the thickness d2 of the silicon oxide insulating layer is related to the current I in the metal oxide semiconductor layer. DS The thickness d2 of the silicon oxide insulating layer is inversely proportional to the capacitance C between the metal oxide semiconductor layer and the gate.

[0011] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, the thickness of the metal oxide semiconductor layer is h, and satisfies 10.8% < d² / d < 11.76% and 3.5% < h / d < 7.4%.

[0012] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, the thickness of the metal oxide semiconductor layer is h, and satisfies 21.8% < d² / d < 37% and 2% < h / d < 3.5%.

[0013] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, the thickness of the metal oxide semiconductor layer is h, and satisfies 21.8% < d² / d < 22.3% and 2.5% < h / d < 2.9%.

[0014] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, 200 Å < d2 < 400 Å.

[0015] For example, in an oxide thin-film transistor provided in at least one embodiment of this disclosure, the oxide thin-film transistor is a bottom-gate thin-film transistor, and an insulating protective layer is provided on the side of the source and the drain away from the substrate. The metal oxide semiconductor layer and the insulating protective layer are in contact in a spaced region between the source and the drain. The metal oxide semiconductor layer includes a first surface and a second surface opposite to each other. The gate insulating layer is in contact with the first surface of the metal oxide semiconductor layer, and the insulating protective layer is in contact with the second surface of the metal oxide semiconductor layer.

[0016] For example, in at least one embodiment of the oxide thin-film transistor provided in this disclosure, the insulating protective layer includes a first insulating layer and a second insulating layer stacked thereon. The second insulating layer is located on the side of the first insulating layer closest to the metal oxide semiconductor layer and is in contact with the metal oxide semiconductor layer. The first insulating layer is located on the side of the second insulating layer away from the metal oxide semiconductor layer and is not in contact with the metal oxide semiconductor layer. The material of the first insulating layer includes SiN. x Where x is greater than 0; the material of the second insulating layer includes SiO2. y , where y is greater than 0.

[0017] For example, in an oxide thin-film transistor provided in at least one embodiment of this disclosure, the metal oxide semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer stacked together, the crystallinity of the second metal oxide semiconductor layer is greater than that of the first metal oxide semiconductor layer, the conductivity of the second metal oxide semiconductor layer is lower than that of the first metal oxide semiconductor layer, and the second metal oxide semiconductor layer is further away from the substrate relative to the first metal oxide semiconductor layer.

[0018] For example, in the oxide thin-film transistor provided in at least one embodiment of this disclosure, the material of the first metal oxide semiconductor layer includes at least two of the metal elements indium, gallium, zinc and tin; the material of the second metal oxide semiconductor layer includes at least two of the metal elements indium, gallium, zinc and tin.

[0019] For example, in at least one embodiment of the oxide thin-film transistor provided in this disclosure, the gate material comprises at least one of the metal elements molybdenum, aluminum, and copper, and the thickness of the gate is [missing information]. to

[0020] At least one embodiment of this disclosure also provides an electronic device including the oxide thin-film transistor of any of the above embodiments.

[0021] At least one embodiment of this disclosure also provides a method for fabricating an oxide thin-film transistor. The method includes: providing a substrate; forming a gate, a gate insulating layer, and a metal oxide semiconductor layer on the substrate; wherein forming the gate insulating layer includes forming a silicon oxide insulating layer and a silicon nitride layer, the silicon nitride layer being a single-layer structure or comprising a plurality of silicon nitride sublayers stacked sequentially, the silicon nitride layer being formed on the side of the silicon oxide insulating layer near the gate and in contact with the gate, the silicon oxide insulating layer being formed on the side of the silicon nitride layer near the metal oxide semiconductor layer and in contact with the metal oxide semiconductor layer, and at least a portion of the silicon nitride layer having a region satisfying that: the percentage of Si-H bonds in the at least a portion of the region relative to the sum of Si-N bonds, NH bonds, and Si-H bonds is not greater than 7%.

[0022] For example, in the preparation method provided in at least one embodiment of this disclosure, the silicon nitride layer is a single-layer structure, and the etching rate for wet etching of the silicon nitride layer is [missing information]. to

[0023] For example, in the preparation method provided in at least one embodiment of this disclosure, the etching solution used to etch the silicon nitride layer is a mixture of NH3F and HF, wherein the mass percentages of NH3F and HF in the mixture are 29.8% to 30.2% and 5.9% to 6.1%, respectively.

[0024] For example, the preparation method provided in at least one embodiment of this disclosure further includes: applying a metal electrode thin film on the side of the metal oxide semiconductor layer away from the substrate, and performing a patterning process on the metal electrode thin film to form mutually spaced source and drain electrodes, and forming an insulating protective layer on the side of the source and drain electrodes away from the substrate, wherein the metal oxide semiconductor layer and the insulating protective layer are in contact in the region spaced between the source and drain electrodes.

[0025] At least one embodiment of this disclosure also provides an oxide thin-film transistor, which includes: a gate, a gate insulating layer, and a metal oxide semiconductor layer stacked on a substrate, wherein the gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked thereon; the first gate insulating layer is located between the gate and the second gate insulating layer, and the material of the first gate insulating layer includes Si and N elements; the second gate insulating layer is located between the metal oxide semiconductor layer and the first gate insulating layer, and the material of the second gate insulating layer includes Si and O elements; the second gate insulating layer is on the side of the first gate insulating layer close to the metal oxide semiconductor layer and in contact with the metal oxide semiconductor layer, and the first gate insulating layer is on the side of the second gate insulating layer away from the metal oxide semiconductor layer and is not in contact with the metal oxide semiconductor layer; the thicknesses of the first gate insulating layer and the second gate insulating layer are d1 and d2, respectively, and the thickness of the gate insulating layer is d, where 3500 Å < d1 + d2 = d < 5000 Å, and 200 Å < d2 < 2000 Å, and 4% < d2 / d < 57%.

[0026] For example, an oxide thin-film transistor according to at least one embodiment of this disclosure further includes a source and a drain, wherein the capacitance between the metal oxide semiconductor layer and the gate is C, and the current between the source and the drain after the thin-film transistor is turned on is I. DS The thickness d2 of the second gate insulating layer is related to the current I. DS The capacitance C between the metal oxide semiconductor layer and the gate is inversely proportional to the second gate insulating layer, which is a silicon oxide insulating layer, and the first gate insulating layer is a silicon nitride layer.

[0027] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, 5.7% < d2 / d < 40%.

[0028] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, the thickness of the metal oxide semiconductor layer is h, 10.8% < d² / d < 11.76%, and 3.5% < h / d < 7.4%.

[0029] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, the thickness of the metal oxide semiconductor layer is h, 21.8% < d2 / d < 37%, and 2% < h / d < 3.5%.

[0030] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, the thickness of the metal oxide semiconductor layer channel is h, 21.8% < d2 / d < 22.3%, 2.5% < h / d < 2.9%.

[0031] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, 200 Å < d2 < 400 Å.

[0032] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, the metal oxide semiconductor layer includes a single-layer structure or a multilayer stacked structure.

[0033] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the metal oxide semiconductor layer includes a multilayer stacked structure, the metal oxide semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer stacked together, the density of the first metal oxide semiconductor layer is greater than the density of the second metal oxide semiconductor layer, and the second metal oxide semiconductor layer is disposed on the side of the first metal oxide semiconductor layer near the substrate and in contact with the second gate insulating layer.

[0034] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, the material of the metal oxide semiconductor layer includes at least one of indium gallium zinc oxide, Sn-containing indium gallium zinc oxide, and lanthanide metal oxides.

[0035] For example, in an oxide thin-film transistor of at least one embodiment of this disclosure, the mobility of the metal oxide semiconductor layer is 5 cm. 2 / v·s up to 50cm 2 / v·s.

[0036] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the oxide thin-film transistor is a bottom-gate thin-film transistor, and the oxide thin-film transistor further includes a passivation layer disposed on the side of the source and the drain away from the substrate. The metal oxide semiconductor layer includes a first surface and a second surface opposite to each other. The second gate insulating layer is in contact with the first surface of the metal oxide semiconductor layer, and the passivation layer is in contact with the second surface of the metal oxide semiconductor layer.

[0037] For example, in an oxide thin-film transistor according to at least one embodiment of the present disclosure, the passivation layer includes a first passivation layer and a second passivation layer stacked together. The material of the first passivation layer includes SiNx and does not include oxygen, wherein x is greater than 0. The material of the second passivation layer includes SiOy, wherein y is greater than 0. The second passivation layer is located on the side of the first passivation layer close to the metal oxide semiconductor layer and is in contact with the metal oxide semiconductor layer. The first passivation layer is located on the side of the second passivation layer away from the metal oxide semiconductor layer and is not in contact with the metal oxide semiconductor layer. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0039] Figure 1 This is a schematic cross-sectional view of an oxide thin-film transistor according to an embodiment of the present disclosure;

[0040] Figure 2 This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure;

[0041] Figure 3 A schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of this disclosure;

[0042] Figure 4 A schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of this disclosure;

[0043] Figure 5 A schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of this disclosure;

[0044] Figure 6 A flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of this disclosure; and

[0045] Figure 7This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0048] Compared to silicon-based and organic semiconductor thin-film transistors (TFTs), oxide semiconductor thin-film transistors (OSTs) are becoming increasingly important in high-end display applications due to their higher mobility. With the continuous development of electronic products, the development of high-mobility OSTs has become a key research focus for display panel manufacturers. However, as the mobility of OSTs increases, the requirements for their stability also become increasingly stringent.

[0049] The internal stress of SiOx thin films, formed from silicon and oxygen, is generally a large negative stress, for example, about -350 MPa, while the Cu metal thin films, used as electrode materials, generally exhibit positive stress, for example, about 300 MPa. This shows a significant stress difference between the Cu metal electrode and the SiOx insulating layer. Furthermore, the Cu metal electrode and the SiOx insulating layer are primarily connected by van der Waals forces, resulting in poor adhesion. In actual production, bulging defects frequently occur between the Cu metal electrode and the SiOx insulating layer. In addition, the high-temperature process typically used when forming the active layer and subsequently the insulating layer with metal oxides can cause Cu to grow into the insulating layer, forming copper whiskers that break down the insulating layer, causing it to lose its insulating function and resulting in short circuit defects, which severely impacts product yield.

[0050] The inventors of this disclosure noted that the bonding strength of Si-N bonds is higher than that of Si-H bonds, and the bonding strength of Si-O-Si bonds is also higher than that of Si-H-Si bonds. The bonding strength between Si-N bonds and Cu metal layers is stronger than that between Si-H bonds and copper metal layers. Furthermore, during subsequent high-temperature annealing, hydrogen (H) elements are more likely to detach and escape than oxygen (O) elements. The lower the percentage of Si-H bonds in the SiNx thin film, the more Si-N bonds there are, resulting in less hydrogen overflow during annealing, stronger bonding between adjacent film layers, higher adhesion, and a lower probability of bulging between film layers. For example, too many silicon nitride layers in the gate insulating layer may lead to production failure, while too few layers may cause stress mismatch, leading to bulging problems, thus affecting the yield of thin-film transistors and making gate lines and data lines prone to short circuits. Based on the above considerations, the inventors of this disclosure have made improvements in balancing mass production and reducing bulging to improve yield.

[0051] At least one embodiment of this disclosure provides an oxide thin-film transistor, which includes: a substrate; a gate and a metal oxide semiconductor layer sequentially stacked on the substrate; and a gate insulating layer disposed between the metal oxide semiconductor layer and the gate, the gate insulating layer including a silicon oxide insulating layer and a silicon nitride layer stacked thereon, the silicon nitride layer being a single-layer structure or including a plurality of silicon nitride sublayers stacked thereon, the silicon oxide insulating layer being disposed between the silicon nitride layer and the metal oxide semiconductor layer; and at least a portion of the silicon nitride layer satisfying that: in at least a portion of the region, the percentage of silicon-hydrogen bonds in the sum of Si-N bonds, NH bonds and Si-H bonds is not greater than 7%.

[0052] For example, Figure 1 This is a schematic cross-sectional view of an oxide thin-film transistor according to an embodiment of the present disclosure, as shown below. Figure 1As shown, the oxide thin-film transistor 10 includes: a substrate 01; a gate 02 and a metal oxide semiconductor layer 07 sequentially stacked on the substrate 01; and a gate insulating layer 03 disposed between the metal oxide semiconductor layer 07 and the gate 02. The gate insulating layer 03 includes a silicon oxide insulating layer 031 and a silicon nitride layer 032 stacked on top of each other. The silicon nitride layer 032 has a single-layer structure, and the silicon oxide insulating layer 031 is disposed between the silicon nitride layer 032 and the metal oxide semiconductor layer 07. At least a portion of the silicon nitride layer 032 contains regions that satisfy the condition that the percentage of silicon-hydrogen bonds (Si-H bonds) in the sum of silicon-nitrogen bonds (Si-N bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds) in the at least a portion of the region is not greater than 7%.

[0053] For example, the substrate 01 is formed of a rigid material or a flexible material. For example, the rigid material includes one of rigid glass and silicon wafer. The flexible material includes one of polyethylene naphthalate, polyethylene terephthalate, polyimide and flexible glass.

[0054] For example, in one instance, the material of the gate 02 comprises at least one of the metallic elements molybdenum, aluminum, and copper, and the thickness of the gate is [missing information]. to

[0055] For example, in another example, the material of the gate 02 can be copper metal, or a combination of copper metal and other metals, such as copper / molybdenum (Cu / Mo), copper / titanium (Cu / Ti), copper / molybdenum-titanium alloy (Cu / MoTi), copper / molybdenum-tungsten alloy (Cu / MoW), copper / molybdenum-niobium alloy (Cu / MoNb), etc. The material of the gate 02 can also be chromium-based metal or a combination of chromium and other metals, such as chromium / molybdenum (Cr / Mo), chromium / titanium (Cr / Ti), chromium / molybdenum-titanium alloy (Cr / MoTi), etc. In the following embodiments, copper metal is used as an example for illustration.

[0056] For example, the metal oxide semiconductor layer 07 can have a single-layer structure or a double-layer structure. For example, the metal oxide semiconductor layer 07 has a double-layer structure, which includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer stacked together. The second metal oxide semiconductor layer is further away from the gate insulating layer 03 relative to the first metal oxide semiconductor layer, and the density of the second metal oxide semiconductor layer is greater than that of the first metal oxide semiconductor layer.

[0057] For example, the material of the metal oxide semiconductor layer 07 includes at least one of the following n-type semiconductor materials: zinc oxide (ZnO), indium oxide (In2O3), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), boron-doped zinc oxide (BZO), magnesium-doped zinc oxide (MZO), zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), gallium zinc oxide (GZO), indium tin oxide (ITO), hafnium indium zinc oxide (HIZO), and tin oxide (SnO2); and at least one of the following p-type semiconductor materials: tin suboxide (SnO) and cuprous suboxide (Cu2O).

[0058] For example, the metal oxide semiconductor layer 07 can be formed by methods such as magnetron sputtering, reactive sputtering, anodizing, or spin coating.

[0059] It should be noted that a certain amount of nitrogen is also present in the silicon oxide insulating layer 031. Those skilled in the art will understand that the silicon oxide insulating layer 031 actually contains a certain amount of nitrogen because the production of silicon oxide requires the use of nitrogen-containing gaseous components, inevitably resulting in a certain amount of nitrogen present in the silicon oxide insulating layer. For example, a silicon oxide insulating layer can be formed by reacting silane with nitrous oxide (laughing gas). Silicon nitride can be formed by reacting silane with ammonia. Depending on the reactants, the percentage of silicon-hydrogen bonds in the formed silicon oxide insulating layer 031 and silicon nitride layer 032 can be controlled.

[0060] For example, a silicon oxide insulating layer 031 is disposed between a silicon nitride layer 032 and a metal oxide semiconductor layer 07, such that the silicon oxide insulating layer 031 separates the metal oxide semiconductor layer 07 and the silicon nitride layer 032, thereby reducing the risk of hydrogen elements in the silicon nitride layer 032 entering the metal oxide semiconductor layer 07.

[0061] For example, by adjusting the molar ratio of silane to nitrous oxide during the reaction, the power of the reaction chamber, and the gas pressure, the resulting silicon oxide insulating layer 031 can have different densities. The smaller the Si:O molar ratio in the silicon oxide insulating layer 031, the greater the density of the resulting silicon oxide insulating layer 031. A higher density of the silicon oxide insulating layer makes it less likely for the etching solution used in the patterning process to penetrate the silicon oxide insulating layer 031, thereby preventing the etching solution from entering the metal oxide semiconductor layer 07, and reducing the risk of damage to the metal oxide semiconductor layer 07.

[0062] For example, in the silicon nitride layer 032, at least some regions satisfy the following condition: the percentage of silicon-hydrogen bonds (Si-H bonds) in at least some regions is no more than 7% of the total percentage of silicon-nitrogen bonds (Si-N bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds). Since the chemical bonding strength of Si-H bonds is lower than that of Si-N bonds, and the bonding strength between Si-H bonds and Cu metal is weaker than that between Si-N bonds and copper metal, subsequent high-temperature annealing allows H atoms to detach and escape more easily than O atoms. If the percentage of silicon-hydrogen bonds (Si-H bonds) in the total number of silicon-nitrogen bonds (Si-N bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds) is greater than 7%, more hydrogen will escape during subsequent annealing, resulting in weaker bonding and adhesion between adjacent film layers. This increases the probability of bulging between film layers. Controlling the percentage of silicon-hydrogen bonds (Si-H bonds) to no more than 7% simplifies the operation process, thereby saving equipment and process costs.

[0063] For example, in the silicon oxide insulating layer 031, at least some regions satisfy the following condition: the percentage of silicon-hydrogen bonds (Si-H bonds) in at least some regions is between 0.1% and 15% of the total percentage of silicon-oxygen bonds (Si-O bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds). This can reduce the escape of H elements during subsequent annealing, ensure the bonding and adhesion between adjacent film layers, and reduce the probability of bulging between film layers. In addition, controlling the percentage of silicon-hydrogen bonds (Si-H bonds) in the silicon oxide insulating layer 031 to no more than 15% simplifies the operation process, thereby saving equipment and process costs.

[0064] For example, in one example, at least some regions in the silicon nitride layer 032 satisfy the following: the percentage of silicon-hydrogen bonds (Si-H bonds) in at least some regions is 0.5% to 7% of the total of Si-N bonds, NH bonds and Si-H bonds. For example, if the content of NH3 in the reaction gas is too low when the silicon nitride layer 032 is fabricated, the percentage of Si-N bonds cannot be ensured.

[0065] For example, in one example, the silicon nitride layer 032 is a single-layer structure. The percentage content of silicon-hydrogen bonds in at least a portion of the silicon nitride layer 032 is positively correlated with the percentage content of silicon-hydrogen bonds in at least a portion of the silicon oxide insulating layer 031. That is, the higher the percentage content of silicon-hydrogen bonds in at least a portion of the silicon nitride layer 032, the higher the percentage content of silicon-hydrogen bonds in at least a portion of the silicon oxide insulating layer 031. The stress difference between the gate 02 and the silicon nitride layer 032 is 400 MPa to 950 MPa. For example, the stress difference between the gate 02 and the silicon nitride layer 032 is 400 MPa, 450 MPa, 500 MPa, 550 MPa, 600 MPa, 650 MPa, 700 MPa, 750 MPa, 800 MPa, 850 MPa, 900 MPa, or 950 MPa, etc. The embodiments of this disclosure do not specifically limit this. For example, through single-layer film testing, the stress of the gate 02 is 150 MPa to 350 MPa, and the stress of the silicon nitride layer 032 is -250 MPa to -850 MPa.

[0066] For example, the stress difference between the silicon nitride layer 032 and the silicon oxide insulating layer 031 is 50 MPa to 400 MPa. For example, the stress difference between the silicon nitride layer 032 and the silicon oxide insulating layer 031 is 50 MPa, 80 MPa, 130 MPa, 150 MPa, 190 MPa, 240 MPa, 300 MPa, 350 MPa, 380 MPa, or 400 MPa. For example, through single-layer film testing, the stress of the silicon oxide insulating layer 031 is -200 MPa to -400 MPa.

[0067] For example, Figure 2 This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, the silicon nitride layer 032 includes a first silicon nitride sublayer 032a and a second silicon nitride sublayer 032b stacked together. The first silicon nitride sublayer 032a is in contact with the silicon oxide insulating layer 031, and the second silicon nitride sublayer 032b is disposed on the side of the first silicon nitride sublayer 032a away from the silicon oxide insulating layer 031 and is in contact with the gate 02. The thickness of the second silicon nitride sublayer 032b is... to The stress of the second silicon nitride sublayer 032b is -400 MPa to -600 MPa, and the stress difference between it and the gate 02 is 670 MPa to 870 MPa; the thickness of the first silicon nitride sublayer 032a is... to The stress of the first silicon nitride sublayer 032a is -400 MPa to -800 MPa, and the stress difference between it and the second silicon nitride sublayer 032b is 0 MPa to 200 MPa, and the stress difference between it and the silicon oxide insulating layer 031 is 50 MPa to 400 MPa, and the stress difference between any two adjacent film layers does not exceed 1000 MPa.

[0068] For example, the second silicon nitride sublayer 032b can act as a buffer layer. The hydrogen content in the first silicon nitride sublayer 032a is less than the hydrogen content in the second silicon nitride sublayer 032b, which can reduce the risk of the gate 02 being oxidized and the risk of the metal oxide semiconductor layer 07 being reduced.

[0069] For example, the stress difference between any two adjacent film layers should not exceed 1000 MPa to ensure that the internal stress is small after annealing and to reduce the risk of warping.

[0070] For example, Figure 3 This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the silicon nitride layer includes a third silicon nitride sublayer 032c, a fourth silicon nitride sublayer 032d, and a fifth silicon nitride sublayer 032e stacked together. The third silicon nitride sublayer 032c is in contact with the oxide insulating layer 031. The fifth silicon nitride sublayer 032e is disposed on the side of the third silicon nitride sublayer 032c away from the oxide insulating layer 031. The fourth silicon nitride sublayer 032d is sandwiched between the third silicon nitride sublayer 032c and the fifth silicon nitride sublayer 032e.

[0071] For example, the fifth silicon nitride sublayer 032e acts as a buffer layer on the side closest to the gate 02, the fourth silicon nitride sublayer 032d is a high-speed deposited silicon nitride layer, and the third silicon nitride sublayer 032c is a low-rate deposited silicon nitride layer.

[0072] For example, the thickness of the fifth silicon nitride sublayer 032e is to Furthermore, the stress of the fifth silicon nitride sublayer 032e is -600 MPa to -1000 MPa; the thickness of the fourth silicon nitride sublayer 032d is... to Furthermore, the stress of the fourth silicon nitride sublayer 032d is 150 MPa to 400 MPa; the thickness of the third silicon nitride sublayer 032c is... to Furthermore, the stress of the third silicon nitride sublayer 032c is between -400 MPa and -800 MPa. The three-layer silicon nitride stack can ensure that the stress difference between any two adjacent film layers does not exceed 1000 MPa, thus ensuring that the internal stress is small after annealing and reducing the risk of warping.

[0073] For example, in one example, the thicknesses of the silicon nitride layer 032 and the silicon oxide insulating layer 031 are d1 and d2, respectively, and the thickness of the gate insulating layer 03 is d, 3500 angstroms < d1 + d2 = d < 5000 angstroms, and 200 angstroms < d2 < 2000 angstroms, 4% < d2 / d < 57%. A ratio of d2 of the silicon oxide insulating layer 031 to d of the gate insulating layer 03 is greater than 4% to ensure the uniformity of each film layer in the entire oxide thin film transistor. If the thickness d2 of the silicon oxide insulating layer 031 is too thin, for example, less than 10 nm, as the interface transition layer between the silicon nitride layer 032 and the metal oxide semiconductor layer 07, the underlying silicon nitride layer 032 may be exposed, causing the silicon nitride layer 032 to contact the metal oxide semiconductor layer 07, which may result in the metal oxide semiconductor layer 07 being reduced. If the thickness d2 of the silicon oxide insulating layer 031 is too large, it will be detrimental to the production capacity and will also lead to a smaller on-state current. The ratio of the thickness d2 of the silicon oxide insulating layer 031 to d of the gate insulating layer 03 within the above range can balance the production capacity and the on-state current Ion, making the on-state current Ion of appropriate magnitude.

[0074] For example, combining Figures 1 to 3 A source electrode 05 and a drain electrode 06, spaced apart from each other, are disposed on the side of the metal oxide semiconductor layer 07 away from the substrate 01. The capacitance between the metal oxide semiconductor layer 07 and the gate electrode 02 is C. When the thin-film transistor is turned on, the current between the source electrode 05 and the drain electrode 06 is I. DS The dielectric constant of the silicon oxide insulating layer 031 is less than that of the metal oxide semiconductor layer 07. The thickness d2 of the silicon oxide insulating layer 032 is related to the current I in the metal oxide semiconductor layer 07. DS The thickness d2 of the silicon oxide insulating layer 032 is inversely proportional to the capacitance C between the metal oxide semiconductor layer 07 and the gate 02.

[0075] For example, I DS =W / L*A / ((d-d2)ε2+d2ε1)(Vgs-Vth-Vds / 2)Vds, d1+d2=d, where d is the total thickness of the gate insulating layer 03, the thickness of the silicon nitride layer 032 is d2, and the thickness of the silicon oxide insulating layer 031 is d1. The smaller d2 is, the greater the current between the source 05 and the drain 06 after the thin-film transistor is turned on. DS The larger.

[0076] For example, the capacitance C = ε0ε1*ε2 / 4πk(d1ε2+d2ε1) = ε0ε1*ε2 / 4πk((d-d2)ε2+d2ε1) = ε0ε1*ε2 / 4πk((dε2+d2(ε1-ε2)), where ε1 is the dielectric constant of SiNx in the silicon nitride layer and ε2 is the dielectric constant of SiOx in the silicon oxide insulating layer; ε1>ε2; the smaller d2 is, the larger the capacitance C is.

[0077] For example, the etching time for the gate insulating layer 03 is: T = d2 / R1 + (d-d2) / R2 = d / R2 + d2(R2-R1) / R2R1, where R1 is the etching rate of the silicon nitride layer, R2 is the etching rate of the silicon oxide insulating layer, and R1 > R2, which satisfies the condition that the smaller d2 is, the larger T is.

[0078] For example, in one instance, the thickness of the metal oxide semiconductor layer 07 is h, and it satisfies 10.8% < d² / d < 11.76% and 3.5% < h / d < 7.4%.

[0079] For example, in another example, the thickness of the metal oxide semiconductor layer is h, and satisfies 21.8% < d² / d < 37% and 2% < h / d < 3.5%.

[0080] For example, in yet another example, the thickness of the metal oxide semiconductor layer is h, and satisfies 21.8% < d² / d < 22.3% and 2.5% < h / d < 2.9%.

[0081] For example, the thickness d2 of the silicon oxide insulating layer 031 satisfies the following range: 200 Å < d2 < 400 Å. Fabricating the silicon oxide insulating layer 031 with a thickness within this range allows for a current I in the metal oxide semiconductor layer to flow smoothly. DS It is relatively large, and can make the capacitance C between the metal oxide semiconductor layer 07 and the gate 02 relatively large.

[0082] For example, Figure 4 This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure, as shown below. Figure 4As shown, the oxide thin film transistor 10 is a bottom-gate thin film transistor. An insulating protective layer 08 is provided on the side of the source electrode 05 and the drain electrode 06 away from the substrate 01. The metal oxide semiconductor layer 07 and the insulating protective layer 08 are in contact in a spaced area between the source electrode 05 and the drain electrode 06. The metal oxide semiconductor layer 07 includes a first surface 071 and a second surface 072 facing each other. The gate insulating layer 02 is in contact with the first surface 071 of the metal oxide semiconductor layer 07, and the insulating protective layer 08 is in contact with the second surface 072 of the metal oxide semiconductor layer 07. The insulating protective layer 08 can prevent external moisture from entering the metal oxide semiconductor layer 07 and affecting the performance of the metal oxide semiconductor layer 07.

[0083] For example, such as Figure 4 As shown, the insulating protective layer 08 includes a first insulating layer 08a and a second insulating layer 08b stacked together. The second insulating layer 08b is located on the side of the first insulating layer 08a closest to the metal oxide semiconductor layer 07 and is in contact with the metal oxide semiconductor layer 07. The first insulating layer 08a is located on the side of the second insulating layer 08b furthest from the metal oxide semiconductor layer 07 and is not in contact with the metal oxide semiconductor layer 07. For example, the material of the first insulating layer 08a includes SiNx, where x is greater than 0; the material of the second insulating layer 08b includes SiOy, where y is greater than 0.

[0084] It should be noted that the density of the first insulating layer 08a refers to the ease with which a liquid or gas can enter the first insulating layer 08a from the outside. The greater the density of the first insulating layer 08a, the more difficult or impossible it is for a liquid or gas to enter the first insulating layer 08a from the outside. Similarly, the density of the second insulating layer 08b refers to the ease with which a liquid or gas can enter the second insulating layer 08b from the outside. The greater the density of the second insulating layer 08b, the more difficult or impossible it is for a liquid or gas to enter the second insulating layer 08b from the outside.

[0085] For example, such as Figure 4 As shown, the metal oxide semiconductor layer 07 includes a first metal oxide semiconductor layer 07a and a second metal oxide semiconductor layer 07b stacked together. The crystallinity of the second metal oxide semiconductor layer 07b is greater than that of the first metal oxide semiconductor layer 07a, and the conductivity of the second metal oxide semiconductor layer 07b is lower than that of the first metal oxide semiconductor layer 07a. Furthermore, the second metal oxide semiconductor layer 07b is further away from the substrate 01 than the first metal oxide semiconductor layer 07a. For example, the first metal oxide semiconductor layer 07a serves as a channel region, and the second metal oxide semiconductor layer 07b can protect the first metal oxide semiconductor layer 07a.

[0086] For example, the material of the first metal oxide semiconductor layer 07a includes at least two of the metal elements indium, gallium, zinc, and tin, and the material of the second metal oxide semiconductor layer 07b includes at least two of the metal elements indium, gallium, zinc, and tin. For example, in one example, the materials of the first metal oxide semiconductor layer 07a and the second metal oxide semiconductor layer 07b can both be indium gallium zinc oxide (IGZO). Depending on the formation conditions in the fabrication process, the second metal oxide semiconductor layer 07b and the first metal oxide semiconductor layer 07a can have different degrees of crystallinity.

[0087] For example, Figure 5 This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure. Figure 5 and Figure 4 The difference is that, Figure 5 The system also includes an electrode layer 09, which can be a common electrode. For example, the material of electrode layer 09 includes indium tin oxide (ITO) or indium zinc oxide (IZO). For instance, when electrode layer 09 is made of ITO, a single-layer film test shows that the stress of electrode layer 09 is between -200 MPa and -400 MPa, and the thickness of the fifth silicon nitride sublayer 032e in contact with electrode layer 09 is... to Furthermore, the stress of the fifth silicon nitride sublayer 032e is -600 MPa to -1000 MPa, which allows the stress difference between the electrode layer 09 and the fifth silicon nitride sublayer 032e to be between 200 MPa and 800 MPa, thus making it less prone to bulging.

[0088] At least one embodiment of this disclosure also provides an electronic device, which includes the oxide thin-film transistor in any of the above embodiments. For example, the electronic device may be a display device or a semiconductor chip. The display device may also be a liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, an X-ray sensor array, or other devices that require thin-film transistors.

[0089] At least one embodiment of this disclosure also provides a method for fabricating an oxide thin-film transistor. The method includes: providing a substrate; forming a gate, a gate insulating layer, and a metal oxide semiconductor layer on the substrate; wherein forming the gate insulating layer includes forming a silicon oxide insulating layer and a silicon nitride layer, the silicon nitride layer being formed on the side of the silicon oxide insulating layer near the gate and in contact with the gate, the silicon oxide insulating layer being formed on the side of the silicon nitride layer near the metal oxide semiconductor layer and in contact with the metal oxide semiconductor layer, and at least a portion of the silicon nitride layer having a region satisfying that: in at least a portion of the region, the percentage of silicon-hydrogen bonds accounting for the sum of Si-N bonds, NH bonds, and Si-H bonds is not greater than 7%.

[0090] For example, Figure 6 The flowchart illustrates a method for fabricating a thin-film transistor according to an embodiment of this disclosure, as follows: Figure 6 As shown, the preparation method includes the following steps:

[0091] S11, Provide a substrate;

[0092] S12. Form a gate on the substrate;

[0093] S13. A silicon oxide insulating layer and a silicon nitride layer are formed on the gate to form a gate insulating layer. The silicon nitride layer is a single-layer structure or includes multiple silicon nitride sub-layers stacked sequentially. The silicon nitride layer is formed on the side of the silicon oxide insulating layer near the gate, and the silicon nitride layer is in contact with the gate.

[0094] S14. A metal oxide semiconductor layer is formed on the gate insulating layer, wherein a silicon oxide insulating layer is formed on the side of the silicon nitride layer close to the metal oxide semiconductor layer, and the silicon oxide insulating layer is in contact with the metal oxide semiconductor layer, wherein at least a portion of the silicon nitride layer satisfies the following condition: the percentage of silicon hydrogen bonds in the sum of Si-N bonds, NH bonds and Si-H bonds in the at least a portion of the region is not greater than 7%.

[0095] For example, the material, thickness, stress, and other characteristics of the gate, silicon oxide insulating layer, and silicon nitride layer forming the gate insulating layer and metal oxide semiconductor layer can be found in the relevant descriptions above, and will not be repeated here.

[0096] For example, the silicon nitride layer is a single-layer structure, and the etching rate for wet etching of the silicon nitride layer is... to For example, the etching rate is or The relevant characteristics of this single-layer silicon nitride layer can be found in the descriptions above, and will not be repeated here.

[0097] For example, the etching solution used to etch the silicon nitride layer is a mixture of NH3F and HF, in which the mass percentages of NH3F and HF are 29.8% to 30.2% and 5.9% to 6.1%, respectively. For example, the remaining component in the etching solution can be deionized water.

[0098] For example, in Figure 6 Based on the flowchart shown, the fabrication method further includes: applying a metal electrode thin film on the side of the metal oxide semiconductor layer away from the substrate, and performing a patterning process on the metal electrode thin film to form mutually spaced source and drain electrodes, and forming an insulating protective layer on the side of the source and drain electrodes away from the substrate, wherein the metal oxide semiconductor layer and the insulating protective layer are in contact in the spaced area between the source and drain electrodes.

[0099] For example, the relevant descriptions of the source, drain, and insulating protective layer can be found in the descriptions above, and will not be repeated here.

[0100] For example, when the metal oxide semiconductor layer is a stacked bilayer structure, forming the metal oxide semiconductor layer includes: applying a first metal oxide semiconductor layer thin film and performing a patterning process to form the first metal oxide semiconductor layer; applying a second metal oxide semiconductor layer thin film on the first metal oxide semiconductor layer and performing a patterning process to form the second metal oxide semiconductor layer; and the density of the second metal oxide semiconductor layer is greater than the density of the first metal oxide semiconductor layer.

[0101] For example, the silicon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer stacked together. The first silicon nitride sublayer is in contact with a silicon oxide insulating layer, and the second silicon nitride sublayer is disposed on the side of the first silicon nitride sublayer away from the silicon oxide insulating layer and in contact with a gate.

[0102] For example, the thickness of the second silicon nitride sublayer is to The stress of the second silicon nitride sublayer is -400 MPa to -600 MPa, and the stress difference between the second silicon nitride sublayer and the gate is 670 MPa to 870 MPa; the thickness of the first silicon nitride sublayer is... to The stress of the first silicon nitride sublayer is -400 MPa to -800 MPa, and the stress difference between it and the second silicon nitride sublayer is 0 MPa to 200 MPa. The stress difference between it and the silicon oxide insulating layer is 50 MPa to 400 MPa, and the stress difference between any adjacent film layers does not exceed 1000 MPa.

[0103] For example, the silicon nitride layer may include a third silicon nitride sublayer, a fourth silicon nitride sublayer, and a fifth silicon nitride sublayer stacked together. The third silicon nitride sublayer is in contact with the silicon oxide insulating layer, the fifth silicon nitride sublayer is disposed on the side of the third silicon nitride sublayer away from the silicon oxide insulating layer, and the fourth silicon nitride sublayer is sandwiched between the third and fifth silicon nitride sublayers. For example, the thickness of the fifth silicon nitride sublayer is... to Furthermore, the stress of the fifth silicon nitride sublayer is -600 MPa to -1000 MPa; the thickness of the fourth silicon nitride sublayer is... to Furthermore, the stress of the fourth silicon nitride sublayer is 150 MPa to 400 MPa; the thickness of the third silicon nitride sublayer is... to Furthermore, the stress of the third silicon nitride sublayer is -400 MPa to -800 MPa.

[0104] At least one embodiment of this disclosure also provides an oxide thin-film transistor, for example, Figure 7 This is a schematic cross-sectional view of another oxide thin-film transistor provided in an embodiment of the present disclosure, as shown below. Figure 7 As shown, the oxide thin-film transistor 20 includes: a gate 22, a gate insulating layer 23, and a metal oxide semiconductor layer 24 stacked on a substrate 21. The gate insulating layer 23 includes a first gate insulating layer 231 and a second gate insulating layer 232 stacked on top of each other. The first gate insulating layer 231 is located between the gate 22 and the second gate insulating layer 232, and the material of the first gate insulating layer 231 includes Si and N elements. The second gate insulating layer 232 is located between the metal oxide semiconductor layer 24 and the first gate insulating layer 231, and the material of the second gate insulating layer 232 includes Si and O elements. Elements; the second gate insulating layer 232 is on the side of the first gate insulating layer 231 close to the metal oxide semiconductor layer 24 and in contact with the metal oxide semiconductor layer 24, and the first gate insulating layer 231 is on the side of the second gate insulating layer 232 away from the metal oxide semiconductor layer 24 and is not in contact with the metal oxide semiconductor layer 24; the thicknesses of the first gate insulating layer 231 and the second gate insulating layer 232 are d1 and d2, respectively, and the thickness of the gate insulating layer 23 is d, 3500 angstroms < d1 + d2 = d < 5000 angstroms, and 200 angstroms < d2 < 2000 angstroms, 4% < d2 / d < 57%.

[0105] For example, the first gate insulating layer 231 is a silicon nitride layer, and the second gate insulating layer 232 is a silicon oxide insulating layer.

[0106] For example, a ratio of the thickness d2 of the silicon oxide insulating layer 231 to the thickness d of the gate insulating layer 23 greater than 4% can ensure the uniformity of each film layer in the entire oxide thin film transistor. If the thickness d2 of the silicon oxide insulating layer 231 is too thin, for example, less than 10 nm, as the interface transition layer between the silicon nitride layer 232 and the metal oxide semiconductor layer 24, there may be a possibility that the underlying silicon nitride layer 232 is exposed, which would cause the silicon nitride layer 232 and the metal oxide semiconductor layer 24 to come into contact, making the metal oxide semiconductor layer 24 at risk of being reduced. If the thickness d2 of the silicon oxide insulating layer 231 is too large, it is not conducive to power production and will also lead to a small on-state current. The ratio of the thickness d2 of the silicon oxide insulating layer 231 to the thickness d of the gate insulating layer 23 within the above range can balance power production and on-state current Ion, making the on-state current Ion of appropriate magnitude.

[0107] For example, at least some regions in the first gate insulating layer 231 satisfy the following condition: the percentage of silicon-hydrogen bonds (Si-H bonds) in at least some regions is no more than 7% of the total percentage of silicon-nitrogen bonds (Si-N bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds). Since the chemical bonding strength of Si-H bonds is lower than that of Si-N bonds, and the bonding strength between Si-H bonds and Cu metal is weaker than that between Si-N bonds and copper metal, subsequent high-temperature annealing allows H atoms to detach and escape more easily than O atoms. If the percentage of silicon-hydrogen bonds (Si-H bonds) in the total number of silicon-nitrogen bonds (Si-N bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds) is greater than 7%, more hydrogen will escape during subsequent annealing, resulting in weaker bonding and adhesion between adjacent film layers. This increases the probability of bulging between film layers. Controlling the percentage of silicon-hydrogen bonds (Si-H bonds) to no more than 7% simplifies the operation process, thereby saving equipment and process costs.

[0108] For example, at least some regions in the second gate insulating layer 232 satisfy the following: the percentage of silicon-hydrogen bonds (Si-H bonds) in at least some regions is 1%-15% of the total content of silicon-oxygen bonds (Si-O bonds), nitrogen-hydrogen bonds (NH bonds), and silicon-hydrogen bonds (Si-H bonds). This can reduce the amount of H element escaping during subsequent annealing, ensure the bonding and adhesion between adjacent film layers, and reduce the probability of bulging between film layers. In addition, controlling the percentage of silicon-hydrogen bonds (Si-H bonds) in the silicon oxide insulating layer 231 to no more than 15% simplifies the operation process, thereby saving equipment and process costs.

[0109] For example, the oxide thin-film transistor also includes a source 25 and a drain 26, wherein the capacitance between the metal oxide semiconductor layer 24 and the gate 22 is C, and the current between the source 25 and the drain 26 after the thin-film transistor is turned on is I. DS The thickness d2 of the second gate insulating layer 232 is related to the current I. DS The second gate insulating layer 232 is a silicon oxide insulating layer, the first gate insulating layer 231 is a silicon nitride layer, and the thickness d2 of the silicon oxide insulating layer is inversely proportional to the capacitance C between the metal oxide semiconductor layer 24 and the gate 22.

[0110] For example, I DS =W / L*A / ((d-d2)ε2+d2ε1)(Vgs-Vth-Vds / 2)Vds, d1+d2=d, where d is the total thickness of the gate insulating layer 23, the thickness of the silicon nitride layer 232 is d2, and the thickness of the silicon oxide insulating layer 231 is d1. The smaller d2 is, the greater the current between the source 25 and the drain 26 after the thin-film transistor is turned on. DS The larger.

[0111] For example, the capacitance C = ε0ε1*ε2 / 4πk(d1ε2+d2ε1) = ε0ε1*ε2 / 4πk((d-d2)ε2+d2ε1) = ε0ε1*ε2 / 4πk((dε2+d2(ε1-ε2)), where ε1 is the dielectric constant of SiNx in the silicon nitride layer and ε2 is the dielectric constant of SiOx in the silicon oxide insulating layer; ε1>ε2; the smaller d2 is, the larger the capacitance C is.

[0112] For example, the etching time for the gate insulating layer 23 is: T = d2 / R1 + (d - d2) / R2 = d / R2 + d2(R2 - R1) / R2R1, where R1 is the etching rate of the silicon nitride layer, R2 is the etching rate of the silicon oxide insulating layer, and R1 > R2, so that the smaller d2 is, the larger T is.

[0113] For example, in one instance, in this oxide thin-film transistor, 5.7% < d² / d < 40%.

[0114] For example, in one example, the thickness of the metal oxide semiconductor layer 24 is h, 10.8% < d2 / d < 11.76%, 3.5% < h / d < 7.4%.

[0115] For example, in one example, the thickness of the metal oxide semiconductor layer 24 is h, 21.8% < d2 / d < 37%, and 2% < h / d < 3.5%.

[0116] For example, in one example, the thickness of the metal oxide semiconductor layer 24 is h, 21.8% < d2 / d < 22.3%, 2.5% < h / d < 2.9%.

[0117] For example, the thickness d2 of the second gate insulating layer 232 satisfies 200 angstroms < d2 < 400 angstroms.

[0118] For example, the thickness d2 of the silicon oxide insulating layer 231 satisfies the following range: 200 Å < d2 < 400 Å. Fabricating the silicon oxide insulating layer 231 with a thickness within this range allows for a current I in the metal oxide semiconductor layer to flow smoothly. DS It is relatively large, and can make the capacitance C between the metal oxide semiconductor layer 24 and the gate 22 relatively large.

[0119] For example, the metal oxide semiconductor layer 24 may include a single-layer structure or a multilayer stacked structure.

[0120] For example, the metal oxide semiconductor layer 24 includes a multilayer stacked structure, the metal oxide semiconductor layer 24 includes a first metal oxide semiconductor layer 241 and a second metal oxide semiconductor layer 242 stacked together, the density of the first metal oxide semiconductor layer 241 is greater than the density of the second metal oxide semiconductor layer 242, and the second metal oxide semiconductor layer 242 is disposed on the side of the first metal oxide semiconductor layer 241 near the substrate 21 and is in contact with the second gate insulating layer 232.

[0121] For example, the material of the metal oxide semiconductor layer 24 includes at least one of indium gallium zinc oxide, Sn-containing indium gallium zinc oxide, and lanthanide metal oxides. For example, in one example, the material of the first metal oxide semiconductor layer 241 and the material of the second metal oxide semiconductor layer 242 can both be indium gallium zinc oxide (IGZO). Depending on the formation conditions in the fabrication process, the second metal oxide semiconductor layer 242 and the first metal oxide semiconductor layer 241 can have different degrees of crystallinity.

[0122] For example, the mobility of the metal oxide semiconductor layer 24 is 5 cm. 2 / v·s up to 50cm 2 / v·s, for example, 5cm 2 / v·s、15cm 2 / v·s、20cm 2 / v·s、25cm 2 / v·s、30cm 2 / v·s、35cm 2 / v·s、40cm 2 / v·s、45cm 2 / v·s or 50cm 2 / v·s.

[0123] For example, the oxide thin film transistor is a bottom-gate thin film transistor. The oxide thin film transistor 20 also includes a passivation layer 27 disposed on the side of the source 25 and drain 26 away from the substrate 21. The metal oxide semiconductor layer 24 includes a first surface 24a and a second surface 24b opposite to each other. The second gate insulating layer 232 is in contact with the first surface 24a of the metal oxide semiconductor layer 24, and the passivation layer 27 is in contact with the second surface 24b of the metal oxide semiconductor layer 24.

[0124] For example, the passivation layer 27 includes a first passivation layer 271 and a second passivation layer 272 stacked together. The material of the first passivation layer 271 includes SiNx and does not include oxygen, where x is greater than 0; the material of the second passivation layer 272 includes SiO. y, where y is greater than 0; the second passivation layer 272 is on the side of the first passivation layer 271 close to the metal oxide semiconductor layer 24 and in contact with the metal oxide semiconductor layer 24, and the first passivation layer 271 is on the side of the second passivation layer 272 away from the oxide semiconductor layer 24 and is not in contact with the metal oxide semiconductor layer 24. This passivation layer 27 can prevent external moisture from entering the metal oxide semiconductor layer 24 and affecting the performance of the metal oxide semiconductor layer 24.

[0125] Where there is no conflict, the embodiments of this disclosure and the features thereof may be combined with each other to obtain new embodiments.

[0126] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An oxide thin-film transistor, comprising: Substrate; A gate and a metal oxide semiconductor layer are sequentially stacked on the substrate. A gate insulating layer is disposed between the metal oxide semiconductor layer and the gate, wherein, The gate insulating layer includes a silicon oxide insulating layer and a silicon nitride layer stacked together. The silicon nitride layer includes a plurality of silicon nitride sub-layers stacked sequentially. The silicon oxide insulating layer is disposed between the silicon nitride layer and the metal oxide semiconductor layer. The silicon nitride layer contains at least some regions that satisfy the following condition: the percentage of Si-H bonds in the total number of Si-N bonds, NH bonds, and Si-H bonds is not greater than 7%. The silicon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer stacked together. The first silicon nitride sublayer is in contact with the silicon oxide insulating layer, and the second silicon nitride sublayer is disposed on the side of the first silicon nitride sublayer away from the silicon oxide insulating layer and in contact with the gate. The hydrogen content in the first silicon nitride sublayer is less than the hydrogen content in the second silicon nitride sublayer.

2. The oxide thin-film transistor according to claim 1, wherein, The silicon nitride layer contains at least some regions that satisfy the following condition: the percentage of Si-H bonds in the total Si-N bonds, NH bonds, and Si-H bonds is 0.5% to 7%.

3. The oxide thin-film transistor according to claim 2, wherein, The thickness of the second silicon nitride sublayer is 2000 Å to 4800 Å, the stress of the second silicon nitride sublayer is -400 MPa to -600 MPa, and the stress difference between the second silicon nitride sublayer and the gate is 670 MPa to 870 MPa; the thickness of the first silicon nitride sublayer is 500 Å to 2000 Å, the stress of the first silicon nitride sublayer is -400 MPa to -800 MPa, and the stress difference between the first silicon nitride sublayer and the second silicon nitride sublayer is 0 MPa to 200 MPa, the stress difference between the first silicon nitride sublayer and the silicon oxide insulating layer is 50 MPa to 400 MPa, and the stress difference between any adjacent film layers does not exceed 1000 MPa.

4. The oxide thin-film transistor according to claim 1, wherein, The thicknesses of the silicon nitride layer and the silicon oxide insulating layer are d1 and d2, respectively, and the thickness of the gate insulating layer is d. 3500 angstroms < d1 + d2 = d < 5000 angstroms, and 200 angstroms < d2 < 2000 angstroms, 4% < d2 / d < 57%.

5. The oxide thin-film transistor according to claim 4, wherein, A source and a drain electrode, spaced apart from each other, are disposed on the side of the metal oxide semiconductor layer away from the substrate. The capacitance between the metal oxide semiconductor layer and the gate electrode is C. When the thin-film transistor is turned on, the current between the source and the drain electrode is I. DS The dielectric constant of the silicon oxide insulating layer is less than that of the metal oxide semiconductor layer, and the thickness d2 of the silicon oxide insulating layer is related to the current I in the metal oxide semiconductor layer. DS The thickness d2 of the silicon oxide insulating layer is inversely proportional to the capacitance C between the metal oxide semiconductor layer and the gate.

6. The oxide thin-film transistor according to claim 4, wherein, The thickness of the metal oxide semiconductor layer is h, and satisfies 10.8% < d² / d < 11.76% and 3.5% < h / d < 7.4%.

7. The oxide thin-film transistor according to claim 4, wherein, The thickness of the metal oxide semiconductor layer is h, and satisfies 21.8% < d² / d < 37% and 2% < h / d < 3.5%.

8. The oxide thin-film transistor according to claim 4, wherein, The thickness of the metal oxide semiconductor layer is h, and satisfies 21.8% < d² / d < 22.3% and 2.5% < h / d < 2.9%.

9. The oxide thin-film transistor according to claim 4, wherein, 200 angstroms < d2 < 400 angstroms.

10. The oxide thin-film transistor according to claim 5, wherein, The oxide thin-film transistor is a bottom-gate thin-film transistor. An insulating protective layer is provided on the side of the source and the drain away from the substrate. The metal oxide semiconductor layer and the insulating protective layer are in contact in the spaced area between the source and the drain. The metal oxide semiconductor layer includes a first surface and a second surface opposite to each other. The gate insulating layer is in contact with the first surface of the metal oxide semiconductor layer, and the insulating protective layer is in contact with the second surface of the metal oxide semiconductor layer.

11. The oxide thin-film transistor according to claim 10, wherein, The insulating protective layer includes a first insulating layer and a second insulating layer stacked together. The second insulating layer is located on the side of the first insulating layer closer to the metal oxide semiconductor layer and is in contact with the metal oxide semiconductor layer. The first insulating layer is located on the side of the second insulating layer away from the metal oxide semiconductor layer and is not in contact with the metal oxide semiconductor layer. The material of the first insulating layer includes SiN x Where x is greater than 0; the material of the second insulating layer includes SiO2. y , where y is greater than 0.

12. The oxide thin-film transistor according to any one of claims 1 to 11, wherein, The metal oxide semiconductor layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer stacked together. The crystallinity of the second metal oxide semiconductor layer is greater than that of the first metal oxide semiconductor layer, and the conductivity of the second metal oxide semiconductor layer is lower than that of the first metal oxide semiconductor layer. Furthermore, the second metal oxide semiconductor layer is further away from the substrate relative to the first metal oxide semiconductor layer.

13. The oxide thin-film transistor according to claim 12, wherein, The material of the first metal oxide semiconductor layer includes at least two of the following metal elements: indium, gallium, zinc, and tin. The material of the second metal oxide semiconductor layer includes at least two of the following metal elements: indium, gallium, zinc, and tin.

14. The oxide thin-film transistor according to claim 1, wherein, The gate is made of at least one of the metal elements molybdenum, aluminum, and copper, and the gate has a thickness of 1,000 Å to 10,000 Å.

15. An electronic device comprising an oxide thin-film transistor according to any one of claims 1 to 14.

16. A method for fabricating an oxide thin-film transistor, comprising: Provide substrates; A gate, a gate insulating layer, and a metal oxide semiconductor layer are formed on the substrate; wherein... Forming the gate insulating layer includes forming a silicon oxide insulating layer and a silicon nitride layer. The silicon nitride layer includes a plurality of silicon nitride sub-layers stacked sequentially. The silicon nitride layer is formed on the side of the silicon oxide insulating layer near the gate and is in contact with the gate. The silicon oxide insulating layer is formed on the side of the silicon nitride layer near the metal oxide semiconductor layer and is in contact with the metal oxide semiconductor layer. At least a portion of the silicon nitride layer satisfies the following condition: the percentage of Si-H bonds in the total number of Si-N bonds, NH bonds, and Si-H bonds is not greater than 7%. The silicon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer stacked together. The first silicon nitride sublayer is in contact with the silicon oxide insulating layer, and the second silicon nitride sublayer is disposed on the side of the first silicon nitride sublayer away from the silicon oxide insulating layer and in contact with the gate. The hydrogen content in the first silicon nitride sublayer is less than the hydrogen content in the second silicon nitride sublayer.

17. The preparation method according to claim 16, wherein, The silicon nitride layer is a single-layer structure, and the etching rate of the silicon nitride layer by wet etching is 20 Å / s to 30 Å / s.

18. The preparation method according to claim 17, wherein, The etching solution used to etch the silicon nitride layer is a mixture of NH3F and HF, wherein the mass percentages of NH3F and HF in the mixture are 29.8% to 30.2% and 5.9% to 6.1%, respectively.

19. The preparation method according to claim 16, further comprising: A metal electrode film is applied to the side of the metal oxide semiconductor layer away from the substrate, and the metal electrode film is patterned to form mutually spaced source and drain electrodes. An insulating protective layer is formed on the side of the source and drain electrodes away from the substrate, wherein the metal oxide semiconductor layer and the insulating protective layer are in contact in the spaced region between the source and drain electrodes.

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