Lateral bipolar transistor structure with inner and outer spacers and its formation method

Abstract

Embodiments of this disclosure provide a lateral bipolar junction transistor (BJT) structure with inner and outer spacers and related methods. The BJT structure may have an emitter / collector (E / C) layer located above an insulator. The E / C layer has a first doping type. A first base layer is located on the insulator and adjacent to the E / C layer. The first base layer has a second doping type opposite to the first doping type. A second base layer is located on the first base layer and has the second doping type. The doping concentration of the second base layer is greater than that of the first base layer. An inner spacer is located on the E / C layer and adjacent to the second base layer. An outer spacer is located on the E / C layer and adjacent to the inner spacer.

Description

Technical Field

[0001] This disclosure relates to bipolar transistors. Background Technology

[0002] This disclosure relates to bipolar transistors. Current technology is an atomic-scale scaling of certain miniature devices such as logic gates, bipolar transistors, field-effect transistors (FETs), and capacitors. Circuit chips containing millions of such devices are common. The structure of a bipolar transistor defines several characteristics during operation. Conventional integrated circuits may employ vertical bipolar transistors or other types of bipolar transistors, but these types of devices may have higher costs and / or fail to meet certain required operating parameters. Improving the electrical behavior of bipolar transistors can provide relevant improvements to the device. Summary of the Invention

[0003] The illustrative aspects of this disclosure are designed to address the problems described herein and / or other problems not discussed herein.

[0004] Embodiments of this disclosure provide a lateral bipolar transistor structure, comprising: an emitter / collector (E / C) layer located above an insulator, the E / C layer having a first doping type; a first base layer located on the insulator and adjacent to the E / C layer, wherein the first base layer has a second doping type opposite to the first doping type; a second base layer located on the first base layer and having the second doping type, wherein the doping concentration of the second base layer is greater than the doping concentration of the first base layer; an inner spacer located on the E / C layer and adjacent to the second base layer; and an outer spacer located on the E / C layer and adjacent to the inner spacer.

[0005] Other embodiments of this disclosure provide a lateral bipolar transistor structure, comprising: an emitter / collector (E / C) layer above an insulator, the E / C layer having a first doping type; a first base layer located on the insulator and adjacent to the E / C layer, wherein the first base layer has a second doping type opposite to the first doping type; a second base layer located on the first base layer and having the second doping type, wherein the doping concentration of the second base layer is greater than the doping concentration of the first base layer, the second base layer comprising: a lower portion having a first horizontal width relative to the inner spacer, and an upper portion having a second horizontal width relative to the inner spacer that is greater than the first horizontal width; an inner spacer located on the E / C layer and adjacent to the second base layer; and an outer spacer located on the E / C layer and adjacent to the inner spacer.

[0006] Another aspect of this disclosure provides a method for forming a lateral bipolar transistor structure, the method comprising: forming an emitter / collector (E / C) layer over an insulator, the E / C layer having a first doping type; forming a first base layer on the insulator and adjacent to the E / C layer, wherein the first base layer has a second doping type opposite to the first doping type; forming a second base layer on the first base layer and having the second doping type, wherein the doping concentration of the second base layer is greater than the doping concentration of the first base layer; forming an inner spacer on the E / C layer and adjacent to the second base layer; and forming an outer spacer on the E / C layer and adjacent to the inner spacer. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of various aspects of the present disclosure in conjunction with the accompanying drawings depicting various embodiments thereof, wherein:

[0008] Figure 1 A cross-sectional view of the initial structure to be processed according to an embodiment of the present disclosure is provided.

[0009] Figure 2 A cross-sectional view of a base structure formed according to an embodiment of the present disclosure is provided.

[0010] Figure 3 A cross-sectional view of a nitride cap formed on a base structure according to an embodiment of the present disclosure is provided.

[0011] Figure 4 A cross-sectional view of the formation of the base layer according to an embodiment of the present disclosure is provided.

[0012] Figure 5 A cross-sectional view of the formation of the E / C layer according to an embodiment of the present disclosure is provided.

[0013] Figure 6 A cross-sectional view of the formation of an inter-layer dielectric (ILD) layer according to an embodiment of the present disclosure is provided.

[0014] Figure 7 A cross-sectional view of an opening formed above the base layer according to an embodiment of the present disclosure is provided.

[0015] Figure 8 A cross-sectional view of the formation of an external base according to an embodiment of the present disclosure is provided.

[0016] Figure 9 A cross-sectional view of a contact formed into a lateral bipolar transistor structure according to an embodiment of the present disclosure is provided.

[0017] Figure 10A cross-sectional view of an inner spacer having vertically tapered sidewalls is provided according to an embodiment of the present disclosure.

[0018] Figure 11 A cross-sectional view of an outer base electrode formed adjacent to a vertical conical sidewall according to an embodiment of the present disclosure is provided.

[0019] Figure 12 A cross-sectional view of a lateral bipolar transistor structure and an inner spacer having vertical tapered sidewalls, according to embodiments of the present disclosure, is provided.

[0020] Figure 13 A cross-sectional view of a set of inner spacers recessed according to an embodiment of the present disclosure is provided.

[0021] Figure 14 A cross-sectional view of a T-shaped outer base according to an embodiment of the present disclosure is provided.

[0022] Figure 15 A cross-sectional view of a lateral bipolar transistor structure with a T-shaped external base according to an embodiment of the present disclosure is provided.

[0023] Please note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0024] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0025] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0026] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of " / ", "and / or", and "at least one" in cases such as "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0027] Embodiments of this disclosure provide a lateral bipolar transistor structure with inner and outer spacers. The lateral bipolar transistor structure may include an emitter / collector (E / C) layer of semiconductor material located above an insulator. The E / C layer may have a first doping type, such as P-type or N-type. A first base layer with a doping type opposite to that of the E / C layer is located on the insulator and adjacent to the E / C layer. A second base layer with the same doping type as the first base layer is located on the first base layer. The second base layer has a higher doping concentration than the first base layer, thus defining the extrinsic base of the lateral bipolar transistor structure. The inner spacer is located on the E / C layer and adjacent to the second base layer, and the outer spacer is located on the E / C layer and adjacent to the inner spacer. In this configuration, the horizontal width of the first and second base layers may be significantly smaller than in other types of lateral bipolar transistor structures.

[0028] Bipolar junction transistor (BJT) structures, such as those in the embodiments of this disclosure, operate using multiple "PN junctions." The term "PN" refers to two adjacent materials with different conductivity types (i.e., P-type and N-type), the conductivity type being induced by dopants within the adjacent materials. When formed in a device, a PN junction can function as a diode. A diode is a two-terminal device that behaves differently from the conductive or insulating materials between two electrical contacts. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the "forward" direction), but provides almost no conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a PN junction, the orientation of the diode in the forward and reverse directions depends on the type and magnitude of the bias applied to the material composition of one or both terminals, which affects the size of the barrier. In the case of a junction between two semiconductor materials, the barrier will form along the interface between the two semiconductor materials.

[0029] refer to Figure 1 This document illustrates a preliminary structure 100 (hereinafter referred to as the "structure") suitable for forming a lateral bipolar transistor structure according to embodiments of the present disclosure. The preliminary structure 100 may be processed as described herein to produce one or more lateral bipolar transistor structures. However, it should be understood that in other embodiments, other techniques, process sequences, etc., may be implemented to produce the same or similar bipolar transistor structures. Figure 1 A cross-sectional view of a structure 100 having a substrate 102 comprising, for example, one or more semiconductor materials is shown. The substrate 102 may include, but is not limited to, silicon, germanium, silicon germanium (SiGe), silicon carbide, or any other common IC semiconductor substrate. In the case of SiGe, the germanium concentration in the substrate 102 may differ from other SiGe-based structures described herein. A portion or all of the substrate 102 may be strained. For example, a doped well region 104 may be included on or within the substrate 102 to achieve electrical bias for structures or components formed above the substrate 102. The doped well region 104 may have the same dopant type as the substrate 102 (e.g., p-type doping), but may have a higher doping concentration.

[0030] Structure 100 may include embedded elements for electrically separating the active material formed over substrate 102 from other regions and / or materials. Optionally, insulator 106 may be formed over doped well region 104 and substrate 102, for example by forming a dielectric material (e.g., oxide or nitride insulating material) layer to convert the silicon material within substrate 102 or doped well region 104 into a higher resistivity material, such as polycrystalline silicon or amorphous silicon (poly-Si), or by other techniques.

[0031] Semiconductor layer 108 and doped semiconductor layer 110 may be located on insulator 106 and may comprise any currently known or later developed semiconductor material (e.g., any semiconductor material described herein with respect to substrate 102). Semiconductor layer 108 and / or doped semiconductor layer 110 may be formed by deposition and / or epitaxial growth of silicon and / or other semiconductor materials on insulator 106 and may have a predetermined doping type, such as by in-situ doping or doping during the formation of doped semiconductor layer 110. In some cases, semiconductor layer 108 may comprise silicon (e.g., polycrystalline silicon), while doped semiconductor layer 110 may comprise silicon germanium (SiGe). According to one example, semiconductor layer 108 may be undoped or only lightly doped, while doped semiconductor layer 110 may be a more heavily doped N-type to provide an active semiconductor material for the base terminal of the final lateral bipolar transistor structure.

[0032] Insulator 106 may extend horizontally throughout structure 100 and / or may be selectively formed below the location where active material is formed, examples of which are discussed elsewhere herein. In other embodiments, insulator 106 may include oxygen doping to form a dielectric insulator or buried oxide (“BOX”) layer over substrate 102 to electrically isolate semiconductor layer 108 from substrate 102. Insulator 106 may therefore include other elements or molecules, such as Ge, N, or Si. Regardless of the specific embodiment, the dimensions of insulator 106 may be as narrow as possible to provide better interaction with the overlying semiconductor material (e.g., semiconductor layer 108, doped semiconductor layer 110, and components formed thereon or by means thereto). In various embodiments, insulator 106 may have a thickness of up to about 25 nanometers (nm) to about 500 nm. Some portions of substrate 102 (not shown) may not have insulator 106 above them, and / or multiple layers of insulator 106 may be formed on substrate 102 at varying thicknesses. In addition, various conductive particles (“dopants”) can be introduced into the substrate 102 through a process known as “pre-doping” of the substrate 102.

[0033] Structure 100 ( Figure 1The bipolar transistor structure may include a set of trench isolations (TIs) 112. One or more TIs 112 can be fabricated by forming and filling trenches (not labeled) with an insulating material such as oxides. One or more TIs 112 horizontally isolate the insulator 106, semiconductor layer 108, and doped semiconductor layer 110 from any adjacent material regions. Various portions of the bipolar transistor structure, including its active semiconductor material and / or other devices (if applicable), may be formed on or by portions of the insulator 106 and the doped semiconductor layer 110 isolated by one or more TIs 112. According to one example, two TIs 112 are formed, with the insulator 106, semiconductor layer 108, and doped semiconductor layer 110 horizontally positioned between the two TIs 112. One or more TIs 112 may be formed before the active material is formed over the substrate 102, but this is not always necessary in all embodiments.

[0034] Each TI 112 can be formed from any currently known or later developed material for providing electrical insulation, such as: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon carbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) comprising atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or layers thereof. One or more TI 112 and doped semiconductor layers 110 can be planarized (e.g., by chemical mechanical planarization or other techniques) such that one or more of their upper surfaces are substantially coplanar with each other.

[0035] Figure 2An embodiment of the present disclosure illustrates the formation of a base assembly 120 on a doped semiconductor layer 110, for example, to allow subsequent or independent processing of the doped semiconductor layer 110. The formation of the base assembly 120 may include forming an insulating liner 122 on a portion of the semiconductor layer 110, and forming a polycrystalline semiconductor 124 (e.g., polycrystalline Si) on the insulating liner 122. The polycrystalline semiconductor 124 may not form part of the final bipolar transistor structure and may be formed as a placeholder material within the base assembly 120 for later removal and replacement with other active and / or insulating materials. Furthermore, embodiments of the present disclosure may include forming a first spacer layer 126 on the outer surface of the insulating liner 122 and / or the polycrystalline semiconductor 124. The first spacer layer 126 may be provided as one or more insulating material bodies formed on the upper surface of a material, for example by deposition, thermal growth, etc., to electrically and physically insulate the material subsequently formed on the covered material from other components. According to one example, the first spacer layer 126 may have one or more oxide insulating materials (e.g., SiO2) formed to a desired thickness. In this case, the first spacer layer 126 may alternatively be formed, for example, by oxidizing the exposed outer surface of the polycrystalline semiconductor 124 to transform its material composition into an oxide insulator (e.g., from polycrystalline Si to silicon dioxide (SiO2) or other semiconductor oxides).

[0036] Figure 3 A second spacer layer 128 is shown formed on a portion of the first spacer layer 126 and the doped semiconductor layer 110 beneath it. The second spacer layer 128 may be formed to approximately the same thickness as the first spacer layer 126, or any other desired thickness. However, the second spacer layer 128 may include an insulating material layer different from the first spacer layer 126. For example, if the first spacer layer 126 comprises an oxide insulator, the second spacer layer 128 may comprise one or more nitride insulators (e.g., SiN). These two spacer layers may cooperate to limit the horizontal width of any subsequently active semiconductor material formed by replacing the polycrystalline semiconductor 124 in subsequent processing. Furthermore, as discussed elsewhere herein, one or both of spacer layers 126 and 128 may be processed as inner and outer spacers for physical and electrical isolation of the emitter, base, and collector terminals of a lateral bipolar transistor.

[0037] Now for reference Figure 4 Embodiments of this disclosure may include using spacer layers 126, 128 as a mask to remove portions of the doped semiconductor layer 110. Figure 1-3The first base layer 130 is formed as the remaining portion of the doped semiconductor layer 110. Local removal of the doped semiconductor layer 110 may, for example, include applying a predetermined amount of wet etchant and / or other etch compounds selective to the composition of the doped semiconductor layer 110 (e.g., SiGe). Such compounds may include, for example, hydrofluoric acid (HF), peroxy acid, and / or other currently known or later developed wet or selective etchants. Such etchants may not remove any significant amount of the semiconductor layer 108, thus preserving the original shape and dimensions of the insulator 106 and the semiconductor layer 108. The amount of etchant can be controlled such that a portion of the doped semiconductor layer 110 remains intact below the base assembly 120 as the first base layer 130. Furthermore, the area where the doped semiconductor layer 110 is removed may horizontally define a set of openings 132 between the first base layer 130 and one or more Ti 112s. The openings 132 can provide unused space in which active material for a bipolar transistor structure will be formed in subsequent processing.

[0038] Turn now Figure 5 Further processing may include forming a set of emitter / collector (E / C) layers 140 on semiconductor layer 108 and horizontally between the first base layer 130 and one or more Ti 112. E / C layers 140 may define all or part of the active bipolar transistor material for the emitter and collector terminals of the bipolar transistor structure. E / C layers 140 may be formed, for example, on a corresponding portion of semiconductor layer 108 by epitaxial growth or deposition of doped semiconductor material. E / C layers 140 may include the same material composition as the first base layer 108 (e.g., doped SiGe), but with the opposite doping type (e.g., when the first base layer 108 is P-type doped, they may be N-type doped, and vice versa). E / C layers 140 may additionally or alternatively include other electroactive semiconductor materials. E / C layers 140 may be formed over semiconductor layer 108 to a desired thickness. When the E / C layers 140 are formed by epitaxial growth, they can extend to a height H1 above the semiconductor layer 108, which is greater than the height H2 of the first base layer 130 above the semiconductor layer 108. In this case, spacers 126, 128 can horizontally separate each E / C layer 140 from the polycrystalline semiconductor 124 of the base assembly 120.

[0039] In some cases, the formation of the E / C layer 140 may cause dopants from the newly formed E / C layer 140 to migrate into the first base layer 130. This migration may be partly caused by a higher dopant concentration in one or more E / C layers 140 than in the first base layer 130. In this case, the geometry of the first base layer 130 may be horizontally recessed inward to further reduce the horizontal thickness of the first base layer 130 adjacent to the E / C layer 140. For example, the sidewalls of the first base layer 130 may have a concave profile (i.e., it has an hourglass shape) due to the migration of opposite types of dopants into the first base layer 130.

[0040] Figure 5 It is also shown that a set of E / C silicide layers 141 are formed on one or more E / C layers 140. E / C silicide layers 151 can be formed to enhance the conductivity between the E / C layer 140 and the conductors formed thereon. Silicide layers 141 can be formed by forming a conductive metal (e.g., cobalt, titanium, nickel, platinum, or other materials) on the layer 140, annealing the metal to produce a conductive silicide material (e.g., cobalt silicide, titanium silicide, etc.) on the upper surface of the layer 140, and removing excess conductive metal. Silicide layers 141 can be formed to allow stronger electrical coupling to overlying contacts.

[0041] Turn now Figure 6 Further processing of the structure may include further modification of the base assembly 120 to form additional active material. Here, the interlayer dielectric (ILD) layer 142 may be formed over one or more TI 112, polycrystalline semiconductor 124, one or more E / C layers 140, etc., by depositing insulating material on the structure or forming insulating material using other techniques. Additional metallization layers (not shown) may be formed in the ILD layer 142 during subsequent processing during mid-stage and / or back-end processes. The ILD layer 142 may include any currently known or later developed insulating layers, such as those included within insulator 106 and / or one or more TI 112. Although the ILD layer 142 may have a similar or identical composition to these materials, it is formed separately from other insulating materials, and physical boundaries and / or interfaces between the ILD layer 142 and these other materials may exist in the structure.

[0042] With ILD layer 142 in place, further processing may include connecting ILD layer 142 with spacer layers 126, 128 ( Figure 2-5The spacers 126, 128, and ILD layer 142 are planarized together to form an inner spacer 144 adjacent to the polycrystalline semiconductor 124 and an outer spacer 146 adjacent to the inner spacer 146. The planarization of spacer layers 126, 128, and ILD layer 142 can be achieved, for example, using chemical mechanical planarization (CMP) or other processes operable for planarizing the upper surface of a structure to give it a single horizontal upper surface. Any one or more remaining portions of the first spacer layer 126 may define the inner spacer 144, and thus the inner spacer 144 may have the same composition as the first spacer layer 126, as described elsewhere herein. Any one or more remaining portions of the second spacer layer 128 may define the outer spacer 146, and thus may have the same composition as the second spacer layer 128. In one example, the inner spacer 144 may include an oxide insulator, while the outer spacer 146 may include a nitride insulator.

[0043] Turn now Figure 7 Subsequent processing can replace polycrystalline semiconductor 124 with various active materials for the base terminals of the final lateral bipolar transistor. Figure 2-6 Here, the polycrystalline semiconductor 124 can be removed (e.g., by selective etching with a wet etchant and / or similar materials) without affecting the ILD layer 142 or spacers 144, 146 to form an opening 148 over the first base layer 130. The opening 148 may be adjacent to one or more corresponding layers of the inner spacers 144, and in some cases may be horizontally located between one or more corresponding layers of the inner spacers 144. The opening 148 may have substantially the same horizontal width as the polycrystalline semiconductor 124, thus defining the size and shape of any alternative material formed therein. Furthermore, the formation of the opening 148 may remove a portion of the insulating liner 122 to expose the first base layer 130.

[0044] Figure 8 This illustrates the formation of additional doped semiconductor material on the first base layer 130 to define the remainder of the base terminal. This can be achieved by creating an opening 148 (…). Figure 7 The second base layer 150 is formed by depositing and / or epitaxially growing silicon germanium (SiGe) and / or other semiconductor materials within the first base layer 130. The second base layer 150 may optionally have the same doping type as the first base layer 130 (e.g., both may be doped p-type). The second base layer 150 may be formed, for example, by selectively growing silicon material over the first base layer 130. The second base layer 150 may have a higher doping concentration than the first base layer 130 or the semiconductor layer 108 (which is electrically inert). Furthermore, the width of the second base layer 150 may be approximately equal to the width of the previously removed polycrystalline semiconductor 124. Figure 2-6 The width of the second base layer 150 is greater than that of the first base layer 130, and in some cases, the second base layer 150 may have a smaller horizontal width than the first base layer 130.

[0045] In the final lateral bipolar junction transistor (TLB) structure, the first base layer 130 may define a lightly doped inner base region, while the second base layer 150 may define a heavily doped outer base region of the transistor. In some cases, the first base layer 130 may be adjacent only to one or more E / C layers 140, and the second base layer 150 may be adjacent only to one or more inner spacers 144. The higher doping concentration in the second base layer 150 can increase the conductivity between the second base layer 150 and any overlying contacts to control the current flow through the TLB structure. Additionally, the base silicide layer 151 can be formed on the second base layer 150 in substantially the same manner as the E / C silicide layer 141, such as... Figure 8 And what is discussed elsewhere in this article.

[0046] refer to Figure 9 Subsequent processing may include forming an additional ILD layer 152 on ILD layer 142 to make the previously discussed active semiconductor material electrically insulated from the overlying structure and / or wire. In some cases, the additional ILD layer 152 may be continuous with ILD layer 142, so that no physical interface is visible between layers 142, 152. To electrically couple E / C layer 140 to the overlying layer and / or structure, a set of E / C contacts 154 to E / C layer 140 (e.g., via E / C silicide layer 141) may be formed within one or more ILD layers 142, 152. Similarly, a set of base contacts 156 may be formed on second base layer 150 (e.g., via E / C silicide layer 141) within one or more ILD layers 142, 152.

[0047] Embodiments of this disclosure provide a lateral bipolar transistor structure 160, wherein a second base layer 150 is situated on a first base layer 130 and adjacent to inner and outer spacers 146, 144. The second base layer 150 is formed adjacent to and / or between inner spacers 144, wherein one or more outer spacers 146 are adjacent to one or more inner spacers 144. This limits the horizontal width of the second base layer 150, i.e., it cannot be wider than the first base layer 130 beneath it. This reduction in size can contribute to the speed and reliability of the bipolar transistor structure 160, while also allowing it to be formed within a smaller surface area than conventional bipolar transistor structures. Furthermore, one or more E / C layers 140 may be partially located beneath the outer spacers 146, or even partially beneath the inner spacers 144 at their interface with the first base layer 130. In this configuration, the second base layer 150 can still have a higher doping concentration than the first base layer 130, thus defining an outer base region and an inner base region within the second base layer 150 and the first base layer 130, respectively. Furthermore, the position and size of the inner spacer 144 and the outer spacer 146 prevent electrical paths from forming directly between one or more E / C layers 140 and the second base layer 150.

[0048] In the lateral bipolar junction transistor (BJT) structure 160, the E / C layer 140 may include a lower portion 140a adjacent to the first base layer 130 and an upper portion 140b adjacent to the outer spacers 146. Due to the presence of the upper portion 140b, the E / C layer 140 may have a height H1 above the semiconductor layer 108, which is greater than the height H2 of the first base layer 130 above the semiconductor layer 108. Therefore, the E / C layer 140 may be higher than the first base layer 130, even if the height H1 of the E / C layer 140 above the semiconductor layer 108 is not greater than the combined height of the first and second base layers 130, 150 above the semiconductor layer 108. In some regions of the upper portion 140b, the inner and outer spacers 146, 146 may be made of only material horizontally located between the E / C layer 140 and the second base layer 150. To provide this configuration, the inner spacer 144 and / or the outer spacer 146 may have a substantially uniform horizontal width between the second base layer 150 and the outer spacer 146 (i.e., they may be substantially rectangular).

[0049] Turning Figure 10 And refer to Figure 7 According to another method of this disclosure, a structure having, for example, different from the outer spacer 146 can be produced. Figure 8 Non-rectangular shapes, non-uniform widths, and / or other contours of spacers. For example, such as... Figure 10 As shown, embodiments of this disclosure may include removing a portion of the internal spacer 144. Figure 7A chamfered inner spacer 164 is formed within the opening 148. To remove part of the inner spacer 144, a mask 166 may be formed on the ILD layer 142, and the outer spacer 146 and / or the inner spacer 144 may be contacted with an etchant selective to its composition (e.g., an oxide-selective etchant). When such an etchant and / or other removal techniques are applied from above the inner spacer 144, less spacer material will be removed in the lower portion of the opening 148 than in the upper portion. The resulting chamfered inner spacer 164 may be thinnest at its upper surface and thickest at its lower surface, such that the chamfered inner spacer 164 includes a vertically tapered sidewall adjacent to the opening 148 and a non-tapered sidewall adjacent to the outer spacer 146.

[0050] Advance to Figure 11 and 12 The additional processing is shown in a cross-sectional view. Figure 11 The formation of the second spacer layer 150 and the base silicide 151 is shown. Figure 12 The remaining portion forming the lateral bipolar transistor 160 is shown. At this stage, mask 166 can be removed. Figure 10 The process continues in substantially the same manner as other embodiments, but the inner spacer 144 is modified to a chamfered inner spacer 164. In this case, the second base layer 150 can be horizontally widest at its upper surface below the base silicide 151 and horizontally thinnest at its interface with the first base layer 130. That is, the width of the second base layer 150 can gradually increase relative to its height above the first base layer 130. In the lateral bipolar transistor structure 160, the chamfered inner spacer 164 can also substantially retain the vertical tapered sidewalls adjacent to the second base layer 150 and the non-tapered sidewalls adjacent to the outer spacer 164. Among other things, the use of the chamfered inner spacer 164 also allows for stronger conductivity between the base contact and the second base layer 150 through the base silicide 151, while maintaining an advantageously reduced width at the interface between the second base layer 150 and the first base layer 130.

[0051] Turning Figure 13 And refer to Figure 7Further embodiments of this disclosure may include recessing the inner spacer 144 to form a recessed inner spacer 168 within the opening 148. As with other operations discussed herein, the inner spacer 144 may be selectively processed (e.g., via an in-place mask 166), and a portion of the inner spacer 144 may be removed, leaving only a portion of the inner spacer 144 remaining on the first base layer 130 as the recessed inner spacer 168. The recessed inner spacer 168 may be formed, for example, by etching down (e.g., reactive ion etching (RIE)) the inner spacer 144 material to expose one or more adjacent sidewalls of the outer spacer 146 in the opening 148. Once the recessed inner spacer 168 is formed, the upper portion of the opening 148 may be wider adjacent to one or more outer spacers 146, and the lower portion of the opening 148 may be thinner adjacent to one or more recessed inner spacers 168. In this case, the opening 148 may be substantially T-shaped. Although one or more recessed inner spacers 168 are exemplarily shown as being substantially rectangular, one or more recessed inner spacers 168 may have vertically tapered sidewalls and / or other spacer configurations as described herein.

[0052] Advance to Figure 14 and 15 The additional processing is shown in a cross-sectional view. Figure 14 The formation of the second spacer layer 150 and the base silicide 151 is shown. Figure 15 The remaining portion forming the lateral bipolar transistor 160 is shown. Further processing can be performed after forming the recessed inner spacer 168. Mask 166 ( Figure 10 The first base layer 150 can be removed from ILD layer 142, and the remainder of the lateral bipolar transistor structure 160 can be formed substantially as discussed herein. Due to the formation of the recessed inner spacer 168, the second base layer 150 may include a lower portion 150a adjacent to the recessed inner spacer 168 and an upper portion 150b adjacent to the outer spacer 146 and located above the recessed inner spacer 168. Because the height of the recessed inner spacer 168 above the first base layer 150 is smaller, the upper portion 150b of the second base layer 150 can be horizontally wider than the lower portion 150b of the second base layer 150. That is, the width of the second base layer 150 can be piecewise defined (i.e., it increases from a smaller width to a larger width at predetermined points). In this case, the second base layer 150 can be substantially T-shaped. However, in embodiments where the recessed inner spacer 168 includes tapered sidewalls, the horizontal width of the second base layer 150 may gradually increase relative to its height before having a larger horizontal width above the recessed inner spacer 168. This contrasts with other embodiments featuring a chamfered inner spacer 164. Figure 10-12Similarly, the use of recessed inner spacers 168 allows for stronger conductivity between the base contact and the second base layer 150 via the base silicide 151, while maintaining an advantageously reduced width at the interface between the second base layer 150 and the first base layer 130.

[0053] The embodiments of this disclosure can provide several technical advantages. The lateral bipolar junction transistor structure 160 includes a second base layer 150 having a horizontal width advantageously no wider than that of the first base layer 130, and wherein the lower portion 140a of one or more E / C layers 140 can extend beneath outer spacers and / or inner spacers 146, 144. The use of multiple spacers 144, 146 can limit the size of the second base layer 150 while optionally allowing wider coupling to the base silicide 151, and simultaneously allowing a narrower physical interface with the first base layer 130. Embodiments of this disclosure can allow the inner and outer spacers 146, 146 to be the only insulating material between the second base layer 150 and one or more E / C layers 140, thereby allowing the E / C layer 140 to extend further over an underlying material such as a semiconductor layer 108. These and other features of this disclosure can provide improvements in gain and operating frequency, for example, due to increased electron mobility. The embodiments of this disclosure can be implemented using existing CMOS processing technologies and / or mask materials.

[0054] The methods and structures described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in package form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including the integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0056] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0057] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A lateral bipolar junction transistor structure, comprising: An emitter / collector layer located above an insulator, the emitter / collector layer having a first doping type; A first base layer is located on the insulator and adjacent to the emitter / collector layer. The first base layer has a concave sidewall adjacent to the emitter / collector layer. The first base layer has a second doping type opposite to the first doping type. A second base layer is located on the first base layer and has the second doping type, wherein the doping concentration of the second base layer is greater than the doping concentration of the first base layer; An inner spacer, located on the emitter / collector layer and adjacent to the second base layer; and An outer spacer is located on the emitter / collector layer and adjacent to the inner spacer.

2. The lateral bipolar transistor structure of claim 1, wherein, The inner spacer includes: a vertically tapered sidewall adjacent to the second base layer and a non-tapered sidewall adjacent to the outer spacer.

3. The lateral bipolar transistor structure of claim 1, wherein, The second base layer includes: The lower part has a first horizontal width, and The upper part has a second horizontal width greater than the first horizontal width, wherein the upper part is located on the inner spacer and adjacent to the outer spacer.

4. The lateral bipolar transistor structure of claim 3, wherein, The horizontal width of the first base layer is smaller than the horizontal width of the upper part of the second base layer.

5. The lateral bipolar transistor structure of claim 1, wherein, The emitter / collector layer includes a lower portion adjacent to the first base layer and an upper portion adjacent to the outer spacer.

6. The lateral bipolar transistor structure of claim 1, wherein, The inner spacer includes a substantially uniform horizontal width located between the second base layer and the outer spacer.

7. The lateral bipolar transistor structure of claim 1, wherein, The inner spacer comprises an oxide insulator, and the outer spacer comprises a nitride insulator.

8. A lateral bipolar junction transistor structure, comprising: An emitter / collector layer located above an insulator, the emitter / collector layer having a first doping type; A first base layer is located on the insulator and adjacent to the emitter / collector layer. The first base layer has a concave sidewall adjacent to the emitter / collector layer. The first base layer has a second doping type opposite to the first doping type. A second base layer, located on the first base layer and having the second doping type, wherein the doping concentration of the second base layer is greater than the doping concentration of the first base layer, and the second base layer comprises: The lower portion has a first horizontal width above the first base layer, and The upper part has a second horizontal width that is greater than the first horizontal width above the first base layer; An inner spacer, located on the emitter / collector layer and adjacent to the second base layer; and An outer spacer is located on the emitter / collector layer and adjacent to the inner spacer.

9. The lateral bipolar transistor structure of claim 8, wherein, The inner spacer includes: a vertically tapered sidewall adjacent to the second base layer and a non-tapered sidewall adjacent to the outer spacer.

10. The lateral bipolar transistor structure of claim 8, wherein, The horizontal width of the first base layer is smaller than the horizontal width of the upper part of the second base layer.

11. The lateral bipolar transistor structure of claim 8, wherein, The upper part includes: a lower surface located on the upper surface of the inner spacer, and a sidewall adjacent to the outer spacer.

12. The lateral bipolar transistor structure of claim 8, wherein, The emitter / collector layer includes a lower portion adjacent to the first base layer and an upper portion adjacent to the outer spacer.

13. The lateral bipolar transistor structure of claim 8, wherein, The second base layer is basically T-shaped.

14. The lateral bipolar transistor structure of claim 8, wherein, The inner spacer comprises an oxide insulator, and the outer spacer comprises a nitride insulator.

15. A method for forming a bipolar transistor structure, the method comprising: An emitter / collector layer is formed above an insulator, the emitter / collector layer having a first doping type; A first base layer is formed on the insulator and adjacent to the emitter / collector layer. The first base layer has a concave sidewall adjacent to the emitter / collector layer. The first base layer has a second doping type opposite to the first doping type. A second base layer is formed on the first base layer and has the second doping type, wherein the doping concentration of the second base layer is greater than the doping concentration of the first base layer; Forming an inner spacer located on the emitter / collector layer and adjacent to the second base layer; and An outer spacer is formed on the emitter / collector layer and adjacent to the inner spacer.

16. The method of claim 15, wherein, The formation of the inner spacer includes: forming a tapered sidewall in the vertical direction adjacent to the second base layer and a non-tapered sidewall of the inner spacer adjacent to the outer spacer.

17. The method of claim 15, wherein, Forming the second base layer includes: A lower portion having a first horizontal width is formed on the first base layer, and An upper portion is formed on the inner spacer and the lower portion and adjacent to the outer spacer, the upper portion having a second horizontal width greater than the first horizontal width.

18. The method of claim 15, wherein, Forming the emitter / collector layer includes: The lower portion of the emitter / collector layer is formed adjacent to the first base layer; and The upper part of the emitter / collector layer is formed adjacent to the outer spacer.

19. The method of claim 15, wherein, The inner spacer includes a substantially uniform horizontal width located between the second base layer and the outer spacer.

20. The method of claim 15, wherein, Forming the inner spacer includes forming an oxide insulator, and forming the outer spacer includes forming a nitride insulator.

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