Thin film transistor, array substrate and manufacturing method, display device

Abstract

The application discloses a thin film transistor, an array substrate and a preparation method thereof, and a display device. The thin film transistor comprises a substrate, a first gate electrode, a first insulating layer, an active layer, a second insulating layer and a second gate electrode which are arranged in a stack on one side of the substrate, the first gate electrode and the second gate electrode inputting the same gate signal, a source electrode and a drain electrode which are arranged on one side of the substrate, and at least one auxiliary electrode which is arranged on one side of the substrate, is electrically connected with the drain electrode, and at least partially overlaps with the active layer in a projection perpendicular to the substrate. The thin film transistor provided by the application is connected with the drain electrode through the auxiliary electrode and is controlled by the auxiliary gate electrode, so that the contact area of the gate electrode and the channel is increased, the control ability of the gate electrode is improved, the potential barrier width of the device is increased through the connection of the auxiliary electrode and the drain electrode, the leakage current is reduced, the on-off ratio of the device is increased, and the bipolarity of the device is inhibited.

Description

Technical Field

[0001] This application generally relates to the field of display technology, and specifically to a thin-film transistor, an array substrate and its fabrication method, and a display device. Background Technology

[0002] Currently, display products mainly consist of two categories: TFT-LCD (Thin Film Transistor Liquid Crystal Display) products and AMOLED (Active Matrix Organic Light-Emitting Display) products.

[0003] TFT-LCD primarily utilizes semiconductor materials such as amorphous silicon, low-temperature polycrystalline silicon, and semiconductor oxides (e.g., indium gallium zinc oxide) to form insulated-gate thin-film transistors with gate, source, and drain electrodes. AMOLED is currently a more advanced display technology, mainly utilizing high-mobility low-temperature polycrystalline silicon or oxide semiconductor thin-film crystal TFTs to form multi-level driving circuits.

[0004] All of the above display technologies rely on semiconductor TFTs as switching elements to control the display of pixels. The active layer electron mobility of the switching element is a parameter for reference in switching performance. With the pursuit of higher mobility, the switching performance of thin film transistors deteriorates, and the stability deteriorates, which affects the use of transistors and thus reduces display quality. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a thin-film transistor, an array substrate and a fabrication method thereof, and a display device that can improve the on / off ratio of the thin-film transistor, thereby ensuring good display quality of the display device.

[0006] In a first aspect, this application provides a thin-film transistor, comprising:

[0007] Substrate;

[0008] A first gate, a first insulating layer, an active layer, a second insulating layer, and a second gate are stacked on one side of the substrate, and the first gate and the second gate receive the same gate signal;

[0009] The source and drain electrodes are disposed on one side of the substrate.

[0010] At least one auxiliary electrode is disposed on one side of the substrate, the auxiliary electrode is electrically connected to the drain electrode, and the auxiliary electrode at least partially overlaps with the active layer in a projection perpendicular to the substrate.

[0011] Optionally, the active layer includes a channel region located between the source and the drain, and the overlapping portion of the auxiliary electrode and the active layer has a projection length perpendicular to the substrate that accounts for 5%-30% of the channel length of the channel region.

[0012] Optionally, the auxiliary electrode and the drain electrode are stacked on the substrate.

[0013] Optionally, the at least one auxiliary electrode includes a first auxiliary electrode, which is disposed on the side of the drain electrode close to the substrate.

[0014] Optionally, a first spacing is provided between the first auxiliary electrode and the first gate in a projection perpendicular to the substrate, and the active layer includes a channel region located between the source and the drain, wherein the first spacing is 5%-40% of the channel length of the channel region.

[0015] Optionally, the first auxiliary electrode is made of the same material as the first gate, and the material of the first auxiliary electrode is selected from one or more of Mo, Cu, Al, Cr, and Au.

[0016] Optionally, the first auxiliary electrode is made of the same material as the drain electrode, and the material of the first auxiliary electrode is selected from one or more of Pd and ITO.

[0017] Optionally, the at least one auxiliary electrode includes a second auxiliary electrode, which is disposed on the side of the drain electrode opposite to the substrate.

[0018] Optionally, a second spacing is provided between the second auxiliary electrode and the second gate in a projection perpendicular to the substrate, and the active layer includes a channel region located between the source and the drain, wherein the second spacing is 5%-40% of the channel length of the channel region.

[0019] Preferably, the second auxiliary electrode and the first auxiliary electrode have their orthogonal projections on the substrate coincide.

[0020] Optionally, the second auxiliary electrode is made of the same material as the second gate, and the material of the second auxiliary electrode is selected from one or more of Mo, Cu, Al, Cr, and Au.

[0021] Optionally, the second auxiliary electrode is made of the same material as the drain electrode, and the material of the second auxiliary electrode is selected from one or more of Pd and ITO.

[0022] Optionally, the active layer is a carbon nanotube (CNT) material.

[0023] Secondly, this application provides an array substrate having thin-film transistors as described above disposed thereon, and further comprising scan lines extending along a first direction and data lines extending along a second direction, wherein the scan lines and the data lines intersect to define pixel units.

[0024] Thirdly, this application provides a display device having an array substrate as described above disposed thereon.

[0025] Fourthly, this application provides a method for fabricating a thin-film transistor, comprising:

[0026] Provide substrates;

[0027] A first gate layer is formed on the substrate, and the first gate is formed by a patterning process.

[0028] A pattern of a first insulating layer is formed on the first gate layer;

[0029] A pattern of an active layer is formed on the first insulating layer; a source / drain layer is formed on the substrate, and the source and drain are formed by a patterning process.

[0030] A pattern of a second insulating layer is formed on the active layer;

[0031] A second gate layer is formed on the second insulating layer and patterned to form the second gate;

[0032] The method further includes:

[0033] At least one auxiliary electrode is formed, the auxiliary electrode being electrically connected to the drain electrode, and the auxiliary electrode at least partially overlapping the active layer in a projection perpendicular to the substrate.

[0034] Optionally, forming at least one auxiliary electrode includes:

[0035] The first auxiliary electrode is formed on the first gate layer simultaneously with the formation of the first gate through a single patterning process.

[0036] Optionally, forming at least one auxiliary electrode includes:

[0037] A second auxiliary electrode is formed on the second gate layer simultaneously with the formation of the second gate through a single patterning process.

[0038] Optionally, forming at least one auxiliary electrode includes:

[0039] A first auxiliary electrode is formed on the source / drain layer by a single patterning process while the drain is being formed. The first auxiliary electrode is disposed on the side of the drain near the substrate.

[0040] Furthermore, the method further includes: forming the pattern of the first auxiliary electrode on the first insulating layer by an over-etching process.

[0041] Optionally, forming at least one auxiliary electrode includes:

[0042] A second auxiliary electrode is formed on the source / drain layer simultaneously with the formation of the drain electrode through a single patterning process. The second auxiliary electrode is disposed on the side of the drain electrode away from the substrate.

[0043] Furthermore, the method also includes:

[0044] The first insulating layer and the second insulating layer are patterned to form vias, and the first gate and the second gate are electrically connected through the vias.

[0045] Fifthly, this application provides a method for fabricating an array substrate, including the method for fabricating a thin-film transistor as described in any of the above descriptions, the method further comprising:

[0046] A pixel electrode pattern is formed above the source / drain layer.

[0047] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0048] The thin-film transistor provided in this application increases the contact area between the gate and the channel and enhances the gate's control capability by connecting the auxiliary electrode to the drain and the auxiliary gate for control. Connecting the auxiliary electrode to the drain increases the device's barrier width, reduces leakage current, increases the device's on / off ratio, and suppresses the device's bipolarity. Attached Figure Description

[0049] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0050] Figure 1 A schematic diagram of a thin-film transistor provided for an embodiment of this application;

[0051] Figure 2 A schematic diagram of another thin-film transistor structure provided for an embodiment of this application;

[0052] Figure 3 A schematic diagram of another thin-film transistor structure provided for an embodiment of this application;

[0053] Figure 4 A schematic diagram of the energy band structure of a thin-film transistor provided for an embodiment of this application;

[0054] Figure 5A schematic diagram of the transfer characteristic curves of a thin-film transistor provided for an embodiment of this application;

[0055] Figure 6 A schematic diagram of a gate arrangement scheme provided for an embodiment of this application;

[0056] Figure 7 A schematic diagram of another gate arrangement scheme provided for an embodiment of this application;

[0057] Figure 8 This is a schematic diagram of the energy band structure corresponding to the gap length between the gate and the auxiliary electrode.

[0058] Figure 9 A schematic diagram of an array substrate provided for an embodiment of this application;

[0059] Figure 10 For the corresponding Figure 9 Schematic diagram of the cross-section at point a;

[0060] Figure 11 For the corresponding Figure 9 Schematic diagram of the cross-section at point b;

[0061] Figure 12 A flowchart illustrating a method for fabricating a thin-film transistor, provided as an embodiment of this application;

[0062] Figure 13 This is a schematic diagram of a thin-film transistor provided as an embodiment of this application. Detailed Implementation

[0063] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0064] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0065] Small bandgap semiconductor materials have great potential in the field of high-speed integrated circuits due to their ultra-high mobility. In particular, the flexibility and high light transmittance of novel nanomaterials such as carbon nanotubes (CNTs) give them unique advantages in flexible electronics and display driving circuits.

[0066] Carbon nanotubes typically have a small band gap. However, devices made of small band gap semiconductor materials usually have a small on / off ratio. When operating under a large bias voltage, the minority carrier reverse tunneling current emitted from the drain terminal increases significantly due to the low and extremely thin Schottky barrier at the drain terminal. This results in an increase in the off-state current of the device under a large bias voltage, and the bipolarity is very obvious.

[0067] The device on / off ratio is the ratio of the on-state current to the off-state current of the device. It is an important parameter for evaluating the characteristics of a thin-film transistor (TFT). There are many methods to determine the on-state current and the off-state current. The simplest method is to define the on-state current as the maximum current of the device and the minimum leakage current as the off-state current.

[0068] Carbon nanotubes (CNTs) theoretically possess extremely high electron mobility, and their high mobility advantage can be maximized by aligning them as the active layer of a TFT. However, due to the generally small band gap of CNTs, it is difficult for aligned CNT-TFTs to achieve a high on / off ratio at high voltages. Furthermore, CNTs tend to deposit multiple layers during fabrication, and CNTs closer to the gate can cause a shielding effect on other layers.

[0069] Please see details. Figure 1 In a first aspect, this application provides a thin-film transistor, comprising:

[0070] Substrate 1;

[0071] A first gate 2, a first insulating layer 4, an active layer 5, a second insulating layer 6, and a second gate 3 are stacked on one side of the substrate 1, and the first gate 2 and the second gate 3 receive the same gate signal;

[0072] Source 7 and drain 8 are disposed on one side of the substrate 1;

[0073] At least one auxiliary electrode is disposed on one side of the substrate 1, the auxiliary electrode is electrically connected to the drain electrode 8, and the auxiliary electrode and the active layer 5 overlap at least partially in a projection perpendicular to the substrate 1.

[0074] In this embodiment, at least one auxiliary electrode is added to the dual-gate TFT, which adds an additional control interface, thus effectively enhancing the gate control capability. When applied to the active layer 5 of CNT, by changing the structure of the switching transistor, the shielding effect between multiple CNT layers can be eliminated, thereby improving the switching ratio.

[0075] Thin-film transistors (TFTs) are a type of field-effect transistor. TFTs have both free electrons and holes as charge carriers, both of which participate in electrical conduction. The conductivity of a TFT is a physical quantity reflecting the conductivity of a semiconductor material, determined by carrier density and mobility. The TFT in this application can be a P-channel transistor (PMOS) or an N-channel transistor (NMOS). In this embodiment, a PMOS transistor is used as an example.

[0076] like Figure 4 As shown, in the embodiments of this application, when a small negative bias voltage is applied to the drain 8, the thin-film transistor, as Figure 4 As shown in (a), S represents the electron-filled state of source 7, and D represents the electron-filled state of drain 8. The conventional structure has a relatively wide potential barrier, which can prevent electrons from entering the channel, such as... Figure 4 As shown by the dashed line in (a); the structural barrier in this application is completely preserved, therefore electrons will not enter the channel, as shown in the image. Figure 4 (a) is shown by the solid line.

[0077] When a large negative bias voltage is applied to drain 8, such as Figure 4 As shown in (b), S represents the electron-filled state of source 7, and D represents the electron-filled state of drain 8. In a conventional structure, the potential barrier becomes thinner, increasing the probability of electrons tunneling through the barrier into the channel to form a current, such as... Figure 4 (b) is shown by the dashed line. In this application, the TFT structure is connected to the drain 8 phase via the auxiliary electrode. Under this bias voltage, the potential barrier can still be completely retained to block electrons, thus achieving a higher on / off ratio while suppressing device bipolarity, such as... Figure 4 (b) is shown by the solid line.

[0078] The structure in this embodiment solves the problem of low drain / channel barrier height in the off-state, reducing the off-state current and improving the on / off ratio of the thin-film transistor. A potential barrier, also known as a potential barrier, is a barrier layer formed by the diffusion of electrons and holes in a PN junction; the potential energy difference between the two sides is called the barrier. The wider the barrier at the drain 8, the more effectively it prevents electrons from entering the channel, resulting in a smaller leakage current.

[0079] Figure 5 The transfer characteristic curve of the thin-film transistor provided in the embodiments of this application is shown. The transfer characteristic curve reflects the drain current I. D With gate-source voltage U GS The curve representing the relationship is referred to as the transfer characteristic. From the transfer characteristic curve, it can be seen that the thin-film transistor provided in this application embodiment can well meet the control of the drain current, effectively improve the switching ratio, and suppress the bipolarity of the device.

[0080] In this embodiment, the active layer 5 includes a channel region located between the source electrode 7 and the drain electrode 8, and the overlapping portion of the auxiliary electrode and the active layer 5 has a projection length perpendicular to the substrate 1 that accounts for 5%-30% of the channel length of the channel region.

[0081] It should be noted that when a transistor TFT is turned on, its current flows from the drain to the source (or from the source to the drain) through the channel below the gate. The channel is the conductive path of the transistor TFT, and its region is located in the active layer between the source and drain. The channel length refers to the distance from the source to the drain on the active layer of the transistor TFT, such as... Figure 6 and Figure 7 L1 in the middle. Figure 6 and Figure 7 In this context, L2 represents the projected length of the auxiliary electrode perpendicular to the substrate, and ΔL represents the projected length of the overlapping portion of the auxiliary electrode and the active layer perpendicular to the substrate.

[0082] The projections of the first gate 2 and the drain 8 perpendicular to the substrate 1 do not overlap, and the projections of the second gate 3 and the source 7 perpendicular to the substrate 1 do not overlap.

[0083] It should be noted that, in this embodiment, device performance is improved by controlling the contact area between the first gate 2 and the second gate 3 and the channel, and the contact area between the first auxiliary electrode 9 and the second auxiliary electrode 10 and the channel. In this embodiment, the transistor has an absolute advantage in suppressing gate leakage current. By increasing the gate's control area over the channel through the overall structure of the dual-gate electrical connection, the transistor greatly enhances the gate control capability, thereby effectively suppressing the short-channel effect and reducing subthreshold leakage current.

[0084] The contact area between the first gate 2, the second gate 3 and the channel region can be set differently depending on the device, effect and application. Figure 6 and Figure 7 A schematic diagram showing different overlap areas between the gate and the channel region is illustrated. The second gate 3 can be located within the projection range of the channel region, and control is achieved by adjusting the area between the first gate 2 and the channel region. Increasing the area of ​​the first gate 2 improves gate control capability, while increasing the projection overlap area of ​​the second gate 3 with the channel region eliminates the shielding effect between multiple CNTs and improves the on / off ratio.

[0085] In this embodiment, the auxiliary electrode and the drain electrode 8 are stacked on the substrate 1.

[0086] It should be noted that, in the embodiments of this application, "layered arrangement" includes direct contact or indirect contact separated by other layers. In the case of indirect contact, the auxiliary electrode and the drain electrode are electrically connected through vias. In the embodiments of this application, it is preferred that the auxiliary electrode and the drain electrode 8 are in direct contact. By using direct contact, the contact area between the drain electrode 8 and the auxiliary electrode is increased, the resistance is reduced, and the bandwidth of the barrier blocking electrons is further preserved, thereby improving the on / off ratio.

[0087] The at least one auxiliary electrode includes a first auxiliary electrode 9, which is disposed on the side of the drain electrode 8 near the substrate 1.

[0088] The first auxiliary electrode 9 and the first gate 2 are provided with a first spacing d1 between their projections perpendicular to the substrate 1. The active layer 5 includes a channel region located between the source electrode 7 and the drain electrode 8. The first spacing d1 is 5%-40% of the channel length of the channel region.

[0089] It should be noted that, based on the research conducted in this application, it has been found that spacing between the auxiliary electrode and the gate, with partial overlap between the auxiliary gate and the drain 8, has the same effect on the on / off ratio. For example... Figure 8 As shown, the gap length between the first auxiliary electrode 9 and the first gate 2, or the gap length between the second auxiliary electrode 10 and the second gate 3, is more conducive to preserving the bandgap thickness, meaning electrons are less likely to pass through the potential barrier. However, if the gap is too long, it will reduce the effective control area of ​​the gate or auxiliary electrode, resulting in insufficient on-state current and affecting device characteristics. The specific setting depends on the specific device, effect, or application. Therefore, considering the combined effects of the potential barrier and the on-state current, this application sets the first gap d1 to 5%-40% of the channel length of the channel region.

[0090] In one embodiment of this application, the first auxiliary electrode 9 is made of the same material as the first gate 2, and the material of the first auxiliary electrode 9 is selected from one or more of Mo, Cu, Al, Cr, and Au.

[0091] In this embodiment, the first auxiliary electrode 9 and the first gate 2 are arranged in the same layer, and the first auxiliary electrode 9 and the first gate 2 are made of the same material. During the fabrication process, the first auxiliary electrode 9 and the first gate 2 can be formed in one patterning process, which reduces the number of masks, reduces the process flow, and improves production performance.

[0092] In one embodiment of this application, the first auxiliary electrode 9 is made of the same material as the drain electrode 8, and the material of the first auxiliary electrode 9 is a high work function material selected from one or more of Pd and ITO.

[0093] In principle, for PMOS, selecting a high work function material makes the source-drain contact without a barrier to holes, and at the same time, the first auxiliary electrode 9 is in a hole depletion mode; for NMOS, selecting a high work function material makes the source-drain contact without a barrier to electrons, and at the same time, the first auxiliary electrode 9 is in an electron depletion mode.

[0094] In addition, the at least one auxiliary electrode includes a second auxiliary electrode 10, which is disposed on the side of the drain electrode 8 away from the substrate 1.

[0095] The second auxiliary electrode 10 and the second gate electrode 3 are provided with a second spacing d2 between their projections perpendicular to the substrate 1. The active layer 5 includes a channel region located between the source electrode 7 and the drain electrode 8. The second spacing d2 is 5%-40% of the channel length of the channel region.

[0096] It should be noted that, in the preferred embodiment of this application, when there are two auxiliary electrodes, the projections of the positions of the first auxiliary electrode and the second auxiliary electrode on the substrate coincide, that is, the first spacing and the second spacing are equal, and the overlap area between the first auxiliary electrode and the drain electrode and the overlap area between the second auxiliary electrode and the drain electrode are equal.

[0097] In one embodiment of this application, the second auxiliary electrode 10 is made of the same material as the second gate 3, and the material of the second auxiliary electrode 10 is selected from one or more of Mo, Cu, Al, Cr, and Au.

[0098] It should be noted that in the embodiments of this application, both the first gate 2 and the second gate 3 are made of metallic materials. The materials of the first gate 2 and the second gate 3 can be pure metals or metal alloys. For example, the materials of the first gate 2 and the second gate 3 include one or more of Mo, Cu, Al, Cr, and Au. It should also be noted that the materials of the first gate 2 and the second gate 3 can be the same or different, and the embodiments of this application do not specifically limit this.

[0099] Additionally, it is worth noting that in the embodiments of this application, the same gate signal is input to the first gate 2 and the second gate 3. In some embodiments, the corresponding first gate 2 or second gate 3 can be input through two identical gate signal lines. In other embodiments, to save wiring space, the first gate 2 and the second gate 3 are electrically connected through a via 11 and input through a single gate signal line. Other configurations can also be implemented in different embodiments, and this application does not limit these configurations.

[0100] In one embodiment of this application, the second auxiliary electrode 10 is made of the same material as the drain electrode 8, and the material of the second auxiliary electrode 10 is a high work function material, selected from one or more of Pt, Pd, and ITO.

[0101] It should be noted that the work function of a metal refers to the minimum energy (usually measured in electron volts) required for an electron to escape immediately from a solid surface. In practical implementation, for transistors where the active layer 5 is made of CNT material, to reduce the off-state current on the drain 8 or suppress the bipolarity of the transistor device, high work function metal materials are also chosen for the source and drain 8. The auxiliary electrode is electrically connected to the drain 8. When the auxiliary electrode and drain 8 are made of the same material, the threshold voltage Vth of the transistor will shift in a direction that makes it difficult to turn on. Therefore, for CNT as the active layer 5, the preferred materials for the first auxiliary electrode 9 and the second auxiliary electrode 10 are the same as the materials for the first gate and the second gate.

[0102] Additionally, it is worth noting that the material settings for the first auxiliary electrode 9 and the second auxiliary electrode 10 in this embodiment are merely illustrative. Based on the same structural principle, the materials of the first auxiliary electrode 9 and the second auxiliary electrode 10 can also be set in other ways. For example, the materials of the first auxiliary electrode 9 and the second auxiliary electrode 10 can be the same or different, and different from the material of the drain electrode 8.

[0103] In this embodiment, the active layer 5 is a carbon nanotube (CNT) material. It should be noted that the active layer 5 can also include other narrow bandgap materials. Typical narrow bandgap materials include, for example, novel nanomaterials such as graphene ribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), and black phosphorus (P); and semiconductor materials such as germanium (Ge), indium arsenide (InAs), indium antimonide (InSb), lead sulfide (PbS), lead selenide (PbSe), and lead telluride (PbTe).

[0104] The thin-film transistor provided in this application increases the contact area between the gate and the channel and enhances the gate's control capability by connecting an auxiliary electrode to the drain 8 and controlling the auxiliary gate. Connecting the auxiliary electrode to the drain 8 increases the device's barrier width, reduces leakage current, increases the device's on / off ratio, and suppresses the device's bipolarity.

[0105] like Figure 9 As shown, this application provides an array substrate having thin-film transistors as described above, and further including scan lines extending along a first direction and data lines extending along a second direction, wherein the scan lines and the data lines intersect to define pixel units.

[0106] The array substrate provided in this embodiment of the invention can be used for liquid crystal display (LCD) panels or organic light-emitting diode (OLED) display panels.

[0107] Figure 10 The corresponding Figure 9 A cross-sectional schematic diagram at point a shows the connection between the first gate 2 and the second gate 3 via a via 11. Figure 11 The corresponding Figure 9 The cross-sectional diagram at point b shows that the source electrode 7 is connected to the data line, and the drain electrode 8 is connected to the pixel electrode 13 of the pixel unit. It should be noted that, referring to... Figure 11 The drain and active layer, and the source and active layer overlap in a direction perpendicular to the substrate. This ensures sufficient electrical connection and achieves the stability of the transistor device. In addition, the order in which the source and drain are fabricated and the active layer are fabricated is not limited during the transistor fabrication process.

[0108] In addition, this application provides a display device having an array substrate as described above disposed thereon.

[0109] The display device in this invention embodiment can be a television, or a display terminal device with display function such as a PC, smartphone, tablet computer, e-book reader, MP3 (Moving Picture Experts Group Audio Layer III) player, MP4 (Moving Picture Experts Group Audio Layer IV) player, or portable computer.

[0110] Please refer to Figure 12 This application provides a method for fabricating a thin-film transistor, comprising:

[0111] S01, Provide substrate 1.

[0112] In the embodiments of this application, the substrate 1 is a rigid substrate or a flexible substrate. The rigid substrate can be made of transparent glass, transparent plastic, etc., and the flexible substrate can be made of polymer materials such as polyimide (PI), polyethersulfone (PES), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyaryl compounds (PAR), and glass fiber reinforced plastic (FRP).

[0113] The substrate 1 is also provided with a barrier layer, a buffer layer 12, etc. For example, on a pre-cleaned transparent substrate, a buffer layer 12 is formed by methods such as PECVD (plasma-enhanced chemical vapor deposition), LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric pressure chemical vapor deposition), ECR-CVD (electron cyclotron resonant chemical vapor deposition) or sputtering to prevent impurities contained in the glass from diffusing into the active layer 5 and to prevent them from affecting the threshold voltage and leakage current characteristics of the TFT element.

[0114] S02. A first gate layer is formed on the substrate 1, and a first gate 2 is formed by a patterning process. The material of the first gate layer may be selected from one or more of Mo, Cu, Al, Cr, and Au.

[0115] It should be noted that the "patterning process" mentioned in this application includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0116] It should also be noted that, in this application, "A and B are set on the same layer" means that A and B are formed simultaneously through the same drafting process. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0117] S03. A pattern of a first insulating layer 4 is formed on the first gate layer; the material of the first insulating layer 4 can be at least one of SiO, SiON, and SiN. When forming the first insulating layer 4, chemical deposition processes such as PECVD, LPCVD, APCVD, or ECR-CVD can be used, or processes such as coating, sputtering, or evaporation can be used.

[0118] S04. A pattern of an active layer 5 is formed on the first insulating layer 4. In this embodiment, the active layer 5 can be selected as a material with a narrow bandgap, such as novel nanomaterials like CNTs, graphene ribbons, molybdenum disulfide (MoS2), tungsten disulfide (WS2), and black phosphorus (P); as well as semiconductor materials such as germanium (Ge), indium arsenide (InAs), indium antimonide (InSb), lead sulfide (PbS), lead selenide (PbSe), and lead telluride (PbTe).

[0119] S05. A source / drain layer is formed on the substrate 1, and a source electrode 7 and a drain electrode 8 are formed by a patterning process. The material of the source / drain layer is preferably a high work function material such as Pd or ITO; however, it can also be Mo, Cu, Al, Cr / Au, etc. During the patterning process, an etchant can be used to etch the source / drain metal thin film.

[0120] S06. A pattern of a second insulating layer 6 is formed on the active layer 5; the material of the second insulating layer 6 can be at least one of SiO, SiON, and SiN. The second insulating layer 6 can be formed using processes such as coating, sputtering, or vapor deposition.

[0121] It should be noted that, in the embodiments of this application, for the formation of the second insulating layer 6, for devices with CNT material as the active layer 5, chemical deposition processes such as PECVD, LPCVD, APCVD or ECR-CVD should be avoided as much as possible to prevent the chemical deposition process from damaging the underlying CNT and causing a decrease in performance.

[0122] S07. A second gate layer is formed on the second insulating layer 6 and a second gate 3 is patterned. The material of the second gate layer may be selected from one or more of Mo, Cu, Al, Cr, and Au.

[0123] S10. Form at least one auxiliary electrode, which is electrically connected to the drain electrode 8, and the auxiliary electrode at least partially overlaps with the active layer 5 in a projection perpendicular to the substrate 1.

[0124] It should be noted that, in the embodiments of this application, there are several different choices for the material of the auxiliary electrode, and different choices can be made according to different application scenarios. The first auxiliary electrode 9 and the second auxiliary electrode 10 are made of the same material.

[0125] In one embodiment of this application, forming at least one auxiliary electrode includes:

[0126] S101. A first auxiliary electrode 9 is formed on the first gate layer simultaneously with the formation of the first gate 2 through a patterning process. The first auxiliary electrode 9 is made of the same material as the first gate 2, and the material of the first auxiliary electrode 9 is selected from one or more of Mo, Cu, Al, Cr, and Au.

[0127] S102, A second auxiliary electrode 10 is formed on the second gate layer by a patterning process while forming the second gate 3.

[0128] In this embodiment, the first gate 2 and the first auxiliary electrode 9 are made of the same material, and the second gate 3 and the second auxiliary electrode 10 are made of the same material, such as... Figure 1 As shown, the process is completed in a single patterning step, reducing the number of steps. The number of auxiliary gates in this embodiment can be selected differently depending on the device, desired effect, and application.

[0129] It should be noted that the materials of the first gate 2 and the second gate 3 may be the same or different. In the embodiments of this application, the same gate signal is input to the first gate 2 and the second gate 3. In some embodiments, the corresponding first gate 2 or second gate 3 can be input through two identical gate signal lines. In other embodiments, in order to save wiring space, the first gate 2 and the second gate 3 are electrically connected through a via 11 and input through a single gate signal line. Other configurations can also be made in different embodiments, and this application does not limit them.

[0130] Therefore, in specific implementation, the method further includes:

[0131] S300, The first insulating layer 4 and the second insulating layer 6 are patterned to form vias 11, and the first gate 2 and the second gate 3 are electrically connected through the vias 11.

[0132] In another embodiment of this application, forming at least one auxiliary electrode includes:

[0133] S201. A first auxiliary electrode 9 is formed on the source / drain layer simultaneously with the formation of the drain electrode 8 through a single patterning process. The first auxiliary electrode 9 is disposed on the side of the drain electrode 8 close to the substrate 1. The first auxiliary electrode 9 is made of the same material as the drain electrode 8, and the material of the first auxiliary electrode 9 is a high work function material selected from one or more of Pd and ITO.

[0134] In addition, when forming the first auxiliary electrode 9, the method further includes: forming the pattern of the first auxiliary electrode 9 on the first insulating layer 4 by an over-etching process.

[0135] It should be noted that in this embodiment, the first auxiliary electrode 9 is disposed on the lower surface of the drain electrode 8 near the substrate 1. The first auxiliary electrode 9 is in direct contact with the drain electrode 8. The orthographic projection of the first auxiliary electrode 9 on the substrate 1 exceeds the area of ​​the orthographic projection of the drain electrode 8 on the substrate 1, which can be formed by over-etching.

[0136] Over-etching, also known as multiple etching, refers to the etching line extending beyond the specified range during the etching process. This range can reach a distance of 1.5 mm. In this application, over-etching can be used to achieve an integrated forming process between the first auxiliary electrode 9 and the drain electrode 8.

[0137] S202. A second auxiliary electrode 10 is formed on the source / drain layer simultaneously with the formation of the drain electrode 8 through a single patterning process. The second auxiliary electrode 10 is disposed on the side of the drain electrode 8 facing away from the substrate 1. The second auxiliary electrode 10 is made of the same material as the drain electrode 8, and the material of the second auxiliary electrode 10 is a high work function material selected from one or more of Pt, Pd, and ITO.

[0138] In the embodiments of this application, such as Figure 13 As shown, the materials of the first auxiliary electrode 9 and the second auxiliary electrode 10 are the same as those of the drain electrode 8. During fabrication, they can be formed in a single patterning process, reducing the number of masks, simplifying the process flow, and improving production performance. Of course, the materials of the first auxiliary electrode 9 and the second auxiliary electrode 10 can be selectively the same as those of the drain electrode 8, depending on the device, effect, application, etc. If the materials of the first auxiliary electrode 9 and the second auxiliary electrode 10 are different, they can be selectively the same as those of the first gate electrode 2 or the second gate electrode 3, and fabricated using the same process as the gate layer in the same layer.

[0139] Fifthly, this application provides a method for fabricating an array substrate, including the method for fabricating a thin-film transistor as described in any of the above descriptions, the method further comprising:

[0140] A pattern of pixel electrode 13 is formed above the source / drain layer.

[0141] In this embodiment, a patterning process is performed in one step using an auxiliary electrode and the first gate 2, the second gate 3, or the drain 8, which reduces the number of masks, simplifies the process flow, and improves production performance.

[0142] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0143] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0144] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for descriptive purposes only and is not intended to limit the invention. Terms such as “set” appearing herein can refer to either a component being directly attached to another component or a component being attached to another component via an intermediary. A feature described in one embodiment herein may be applied, alone or in combination with other features, to another embodiment, unless that feature is not applicable in that other embodiment or is otherwise stated.

[0145] The present invention has been described through the above embodiments; however, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will understand that many variations and modifications can be made based on the teachings of the present invention, and all such variations and modifications fall within the scope of protection claimed by the present invention.

Claims

1. A thin film transistor, characterized by comprising: include: Substrate; A first gate, a first insulating layer, an active layer, a second insulating layer, and a second gate are stacked on one side of the substrate, and the first gate and the second gate receive the same gate signal; The source and drain electrodes are disposed on one side of the substrate. At least one auxiliary electrode is disposed on one side of the substrate, the auxiliary electrode is electrically connected to the drain electrode, and the auxiliary electrode at least partially overlaps with the active layer in a projection perpendicular to the substrate. The at least one auxiliary electrode includes a first auxiliary electrode and / or a second auxiliary electrode, wherein the first auxiliary electrode is disposed on the side of the drain electrode close to the substrate, and the second auxiliary electrode is disposed on the side of the drain electrode away from the substrate. A first spacing is provided between the first auxiliary electrode and the first gate electrode when projected perpendicular to the substrate. The active layer includes a channel region located between the source electrode and the drain electrode. The first spacing is 5%-40% of the channel length of the channel region. The second auxiliary electrode and the second gate are provided with a second spacing between their projections perpendicular to the substrate. The active layer includes a channel region located between the source and the drain. The second spacing is 5%-40% of the channel length of the channel region.

2. The thin film transistor according to claim 1, wherein The overlapping portion of the auxiliary electrode and the active layer has a projection length perpendicular to the substrate that accounts for 5%-30% of the channel length of the channel region.

3. The thin film transistor according to claim 1, wherein The auxiliary electrode and the drain electrode are stacked on the substrate.

4. The thin film transistor according to claim 1, wherein The first auxiliary electrode is made of the same material as the first gate, and the material of the first auxiliary electrode is selected from one or more of Mo, Cu, Al, Cr, and Au.

5. The thin film transistor according to claim 1, wherein The first auxiliary electrode is made of the same material as the drain electrode, and the material of the first auxiliary electrode is one or more of Pd and ITO.

6. The thin-film transistor according to claim 1, characterized in that, The second auxiliary electrode and the first auxiliary electrode have their orthogonal projections on the substrate coincide.

7. The thin-film transistor according to claim 1, characterized in that, The second auxiliary electrode is made of the same material as the second gate, and the material of the second auxiliary electrode is selected from one or more of Mo, Cu, Al, Cr, and Au.

8. The thin-film transistor according to claim 1, characterized in that, The second auxiliary electrode is made of the same material as the drain electrode, and the material of the second auxiliary electrode is one or more of Pd and ITO.

9. The thin-film transistor according to claim 1, characterized in that, The active layer is made of carbon nanotube (CNT) material.

10. An array substrate, characterized in that, It is provided with a thin-film transistor as described in any one of claims 1-9, and further includes a scan line extending along a first direction and a data line extending along a second direction, wherein the scan line and the data line intersect to define a pixel unit.

11. A display device, characterized in that, It is provided with the array substrate as described in claim 10.

12. A method for fabricating a thin-film transistor, characterized in that, For fabricating a thin-film transistor as described in any one of claims 1-9, comprising: Provide substrates; A first gate layer is formed on the substrate, and the first gate is formed by a patterning process. A pattern of a first insulating layer is formed on the first gate layer; A pattern of an active layer is formed on the first insulating layer; A source / drain layer is formed on the substrate, and the source and drain electrodes are formed by a patterning process. A pattern of a second insulating layer is formed on the active layer; A second gate layer is formed on the second insulating layer and patterned to form the second gate; The method further includes: At least one auxiliary electrode is formed, the auxiliary electrode being electrically connected to the drain electrode, and the auxiliary electrode at least partially overlapping the active layer in a projection perpendicular to the substrate.

13. The method for fabricating a thin-film transistor according to claim 12, characterized in that, The formation of at least one auxiliary electrode includes: The first auxiliary electrode is formed on the first gate layer simultaneously with the formation of the first gate through a single patterning process.

14. The method for fabricating a thin-film transistor according to claim 13, characterized in that, The formation of at least one auxiliary electrode includes: A second auxiliary electrode is formed on the second gate layer simultaneously with the formation of the second gate through a single patterning process.

15. The method for fabricating a thin-film transistor according to claim 12, characterized in that, The formation of at least one auxiliary electrode includes: A first auxiliary electrode is formed on the source / drain layer by a single patterning process while the drain is being formed. The first auxiliary electrode is disposed on the side of the drain near the substrate.

16. The method for fabricating a thin-film transistor according to claim 15, characterized in that, The method further includes: forming the pattern of the first auxiliary electrode on the first insulating layer by an over-etching process.

17. The method for fabricating a thin-film transistor according to claim 16, characterized in that, The formation of at least one auxiliary electrode includes: A second auxiliary electrode is formed on the source / drain layer simultaneously with the formation of the drain electrode through a single patterning process. The second auxiliary electrode is disposed on the side of the drain electrode away from the substrate.

18. The method for fabricating a thin-film transistor according to claim 12, characterized in that, The method further includes: The first insulating layer and the second insulating layer are patterned to form vias, and the first gate and the second gate are electrically connected through the vias.

19. A method for fabricating an array substrate, characterized in that, The method includes the fabrication method of a thin-film transistor as described in any one of claims 12-18, the method further comprising: A pixel electrode pattern is formed above the source / drain layer.

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