Diode structure with one or more elevated terminals

Abstract

The invention relates to a diode structure having one or more elevated terminals. A structure for a diode and a method of manufacturing a structure for a diode. The structure comprises a layer of semiconductor material. The layer comprises a first segment, a second segment, and a third segment positioned laterally between the first segment and the second segment. The structure comprises a first terminal having a first elevated semiconductor layer on the first segment of the layer, a second terminal comprising a portion on the second segment of the layer, and a gate on the third segment of the layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 237,206, filed August 26, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to the manufacture of semiconductor devices and integrated circuits, and more specifically, to structures for diodes and methods for forming structures for diodes. Background Technology

[0004] High-performance diodes are implemented in radio frequency (RF) technology to support applications such as millimeter-wave frequency multipliers and subharmonic mixers, power detectors, low-noise voltage-controlled oscillators, and high-speed data converter front-ends. Schottky barrier diodes are semiconductor diodes formed by a junction of a metal and a lightly doped semiconductor. PIN diodes comprise an intrinsic semiconductor region located between a p-type semiconductor region and an n-type semiconductor region.

[0005] There is a need to improve the structure for diodes and the methods for forming the structure for diodes. Summary of the Invention

[0006] In one embodiment, a structure for a diode is provided. The structure includes a layer made of a semiconductor material. The layer includes a first segment, a second segment, and a third segment laterally positioned between the first segment and the second segment. The structure further includes: a first terminal having a first raised semiconductor layer located on the first segment of the layer; a second terminal including a portion located on the second segment of the layer; and a gate located on the third segment of the layer.

[0007] In one embodiment, a method of manufacturing a structure for a diode is provided. The method includes: forming a first terminal including a first raised semiconductor layer on a first segment of a layer made of semiconductor material; forming a second terminal including a portion on a second segment of the layer; and forming a gate on a third segment of the layer. The third segment of the layer is laterally positioned between the first segment and the second segment of the layer. Attached Figure Description

[0008] The accompanying drawings, which are included in and form part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.

[0009] Figure 1-8This is a cross-sectional view of the structure of the continuous manufacturing stage of the processing method according to an embodiment of the present invention.

[0010] Figure 9 This is a simplified schematic top view for illustrative purposes, in which... Figure 8 Typically, the line is cut off at 8-8 intervals.

[0011] Figure 10-11 This is a cross-sectional view of the structure of the continuous manufacturing stage of the processing method according to an alternative embodiment of the present invention.

[0012] Figure 12-13 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention. Detailed Implementation

[0013] refer to Figure 1 According to embodiments of the present invention, the semiconductor-on-insulator substrate includes a device layer 12 defining a layer comprising a semiconductor material, a buried insulating layer 14 located below the device layer 12, and a processing substrate 16 located below the buried insulating layer 14. The buried insulating layer 14 has a lower interface with the processing substrate 16 and an upper interface with the device layer 12, the lower interface and the upper interface being separated by the thickness of the buried insulating layer 14. In one embodiment, the device layer 12 may have a thickness in the range of about 4 nanometers (nm) to about 100 nm. In an alternative embodiment, the device layer 12 may have a thickness in the range of about 4 nm to about 10 nm. In one embodiment, the device layer 12 can be used to fabricate a fully depleted silicon-on-insulator device structure.

[0014] The processing substrate 16 may be made of a semiconductor material, such as single-crystal silicon. The buried insulating layer 14 may be made of a dielectric material (such as silicon dioxide), which is an electrical insulator. The device layer 12 may be separated from and electrically isolated from the processing substrate 16 by the buried insulating layer 14.

[0015] The shallow trench isolation region 18 extends completely through the device layer 12. The shallow trench isolation region 18 can be formed by etching trenches using a patterned hard mask, depositing a dielectric material (e.g., silicon dioxide) in the trenches, and planarizing them by chemical mechanical polishing. The shallow trench isolation region 18 surrounds the active region of the device layer 12, in which a structure for a diode can subsequently be formed.

[0016] In one embodiment, device layer 12 may be composed of a single-crystal semiconductor material (e.g., single-crystal silicon). In an alternative embodiment, device layer 12 in the active region may be modified to add germanium via, for example, a condensation process, such that device layer 12 in the active region is entirely composed of silicon and germanium. In an alternative embodiment, device layer 12 in the active region may be modified to include a combination of silicon and silicon-germanium. For example, germanium may be introduced only into a portion of device layer 12 in the active region.

[0017] In one embodiment, the semiconductor material of device layer 12 in the active region may be intrinsic. In an alternative embodiment, the semiconductor material of device layer 12 in the active region may be lightly doped to provide, for example, p-type conductivity. Doping can be provided by an ion implantation process, such as... Figure 1 The unidirectional arrow in the diagram schematically shows that the dopant concentration can be around 1 × 10⁻⁶. 15 cm -3 To approximately 1×10 17 cm -3 Within a certain range. Additional doping can be used to adjust the performance of the subsequently formed diode.

[0018] refer to Figure 2 The same reference numerals indicate Figure 1 The same features are present in the device layer 12 and the shallow trench isolation region 18, and in subsequent manufacturing stages, dielectric layer 20, gate layer 22, and dielectric layer 24 are formed in a layer stack above the device layer 12 and the shallow trench isolation region 18. Dielectric layer 20 may be made of a dielectric material, such as silicon dioxide. Gate layer 22 may be made of a doped polycrystalline semiconductor material, such as doped polycrystalline silicon. Dielectric layer 24 may be made of a dielectric material, such as silicon nitride.

[0019] refer to Figure 3 The same reference numerals indicate Figure 2 The same features are present in the layer stack, and in subsequent manufacturing stages, layers 20, 22, and 24 can be patterned using photolithography and etching processes. Gate 26 includes a patterned segment of gate layer 22 located above a patterned segment of dielectric layer 20. Gate 26 and the patterned segment of dielectric layer 20 are located above segment 60 of device layer 12. The patterned segment of dielectric layer 20 is located in the vertical direction between gate 26 and segment 60 of device layer 12, and the patterned segment of layer 24 defines a dielectric cap located above gate 26. A dielectric layer 28 made of a dielectric material such as silicon nitride can be conformally deposited after patterning gate 26.

[0020] Segments 60 of device layer 12 are laterally arranged between adjacent segments 62 and 64 of device layer 12, and segments 62 and 64 are opened by patterning layers 20, 22, and 24. Segment 62 of device layer 12 is positioned adjacent to the sidewall 23 of gate 26. Segment 64 of device layer 12 is positioned adjacent to the opposite sidewall 25 of gate 26.

[0021] refer to Figure 4 The same reference numerals indicate Figure 3The same features are incorporated in subsequent manufacturing stages, forming an etching mask 30 and an opening 32 in the etching mask 30 that exposes a portion of the dielectric layer 28 above the segment 64 of the device layer 12. The etching mask 30 may comprise a layer of photoresist applied by a spin-coating process, followed by pre-baking and exposure to light projected through the photomask, post-exposure baking, and development with a chemical developer to define the opening 32. The exposed portion of the dielectric layer 28 is removed by an etching process. The etching mask 30 may be stripped, for example, by ashing.

[0022] refer to Figure 5 The same reference numerals indicate Figure 4 The semiconductor layer 34, exhibiting the same characteristics as in the device layer 12 and subsequently formed in a manufacturing stage, is formed on segment 64 of the device layer 12 and adjacent to the sidewall 25 of the gate 26. The semiconductor layer 34 can be formed by an epitaxial growth process and can be made of a single-crystal semiconductor material (e.g., single-crystal silicon). The epitaxial growth process can be selective in nature, resulting in epitaxial growth from the exposed semiconductor material (e.g., device layer 12) rather than from the dielectric material (e.g., dielectric layers 24, 28). The crystal structure of the single-crystal semiconductor material of the device layer 12 serves as a crystallization template for the epitaxial growth of the semiconductor layer 34. The semiconductor layer 34 can be doped (e.g., heavily doped) during epitaxial growth with a certain concentration of dopant, such as an n-type dopant (e.g., arsenic or phosphorus), to provide n-type conductivity. In one embodiment, the dopant concentration can be greater than 1 × 10⁻⁶. 19 cm -3 The semiconductor layer 34 is raised relative to the top surface 10 of the device layer 12. In one embodiment, the semiconductor layer 34 can provide a raised cathode for the PIN diode.

[0023] refer to Figure 6 The same reference numerals indicate Figure 5 The same features as those in the semiconductor layer 34 can be conformally deposited in subsequent manufacturing stages after the formation of the semiconductor layer 34, forming a dielectric layer 36 of a dielectric material such as silicon nitride. The dielectric layers 28, 36 can be patterned by photolithography and etching processes to expose segments 62 of the device layer 12. For this purpose, an etching mask 44 is applied, and openings 45 of the dielectric layer 36 exposed above the segments 62 of the device layer 12 are formed in the etching mask 44. The etching mask 44 may include a layer of photoresist applied by a spin coating process, then pre-baked and exposed to light projected through the photomask, post-baked, and developed with a chemical developer to define the openings 45. Portions of the dielectric layers 28, 36 aligned with the openings 45 are removed by an etching process to open the segments 62 of the device layer 12. The etching mask 30 can be stripped, for example, by ashing.

[0024] refer to Figure 7 The same reference numerals indicate Figure 6 The semiconductor layer 38, exhibiting the same characteristics as in the device layer 12 and subsequently formed in the manufacturing stage, is formed on segment 62 of the device layer 12 and adjacent to the sidewall 23 of the gate 26. The semiconductor layer 38 can be formed by an epitaxial growth process and can be made of a single-crystal semiconductor material (e.g., single-crystal silicon). The epitaxial growth process can be selective in nature, resulting in epitaxial growth from an exposed semiconductor material (e.g., device layer 12) rather than from a dielectric material such as dielectric layer 36. The crystal structure of the single-crystal semiconductor material of device layer 12 serves as a crystallization template for the epitaxial growth of semiconductor layer 38. Semiconductor layer 38 can be doped (e.g., heavily doped) during epitaxial growth with a certain concentration of dopant, such as a p-type dopant (e.g., boron), to provide p-type conductivity. In one embodiment, the dopant concentration can be greater than 1 × 10⁻⁶. 19 cm -3 The semiconductor layer 38 is raised relative to the top surface 10 of the device layer 12. In one embodiment, the semiconductor layer 38 can provide a raised anode for the PIN diode.

[0025] Gate 26 is laterally located on segment 60 of device layer 12 between semiconductor layers 34 and 38, where semiconductor layers 34 and 38 can respectively provide a raised cathode and a raised anode for the PIN diode. Dielectric layers 28 and 36 are laterally disposed between the sidewalls 23 of semiconductor layer 38 and gate 26 as sidewall spacers. In contrast, only dielectric layer 28 is laterally disposed between the sidewalls 25 of semiconductor layer 34 and gate 26 as sidewall spacers. Therefore, the sidewall spacers between gate 26 and semiconductor layer 38 are thicker than the sidewall spacers between gate 26 and semiconductor layer 34.

[0026] refer to Figure 8 , 9 The same reference numerals indicate Figure 7 The same features are present in the dielectric layer 34 and 38, and in subsequent manufacturing stages, a silicide layer 50 is formed on the semiconductor layers 34 and 38 via a silicide process. Contacts 52 formed in the dielectric layer 54 can be coupled to the semiconductor layers 34 and 38 via the silicide layer 50. In one embodiment, the gate 26 can be non-contact. In one embodiment, the gate 26 can be contacted via contact 53, which is also formed in the dielectric layer 40.

[0027] The device structure can be a PIN diode, comprising a raised cathode (i.e., semiconductor layer 34) and a raised anode (i.e., semiconductor layer 38) as terminals, with a spacer-covered gate 26 laterally positioned between the raised anode and the raised cathode. Dopant can diffuse from semiconductor layer 34 into segment 64 of device layer 12 below semiconductor layer 34 and contribute to the cathode. Dopant can diffuse from semiconductor layer 38 into segment 62 of device layer 12 below semiconductor layer 38 and contribute to the anode. Intrinsic regions are provided in the PIN diode by segment 60 of device layer 12 disposed between the anode and cathode and below gate 26. Semiconductor layer 34 can be heavily doped (e.g., n+), and semiconductor layer 38 can also be heavily doped with a dopant of the opposite conductivity type to semiconductor layer 34 (e.g., p+). Semiconductor layers 34 and 38 are typically heavily doped because, for example, semiconductor layers 34 and 38 can provide ohmic contacts.

[0028] Semiconductor layers 34 and 38 are formed sequentially using different epitaxial growth processes. Device layer 12, in segments 60, 62, and 64 of device layer 12, may comprise silicon, silicon-germanium, or combinations of these semiconductor materials. The gate length (i.e., the length of segment 60 of device layer 12 below gate 26) can be easily adjusted for breakdown voltage regulation by adjusting the lateral dimensions of gate 26. The sidewall spacers between gate 26 and semiconductor layer 38 may be thicker than the sidewall spacers between gate 26 and semiconductor layer 34, facilitated by the different epitaxial growth processes used to form semiconductor layers 34 and 38. Doping in segment 60 of device layer 12 can be adjusted (e.g., by optional ion implantation) to regulate (e.g., reduce) the breakdown voltage.

[0029] Compared to forming a bulk substrate that requires additional wells for device isolation, forming a bipolar junction transistor using a silicon-on-insulator substrate can reduce capacitance during operation. In one embodiment, doped regions in segments 62, 64 of device layer 12 located beneath semiconductor layers 34, 38 can extend across the entire thickness of device layer 12 to the buried insulator layer 14, which can effectively reduce leakage during operation.

[0030] Diode device structures can be integrated with lateral bipolar junction transistors (TLJs) for radio frequency (RF) applications. If the diode fabrication stage is shared with the TLJ formation stage, an additional mask may not be required to form the diode device structure. In this respect, a single additional mask is needed if segment 60 of device layer 12 is injected for breakdown voltage regulation.

[0031] refer to Figure 10 The same reference numerals indicate Figure 5The same features as in the alternative embodiment, and in subsequent manufacturing stages, allow the dielectric layer 28 to be patterned and removed from the segment 62 of the device layer 12 adjacent to the sidewall 23 of the gate 26 after the semiconductor layer 34 is formed. For this purpose, an etch mask 48 is applied and an opening 49 is formed in the etch mask 48, exposing the dielectric layer 28 above the segment 62 of the device layer 12. The exposed portion of the dielectric layer 28 can be etched and removed to expose the segment 62 of the device layer 12. The etch mask 48 may comprise a layer of photoresist applied by a spin-coating process, then pre-baked and exposed to light projected through the photomask, post-baked, and developed with a chemical developer to define the opening 49. The exposed dielectric layer 28 is removed by an etching process. The etch mask 48 can be stripped, for example, by ashing.

[0032] refer to Figure 11 The same reference numerals indicate Figure 10 The same features are present in the semiconductor layer 34 that provides the raised cathode of the Schottky barrier diode, and in subsequent manufacturing stages, a silicide layer 50 is formed by a silicide process on the semiconductor layer 34 that provides the cathode of the Schottky barrier diode and also on the open segment 62 of the device layer 12. The silicide layer 50 and the segment 62 of the device layer 12 located below the silicide layer 50 define the anode of the Schottky barrier diode. The segment 62 of the device layer 12, which can be thinned by silicide formation, is in physical and electrical contact with the silicide layer 50 and is located in the vertical direction between the silicide layer 50 and the buried insulating layer 14.

[0033] In addition to the anode, the diode structure includes a semiconductor layer 34 serving as the raised cathode of the Schottky barrier diode. A gate 26 is laterally positioned on device layer 12 between the anode and the raised cathode of the Schottky barrier diode. A contact 52 is coupled to both the anode and the raised cathode. In one embodiment, the gate 26 may be contactless. In another embodiment, the gate 26 may be in contact with a contact 53 also formed in the dielectric layer 40.

[0034] A Schottky barrier diode may include a Schottky contact defining an anode at the interface between the silicide layer 50 and the device layer 12. The Schottky barrier diode includes a raised cathode (i.e., semiconductor layer 34) as one of the terminals of the Schottky barrier diode. In one embodiment, the raised cathode may be heavily doped (e.g., n+). The gate length (i.e., the length of segment 60 of device layer 12 below gate 26) may be adjusted for breakdown voltage regulation. Segments 60, 62, and 64 of device layer 12 may include silicon, silicon-germanium, or combinations of these semiconductor materials.

[0035] refer to Figure 12According to an alternative embodiment, the back gate 56 may be formed in the processing substrate 16. In one embodiment, the back gate 56 may extend laterally below the anode, cathode, and gate of the Schottky barrier diode. The back gate 56 may be embodied in a doped region formed in the processing substrate 16 by a masked ion implantation process. A bulk contact 55 may be formed extending through the buried insulating layer 14 to the back gate 56.

[0036] During operation 11, a bias voltage can be applied to the back gate 56 via the body contact 55. The bias voltage can be selected to adjust performance parameters of the Schottky barrier diode, such as on-resistance and / or breakdown voltage. In an alternative embodiment, the back gate 56 can be added to a device structure for a PIN diode.

[0037] refer to Figure 13 The same reference numerals indicate Figure 11 With the same features as described above and according to an alternative embodiment, a guard ring 58 can be formed as a boundary region in a segment 62 of the device layer 12 beneath the silicide layer 50. The guard ring 58 can be laterally positioned in the segment 62 of the device layer 12 adjacent to the interface between the device layer 12 and the shallow trench isolation region 18. The guard ring 58 can be formed by introducing a dopant into a portion of the segment 62 of the device layer 12 over which the silicide layer 50 is formed using a masked ion implantation process. In one embodiment, the guard ring 58 can be heavily doped with a p-type dopant compared to the intrinsic or lightly doped semiconductor material of the remaining portion of the segment 62 of the device layer 12. The guard ring 58 can effectively reduce device leakage in operating devices.

[0038] The method described above is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. The chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of intermediate or final products. The final product can be any product that includes integrated circuit chips, such as a computer product with a central processing unit or a smartphone.

[0039] References to terms modified by approximate language such as “approximately,” “roughly,” and “basically” are not limited to the specified precise values. Approximate language may correspond to the precision of the instrument used to measure the value and may indicate a range of + / -10% of the value unless dependent on the precision of the instrument.

[0040] The use of terms such as “vertical” and “horizontal” in this document is illustrative rather than restrictive, in order to establish a frame of reference. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. As just defined, the terms “vertical” and “normal” refer to directions perpendicular to the horizontal. The term “lateral” refers to a direction within the horizontal plane.

[0041] A feature that is “connected” or “coupled” to or with another feature can be directly connected or coupled to or coupled to another feature; conversely, one or more intermediate features may exist. If no intermediate features exist, a feature can be “indirectly connected” or “indirectly coupled” to or coupled to another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to or coupled to another feature. A feature that is “located on” or “in contact with” another feature can be directly located on or in direct contact with another feature; conversely, one or more intermediate features may exist. If no intermediate features exist, a feature can be “directly located on” or “in direct contact with” another feature. If at least one intermediate feature exists, a feature can be “indirectly located on” or “indirectly in contact with” another feature. If a feature extends above and covers a portion of another feature, the different features “overlap.”

[0042] Various embodiments of the present invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a diode, the structure comprising: A layer made of semiconductor material, the layer comprising a first segment, a second segment, and a third segment laterally positioned between the first segment and the second segment; A first terminal includes a first raised semiconductor layer located on the first segment of the layer; The second terminal has a portion located on the second segment of the layer; as well as The gate is located on the third segment of the layer. The third segment of the layer comprises intrinsic semiconductor material.

2. The structure according to claim 1, wherein, The portion of the second terminal is a second raised semiconductor layer on the second segment of the layer.

3. The structure according to claim 2, wherein, The first raised semiconductor layer contains an n-type dopant, and the second raised semiconductor layer contains a p-type dopant.

4. The structure according to claim 1, wherein, The portion of the second terminal is a silicide layer on the second segment of the layer.

5. The structure according to claim 4, further comprising: The boundary region is located in the second segment of the layer and below the silicide layer.

6. The structure according to claim 5, further comprising: The shallow trench isolation zone passes through the layer. The boundary region is located in the second segment of the layer adjacent to the shallow trench isolation region.

7. The structure according to claim 5, wherein, The first and second segments of the layer comprise intrinsic semiconductor materials or lightly doped semiconductor materials, and the semiconductor material of the layer in the boundary region comprises heavily doped semiconductor materials.

8. The structure according to claim 1, wherein, The layer is a device layer on a silicon-on-insulator substrate, and the structure further includes: Processed substrate; and A buried insulating layer separates the device layer from the processing substrate.

9. The structure according to claim 8, further comprising: A back gate is located in the processing substrate below the first terminal, the second terminal, and the gate.

10. The structure according to claim 8, wherein, The device layer has a thickness ranging from 4 nanometers to 100 nanometers.

11. The structure according to claim 8, wherein, The portion of the second terminal is a silicide layer on the second segment of the layer, and the second segment of the device layer is located between the silicide layer and the buried insulator layer.

12. The structure according to claim 1, wherein, The layer comprises silicon, silicon germanium, or a combination thereof.

13. The structure according to claim 1, further comprising: The first contact is connected to the first terminal; as well as The second contact is connected to the second terminal. The gate is non-contact.

14. The structure according to claim 1, wherein, The first terminal, the second terminal, and the gate are laterally positioned on the layer.

15. A method of manufacturing a structure for a diode, the method comprising: A first terminal is formed, the first terminal including a first raised semiconductor layer located on a first segment of a layer made of semiconductor material; A second terminal is formed, the second terminal including a portion located on a second segment of the layer; as well as A gate is formed on the third segment of the layer. The third segment of the layer is laterally positioned between the first segment and the second segment of the layer. The third segment of the layer comprises intrinsic semiconductor material.

16. The method according to claim 15, wherein, The second terminal, comprising the portion located on the second segment of the layer, includes: A second raised semiconductor layer is formed on the second segment of the layer.

17. The method according to claim 16, wherein, The first raised semiconductor layer contains an n-type dopant, and the second raised semiconductor layer contains a p-type dopant.

18. The method according to claim 15, wherein, The second terminal, comprising the portion located on the second segment of the layer, includes: A silicide layer is formed on the second segment of the layer.

19. The method of claim 18, further comprising: A protective ring is formed in the second segment of the layer located below the silicide layer.

20. The method of claim 15, wherein, The layer is a device layer on a silicon-on-insulator substrate, and the silicon-on-insulator substrate further includes a processing substrate and a buried insulator layer that separates the device layer from the processing substrate.

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