Packaging structure, antenna module and probe card

Abstract

This invention discloses a packaging structure, an antenna module, and a probe card. The packaging structure includes a connecting member and a first redistribution structure disposed on the connecting member. The connecting member includes a connector and an insulating layer surrounding the connector. The first redistribution structure includes a first dielectric layer, a first wiring pattern, and a first element. The first dielectric layer is disposed on the connecting member. The first wiring pattern is disposed in the first dielectric layer. The first element is disposed above the first dielectric layer and electrically connected to the connector.

Description

Technical Field

[0001] This invention relates to a packaging structure, an antenna module, and a probe card. Background Technology

[0002] In recent years, electronic products have become increasingly important to people's lives. To achieve thin, light, and compact designs, semiconductor packaging technology has also advanced rapidly, developing products that meet requirements for small size, light weight, high density, and high market competitiveness. Furthermore, to accelerate the integration of various functions, the industry now mostly adopts two methods: component embedding or chip embedding, integrating chips with active and passive components onto the circuit board (system carrier) to achieve high efficiency, low power consumption, and small size.

[0003] However, as demands for electronic products shift towards smaller size, higher functionality, faster signal transmission, and higher circuit density, existing electronic products can no longer meet current or future needs in terms of performance and size. For example, current communication paths between components (such as the communication path between chips and active / passive components) are relatively long, resulting in greater signal loss; active / passive components occupy a large area, preventing the integration of more integrated circuits; or the thickness of active / passive components is difficult to reduce, hindering the reduction of electronic product size. Summary of the Invention

[0004] An embodiment of the present invention provides an encapsulation structure including a connecting member and a first redistribution structure. The connecting member includes a connector and an insulating layer surrounding the connector. The first redistribution structure is disposed on the connecting member and includes a first dielectric layer, a first wiring pattern, and a first element. The first dielectric layer is disposed on the connecting member. The first wiring pattern is disposed in the first dielectric layer. The first element is disposed above the first dielectric layer and electrically connected to the connector.

[0005] An embodiment of the present invention provides an antenna module including a connecting member, a redistribution structure, and a chip. The connecting member includes a connector and an insulating layer surrounding the connector. The redistribution structure is disposed on a first side of the connecting member and includes a first wiring pattern, a first dielectric layer, and an antenna element. The first wiring pattern is disposed on the connecting member and electrically connected to the connector. The first dielectric layer is disposed on the connecting member and covers the first wiring pattern. The antenna element is disposed above the first dielectric layer and configured to transmit and / or receive signals, wherein the antenna element is electrically connected to the first wiring pattern. The chip is disposed above a second side of the connecting member opposite to the first side, wherein the chip is electrically connected to the antenna element.

[0006] An embodiment of the present invention provides a probe card including a connecting member, a first redistribution structure, conductive probes, and a substrate. The connecting member includes a connector and an insulating layer surrounding the connector. The first redistribution structure is disposed on a first side of the connecting member and includes a first dielectric layer, a first wiring pattern, and a first element. The first dielectric layer is disposed on the connecting member. The first wiring pattern is disposed in the first dielectric layer. The first element is disposed above the first dielectric layer and electrically connected to the connector. The conductive probe is disposed above the first redistribution structure and electrically connected to the first element. The substrate is disposed on a second side of the connecting member opposite to the first side, and the wiring pattern in the substrate is electrically connected to the first element in the first redistribution structure via the connecting member.

[0007] Based on the above, the packaging structure, antenna module, and probe card in the above embodiments can reduce the communication path length between components and reduce the occupied area of ​​active / passive components by integrating the first component (e.g., an active component or a passive component) into the design of the first redistribution structure, thereby helping to improve component performance and reduce component size. Attached Figure Description

[0008] Figure 1a This is a cross-sectional schematic diagram of the packaging structure according to the first embodiment of the present invention;

[0009] Figure 1b yes Figure 1a An enlarged schematic diagram of region A1 in the diagram;

[0010] Figure 1c yes Figure 1b A cross-sectional schematic diagram of an embodiment of the first element D1;

[0011] Figure 1d yes Figure 1b A top view schematic diagram of an embodiment of the second element D2;

[0012] Figure 2a This is a cross-sectional schematic diagram of the packaging structure according to the second embodiment of the present invention;

[0013] Figure 2b yes Figure 2a An enlarged schematic diagram of region A2 in the image;

[0014] Figure 3a This is a cross-sectional schematic diagram of the packaging structure according to the third embodiment of the present invention;

[0015] Figure 3b yes Figure 3a An enlarged view of region A3 in the diagram;

[0016] Figure 4a This is a cross-sectional schematic diagram of the packaging structure according to the fourth embodiment of the present invention;

[0017] Figure 4b yes Figure 4a An enlarged view of region A4 in the diagram;

[0018] Figure 5a This is a cross-sectional schematic diagram of the packaging structure according to the fifth embodiment of the present invention;

[0019] Figure 5b yes Figure 5a An enlarged view of region A5 in the diagram;

[0020] Figure 6a This is a cross-sectional schematic diagram of the packaging structure according to the sixth embodiment of the present invention;

[0021] Figure 6b yes Figure 6a An enlarged view of region A6 in the diagram;

[0022] Figure 7a This is a cross-sectional schematic diagram of the packaging structure according to the seventh embodiment of the present invention;

[0023] Figure 7b yes Figure 7a An enlarged view of region A7 in the diagram;

[0024] Figure 8a This is a cross-sectional schematic diagram of the packaging structure according to the eighth embodiment of the present invention;

[0025] Figure 8b yes Figure 8a An enlarged view of region A8 in the diagram;

[0026] Figure 9a This is a cross-sectional schematic diagram of the packaging structure according to the ninth embodiment of the present invention;

[0027] Figure 9b yes Figure 9a An enlarged view of region A9 in the diagram;

[0028] Figure 10a This is a cross-sectional schematic diagram of the packaging structure according to the tenth embodiment of the present invention;

[0029] Figure 10b yes Figure 10a An enlarged schematic diagram of region A10 in the image;

[0030] Figure 11a This is a cross-sectional schematic diagram of the packaging structure according to the eleventh embodiment of the present invention;

[0031] Figure 11b yes Figure 11a An enlarged schematic diagram of region A11 in the image;

[0032] Figure 12a This is a cross-sectional schematic diagram of the packaging structure according to the twelfth embodiment of the present invention;

[0033] Figure 12b yes Figure 12a An enlarged schematic diagram of region A12 in the image;

[0034] Figure 13a This is a cross-sectional schematic diagram of the packaging structure according to the thirteenth embodiment of the present invention;

[0035] Figure 13b yes Figure 13a An enlarged schematic diagram of region A13 in the image;

[0036] Figure 14a This is a cross-sectional schematic diagram of the packaging structure according to the fourteenth embodiment of the present invention;

[0037] Figure 14b yes Figure 14a An enlarged view of region A14 in the diagram;

[0038] Figure 15 This is a cross-sectional schematic diagram of the packaging structure according to the fifteenth embodiment of the present invention. Detailed Implementation

[0039] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0040] The invention is illustrated more fully with reference to the accompanying drawings of the embodiments. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0041] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may mean that there are other elements between the two elements.

[0042] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned values ​​and specific values ​​within an acceptable range of deviation that can be determined by one of ordinary skill in the art, taking into account the measurement under discussion and the specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties, selecting a more acceptable range of deviations or standard deviations, rather than applying a single standard deviation to all properties.

[0043] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.

[0044] Figure 1a This is a cross-sectional schematic diagram of the packaging structure according to the first embodiment of the present invention. Figure 1b yes Figure 1a An enlarged schematic diagram of region A1 in the image. Figure 1c yes Figure 1b A cross-sectional schematic diagram of an embodiment of the first element D1. Figure 1d yes Figure 1b A top view schematic diagram of an embodiment of the second element D2.

[0045] Please refer to Figure 1a The packaging structure 1000 may include a connecting member 100a, a redistribution structure 200A, a redistribution structure 300, and an integrated circuit structure 400.

[0046] The connecting member 100a includes a connector 102 and an insulating layer 104 surrounding the connector 102. In some embodiments, the connector 102 may include an electrical connection structure 102a, a pad 102b, and a pad 102c. Pad 102b connects one end of the electrical connection structure 102a to the redistribution structure 200A. Pad 102c connects the other end of the electrical connection structure 102a to the redistribution structure 300.

[0047] In some embodiments, the electrical connection structure 102a may include solders such as tin, tin-lead, gold, silver, tin-silver, tin-bismuth, copper, copper-tin, copper-tin-silver, copper-nickel-tin-silver, palladium, indium, nickel, nickel-palladium-gold, nickel-gold, similar materials, or combinations thereof. In some embodiments, pads 102b and 102c may include conductive materials such as metals. For example, pads 102b and 102c may include metals such as copper, nickel, titanium, tungsten, aluminum, or the like. In some embodiments, pad 102b may be formed, for example, on the surface adjacent to the connecting member 100a in the redistribution structure 200A, while pad 102c may be formed, for example, on the surface adjacent to the connecting member 100a in the redistribution structure 300. In this embodiment, the electrical connection structure 102a may be formed in the following manner. First, a solder layer is formed on one of pads 102b and 102c using methods such as vapor deposition, electroplating, printing, solder transfer, balling, or similar methods. Next, a reflow is performed to shape the material into the desired bump solder. Then, the other of pads 102b and 102c is brought into contact with the aforementioned bump solder and subsequently reflowed to form an electrical connection structure 102a. That is, the electrical connection structure 102a can be a solder joint between pads 102b and 102c, thereby connecting the redistribution structure 200A to the redistribution structure 300. An insulating layer 104 reduces stress and protects the electrical connection structure 102a. In some embodiments, the insulating layer 104 can be an underfill.

[0048] In other embodiments, the connecting member 100a may be an add-on circuit structure. For example, the connector 102 may be a conductive via penetrating the insulating layer 104. When the connecting member 100a is an add-on circuit structure, the connector 102 may be formed, for example, by forming a plurality of through holes (not shown) in the insulating layer 104 by laser drilling. Then, for example, a conductive via is formed in the through holes by electroplating.

[0049] The redistribution structure 300 may include a redistribution layer 302 and an insulating layer 304, wherein the redistribution layer 302 may be formed in the insulating layer 304. In some embodiments, the redistribution layer 302 may include vias and / or wiring layers. The vias may extend through the insulating layer 304, while the wiring layers may extend along the insulating layer 304. The vias and / or wiring layers may include conductive materials. The conductive materials may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. In some embodiments, the insulating layer 304 may be formed of a polymer. The polymer may be, for example, a photosensitive material patterned using a photomask, such as PBO, polyimide, BCB-based polymers, or the like. In other embodiments, the insulating layer 304 may be formed of: nitrides, such as silicon nitride; oxides, such as silicon oxide, PSG, BSG, BPSG; or similar materials. In this embodiment, the insulating layer 304 may be formed by spin coating, stacking, CVD, similar processes, or combinations thereof.

[0050] The integrated circuit structure 400 may include an integrated circuit 402 and an insulating layer 404 surrounding the integrated circuit 402. The integrated circuit 402 may include a radio frequency chip (RF chip). The insulating layer 404 may be, for example, an epoxy molding compound (EMC). The redistribution structure 300 may be electrically connected to the integrated circuit structure 400.

[0051] Please refer to Figure 1a and Figure 1b A redistribution structure 200A is disposed on the connecting member 100a. In some embodiments, the redistribution structure 200A may include a first redistribution structure. The first redistribution structure may include a first dielectric layer 201, a first wiring pattern 202, and a first element D1. The first dielectric layer 201 may be disposed on the connecting member 100a. The first wiring pattern 202 may be disposed in the first dielectric layer 201. The first element D1 may be disposed above the first dielectric layer 201 and electrically connected to a connector 102 of the connecting member 100a. The first element D1 may be electrically connected to the integrated circuit 402 through the first wiring pattern 202, the connecting member 100a, and the redistribution structure 300. That is, the first element D1 may be integrated into the first redistribution structure of the redistribution structure 200A to reduce the communication path length between components and reduce the area occupied by the first element D1, thereby helping to improve the performance of the package structure 1000 and reduce the size of the package structure 1000. The first element D1 may include an active element, a passive element, or a combination thereof. For example, the first element D1 may include a capacitor, a resistor, an inductor, a filter, an antenna, or a combination thereof.

[0052] In some embodiments, the first redistribution structure of the redistribution structure 200A may include a plurality of dummy patterns 204 disposed in the first dielectric layer 201. In some embodiments, the dummy patterns 204 may be electrically isolated from the connector 102 of the connecting member 100a. The dummy patterns 204 may adjust the flatness of the surface of the first dielectric layer 201 away from the dummy pattern 204. For example, see... Figure 1b and Figure 1c When the first element D1 includes a capacitor structure, the dummy pattern 204 can be configured to adjust the flatness of the first dielectric layer 201 to a range of about 40% to about 60%, such that the first dielectric layer 201 includes a protrusion on the dummy pattern 204 and a recess between two adjacent dummy patterns 204. In other words, the first dielectric layer 201 can have a trench structure (also referred to as a self-forming trench structure) without the need for an additional trench forming process. As a result, the capacitor (i.e., the first element D1) formed on the protrusions and recesses of the first dielectric layer 201 can have an improved effective capacitor area, thereby reducing the area occupied by the first element D1 in the package structure 1000. In some embodiments, the area occupied by the first element D1 in the package structure 1000 can be reduced by about 10% to about 30% through the above design.

[0053] In some embodiments, the flatness of the first dielectric layer 201 can be calculated using the following formula 1a:

[0054] [Equation 1a]

[0055] Flatness (DOP1) = [1 - (h1 / T1)] × 100%

[0056] In Equation 1a, DOP1 represents the flatness of the first dielectric layer 201; h1 represents the difference between the highest and lowest heights of the top surface of the first dielectric layer 201; and T1 represents the thickness of the pattern covered by the first dielectric layer 201 (e.g., the thickness of the dummy pattern 204 or the thickness of the first wiring pattern 202).

[0057] In some embodiments, the ratio T1 / h1 of the thickness T1 of the pattern covered by the first dielectric layer 201 to the thickness h1 of the first dielectric layer 201 can be, for example, between 1 / 1.1 and 1 / 1.6. In some embodiments, in order to control the flatness of the first dielectric layer 201 to about 40%, Table 1 below shows the pattern width and the ratio of pattern width to pattern spacing corresponding to different thicknesses of the pattern covered by the first dielectric layer 201. In Table 1, the width of the pattern covered by the first dielectric layer 201 is L1, and the spacing of the pattern covered by the first dielectric layer 201 is S1.

[0058] Table 1

[0059]

[0060] The capacitor structure may include a first electrode E1, a dielectric HK, and a second electrode E2. The first electrode E1 may be disposed on the surface of the recess and the raised portion of the first dielectric layer 201. The dielectric HK may be disposed on the first electrode E1. The second electrode E2 may be disposed on the dielectric HK. The first electrode E1 and / or the second electrode E2 may include a conductive material. In some embodiments, the first electrode E1 and / or the second electrode E2 may include a conductive material forming wiring in the redistribution structure, such as metallic materials like Ti and Cu. That is, the fabrication process for forming the first electrode E1 and / or the second electrode E2 may be integrated into the fabrication process for the wiring layer forming the redistribution structure. The dielectric HK may include a dielectric with a high dielectric constant. For example, the material of the dielectric HK may be a high dielectric constant material or a combination thereof with a dielectric constant greater than 4, greater than 7, or even greater than 10. High dielectric constant materials are, for example, metal oxides. For example, the metal oxide can be a rare earth metal oxide, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi2Ta2O9, SBT), or combinations thereof.

[0061] In some embodiments, the first redistribution structure may include a wiring layer 206 disposed on the first dielectric layer 201 and electrically connected to the first wiring pattern 202. In some embodiments, the wiring layer 206 may be electrically connected to a capacitor structure. In some embodiments, the fabrication process for forming the capacitor structure may be integrated into the fabrication process for forming the wiring layer 206. For example, the fabrication process for forming the first electrode E1 and / or the second electrode E2 in the capacitor structure may be integrated into the fabrication process for forming the wiring layer 206.

[0062] In some embodiments, the capacitor structure may include a compensation structure 208 disposed on the second electrode E2 and filling the recess of the first dielectric layer 201 to adjust the flatness of the film layer (e.g., the second dielectric layer 203) formed thereon. In some embodiments, the compensation structure 208 includes a conductive material such as a metal.

[0063] In some embodiments, the redistribution structure 200A may further include a second redistribution structure disposed on the first redistribution structure. The second redistribution structure may include a second dielectric layer 203, a plurality of second wiring patterns 210, and a second element D2. The second dielectric layer 203 may be disposed on the first dielectric layer 201 and cover the wiring layer 206 and the first element D1. The second wiring patterns 210 may include vias disposed in the second dielectric layer 203 and wiring layers disposed on the second dielectric layer 203. The second element D2 may be disposed on a portion of the second dielectric layer 203 below which a compensation structure 208 is provided and electrically connected to the first element D1. The second element D2 may include a capacitor, resistor, inductor, filter, antenna, or a combination thereof.

[0064] In some embodiments, please refer to Figure 1b and Figure 1d When the second element D2 includes an inductor structure, the compensation structure 208 ensures that the flatness of the second dielectric layer 203 located on the compensation structure 208 is greater than approximately 95%. In this way, the inductor structure disposed on the portion below the second dielectric layer 203 where the compensation structure 208 is located can avoid electrical abnormalities caused by unevenness in the wiring pattern. In some embodiments, the fabrication process for forming the inductor structure can be integrated into the fabrication process for forming the wiring layer in the second redistribution structure. For example, the second redistribution structure may include a wiring layer 212 and a wiring layer 214 formed on the second wiring pattern 210, wherein the wiring layer 212 is disposed around the wiring layer 214 and includes a portion electrically connected to the second wiring pattern 210, and the wiring layer 214 may be formed as follows: Figure 1d The pattern shown serves as an inductor structure. In some embodiments, the wiring layer 212 may include portions electrically connected to a capacitor structure (i.e., the first element D1) and portions electrically connected to an inductor structure (i.e., the second element D2). In some embodiments, the portions of the wiring layer 212 electrically connected to the capacitor structure are spaced at least 10 μm from the inductor structure (i.e., the second element D2) to reduce inductance losses. For example, when the first element D1 is a capacitor structure and the second element D2 is an inductor structure, the portions of the wiring layer 212 electrically connected to the first element D1 (e.g., the second element D2) are spaced at least 10 μm apart. Figure 1b The portion of the wiring layer 212 located to the right of the second element D2 is horizontally spaced at least 10 μm from the inductor structure (i.e., the second element D2) (e.g., from a top-down view).

[0065] In some embodiments, the flatness of the second dielectric layer 203 can be calculated using the following formula 1b:

[0066] [Equation 1b]

[0067] Flatness (DOP2) = [1 - (h2 / T2)] × 100%

[0068] In Equation 1b, DOP2 represents the flatness of the second dielectric layer 203; h2 represents the difference between the highest and lowest heights of the top surface of the second dielectric layer 203; and T2 represents the thickness of the pattern covered by the second dielectric layer 203 (e.g., the thickness of the wiring layer 206).

[0069] In some embodiments, the ratio T2 / h2 of the thickness T2 of the pattern covered by the second dielectric layer 203 to the thickness h2 of the second dielectric layer 203 may be, for example, between 1 / 1.1 and 1 / 1.6. In some embodiments, in order to control the flatness to be greater than about 95%, Table 2 below shows the pattern width and the ratio of pattern width to pattern spacing corresponding to different thicknesses of the pattern covered by the second dielectric layer 203. In Table 2, the width of the pattern covered by the second dielectric layer 203 is L2, and the spacing of the pattern covered by the second dielectric layer 203 is S2.

[0070] Table 2

[0071]

[0072] In some embodiments, the second redistribution structure of the redistribution structure 200A may include a third dielectric layer 205, a third wiring pattern 216, pads 218, and solder balls 220. The third dielectric layer 205 may cover the second element D2 and the second wiring pattern 210. The third wiring pattern 216 may include vias formed in the third dielectric layer 205 and wiring layers formed on the third dielectric layer 205. In some embodiments, the third wiring pattern 216 may be electrically connected to the second wiring pattern 210 through the wiring layer 212. Pads 218 may be formed on and electrically connected to the third wiring pattern 216. Solder balls 220 may be formed on and electrically connected to the pads 218.

[0073] Figure 2a This is a cross-sectional schematic diagram of the packaging structure according to the second embodiment of the present invention. Figure 2b yes Figure 2a An enlarged schematic diagram of region A2 in the image. Figure 2a The package structure 1100 shown is... Figure 1a The package structure shown is similar to 1000, the main difference being that the redistribution structure 200B of package structure 1100 does not include... Figure 1aThe second element D2 shown is represented by the same or similar element symbols for other identical or similar components / films / patterns, which will not be repeated here.

[0074] Please refer to Figure 2a and Figure 2b The redistribution structure 200B in the encapsulation structure 1100 is disposed on the connecting member 100a and may include a first redistribution structure. The first redistribution structure may include the aforementioned first dielectric layer 201, first wiring pattern 202, first element D1, dummy pattern 204, and wiring layer 206. These components have been described in detail above and will not be repeated here.

[0075] In some embodiments, the redistribution structure 200B may further include a second redistribution structure disposed on the first redistribution structure. The second redistribution structure may include a second dielectric layer 203, a plurality of second wiring patterns 211, a third wiring pattern 216, pads 218, and solder balls 220. The second dielectric layer 203 may be disposed on the first dielectric layer 201 and cover the wiring layer 206. The second wiring patterns 211 may be disposed in the second dielectric layer 203 and electrically connected to the wiring layer 206. The third wiring pattern 216 may be electrically connected to the second wiring pattern 211 and may include vias disposed in the second dielectric layer 203 and wiring layers disposed on the second dielectric layer 203.

[0076] Figure 3a This is a cross-sectional schematic diagram of the packaging structure according to the third embodiment of the present invention. Figure 3b yes Figure 3a An enlarged schematic diagram of region A3 in the image. Figure 3a The package structure 1200 shown is... Figure 1a The package structure shown is similar to the package structure 1000. The main difference is that the redistribution structure 200C of the package structure 1200 includes first elements D1a, D1b, and D1c applied to different circuit regions. Other identical or similar components / films / patterns are represented by the same or similar element symbols, which will not be repeated here.

[0077] Please refer to Figure 3a and Figure 3b The redistribution structure 200C in the package structure 1200 may be disposed on the connecting member 100a and may include first elements D1a, D1b, D1c and second wiring pattern 213 applied to different circuit regions, as well as the aforementioned first dielectric layer 201, first wiring pattern 202, second dielectric layer 203, dummy pattern 204, third wiring pattern 216, pad 218 and solder ball 220. The aforementioned components have been described in detail above and will not be repeated here.

[0078] First elements D1a, D1b, and D1c may be disposed above the first dielectric layer 201. The second wiring pattern 213 may include vias disposed in the first dielectric layer 201, wiring layers disposed on the first dielectric layer 201, and vias and wiring layers disposed in the second dielectric layer 203. In some embodiments, the fabrication process for forming the first elements D1a, D1b, and D1c may be integrated into the fabrication process for forming the second wiring pattern 213. For example, the first elements D1a, D1b, or D1c may be, for instance, high-frequency elements formed by wiring in the second wiring pattern 213. In some embodiments, the first elements D1a, D1b, and D1c may be configured in different circuit regions of the redistribution structure 200C. For example, the first element D1a may be configured in a fan-out circuit region; the first element D1b may be configured in a matching circuit region; and the first element D1c may be configured in a millimeter-wave circuit region.

[0079] In some embodiments, the dummy pattern 204 is disposed in the first dielectric layer 201 and can be configured such that the flatness of the first dielectric layer 201 is greater than about 95%. In this way, the first elements D1a, D1b and D1c disposed on the portion of the first dielectric layer 201 under which the dummy pattern 204 is disposed can avoid electrical abnormalities caused by unevenness of the circuit pattern.

[0080] Figure 4a This is a cross-sectional schematic diagram of the packaging structure according to the fourth embodiment of the present invention. Figure 4b yes Figure 4a An enlarged view of region A4 in the diagram. Figure 4a The package structure 1300 shown is... Figure 3a The encapsulation structure 1200 shown is similar, but the main difference is that the first dielectric layer 201 of the redistribution structure 200D in the encapsulation structure 1300 is a planarization layer (hereinafter referred to as planarization layer 201), so it can be omitted to form a dummy pattern 204. Other identical or similar components / films / patterns are represented by identical or similar element symbols, and will not be repeated here.

[0081] Please refer to Figure 4a and Figure 4bThe first elements D1a, D1b, and D1c may be disposed on the planarization layer 201. The second wiring pattern 213 may include vias disposed in the planarization layer 201 and wiring layers disposed on the planarization layer 201, as well as vias and wiring layers disposed in the second dielectric layer 203. In this embodiment, the material of the planarization layer 201 may be different from the material of the second dielectric layer 203. In some embodiments, the fabrication process for forming the first elements D1a, D1b, and D1c may be integrated into the fabrication process for forming the second wiring pattern 213. For example, the first elements D1a, D1b, or D1c may be, for example, high-frequency elements composed of wiring in the second wiring pattern 213. In some embodiments, the first elements D1a, D1b, and D1c may be configured in different circuit regions in the redistribution structure 200C. For example, the first element D1a may be configured in the fan-out circuit region; the first element D1b may be configured in the matching circuit region; and the first element D1c may be configured in the millimeter-wave circuit region.

[0082] In some embodiments, the flatness of the planarization layer 201 is greater than about 95%, which allows the first elements D1a, D1b and D1c disposed on the planarization layer 201 to avoid electrical abnormalities caused by uneven circuit patterns.

[0083] Figure 5a This is a cross-sectional schematic diagram of the packaging structure according to the fifth embodiment of the present invention. Figure 5b yes Figure 5a An enlarged schematic diagram of region A5 in the image. Figure 5a The package structure 1400 shown is... Figure 1a The encapsulation structure 1000 shown is similar, but the main difference lies in the fact that the first element D11 and the second element D22 in the redistribution structure 200E of the encapsulation structure 1400 are different from the first element D1 and the second element D2 in the redistribution structure 200A of the encapsulation structure 1000. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0084] Please refer to Figure 5a and Figure 5bA redistribution structure 200E is disposed on the connecting member 100a. In some embodiments, the redistribution structure 200E may include a first redistribution structure. The first redistribution structure may include a first dielectric layer 201, a first wiring pattern 202, and a first element D11. The first dielectric layer 201 may be disposed on the connecting member 100a. The first wiring pattern 202 may be disposed in the first dielectric layer 201. The first element D11 may be disposed above the first dielectric layer 201 and electrically connected to a connector 102 of the connecting member 100a. The first element D11 may be electrically connected to the integrated circuit 402 through the first wiring pattern 202, the connecting member 100a, and the redistribution structure 300. That is, the first element D11 may be integrated into the first redistribution structure to reduce the communication path length between components and reduce the area occupied by the first element D11, thereby helping to improve the performance of the package structure 1400 and reduce the size of the package structure 1400.

[0085] In some embodiments, the first redistribution structure of the redistribution structure 200E may include a plurality of dummy patterns 204 disposed in the first dielectric layer 201 and a wiring layer 206 disposed on the first dielectric layer 201 and electrically connected to the first wiring pattern 202. In some embodiments, the dummy patterns 204 may be electrically isolated from the connector 102 of the connecting member 100a. The dummy patterns 204 may adjust the flatness of the first dielectric layer 201. For example, when the first element D11 includes an inductor structure, the dummy patterns 204 may be configured to adjust the flatness of the first dielectric layer 201 to greater than about 95%, so that the inductor structure (i.e., the first element D11) disposed on the first dielectric layer 201 can avoid electrical abnormalities caused by unevenness in the circuit pattern. In some embodiments, the fabrication process for forming the inductor structure may be integrated into the fabrication process for forming the wiring layer 206. For example, the wiring layer 206 may include wiring 206a and wiring 206b formed on the first dielectric layer 201. Wiring 206a may be disposed around wiring 206b and include a portion electrically connected to the first wiring pattern 202. Wiring 206b may be formed as described above. Figure 1d The pattern shown is used as an inductor structure.

[0086] In some embodiments, the redistribution structure 200E may further include a second redistribution structure disposed on the first redistribution structure. The second redistribution structure may include a second dielectric layer 203, a second wiring pattern 210, and a second element D22. The second dielectric layer 203 may be disposed on the first dielectric layer 201 and cover the wiring layer 206. The second element D22 may be disposed on the portion of the second dielectric layer 203 below the portion where the first element D11 is located and is electrically connected to the first element D11.

[0087] In some embodiments, the pattern of the wiring 206b used to form the first element D11 can adjust the flatness of the second dielectric layer 203. For example, when the second element D22 includes a capacitor structure, the wiring 206b can be configured to adjust the flatness of the second dielectric layer 203 to a range of about 40% to about 60%, such that the second dielectric layer 203 includes protrusions on the wiring 206b and recesses between adjacent patterns in the wiring 206b. In other words, the second dielectric layer 203 can have a trench structure (also referred to as a self-forming trench structure) without requiring an additional trench forming process. In this way, the capacitor structure (i.e., the second element D22) formed on the protrusions and recesses of the second dielectric layer 203 can have an improved effective capacitor area, thereby reducing the area occupied by the second element D22 in the package structure 1400. In some embodiments, the area occupied by the second element D22 in the package structure 1400 can be reduced by about 10% to about 30% through the above design.

[0088] In some embodiments, the second redistribution structure may include a third dielectric layer 205, a wiring layer 212, a third wiring pattern 216, pads 218, and solder balls 220. The third dielectric layer 205 may cover the second element D22 and the second wiring pattern 210. The wiring layer 212 may be formed on the second wiring pattern 210 and electrically connected to the second element D22. The third wiring pattern 216 may include vias formed in the third dielectric layer 205 and wiring layers formed on the third dielectric layer 205. In some embodiments, the third wiring pattern 216 may be electrically connected to the second wiring pattern 210 through the wiring layer 212. Pads 218 may be formed on the third wiring pattern 216 and electrically connected to the third wiring pattern 216. Solder balls 220 may be formed on the pads 218 and electrically connected to the pads 218. In some embodiments, the second redistribution structure may include a third element (e.g., ...) disposed in the third dielectric layer 205. Figure 13b The third element D3 shown is electrically connected to the second element D2 via the second wiring pattern 210. In some embodiments, the third element D3 may include an antenna element, but the invention is not limited thereto.

[0089] In some embodiments, the capacitor structure may include a compensation structure 208 filled into the recesses of the first dielectric layer 201 to adjust the flatness of the film layer (e.g., the third dielectric layer 205) formed thereon. For example, the compensation structure 208 may make the flatness of the third dielectric layer 205 located on the compensation structure 208 greater than about 95%. In this way, the wiring pattern (e.g., the third wiring pattern 216) disposed on the portion below the third dielectric layer 205 where the compensation structure 208 is located can avoid electrical abnormalities caused by uneven wiring patterns.

[0090] Figure 6aThis is a cross-sectional schematic diagram of the packaging structure according to the sixth embodiment of the present invention. Figure 6b yes Figure 6a An enlarged schematic diagram of region A6 in the image. Figure 6a The packaging structure shown is 2000 and Figure 1a The package structure 2000 shown is similar to the one shown in the diagram. The main difference is that the package structure 2000 is used for a probe card (hereinafter referred to as probe card 2000), therefore the redistribution structure 300 and the integrated circuit structure 400 in the package structure 1000 are not shown. Figure 6a The probe card 2000 includes a substrate 500 and a conductive probe 600. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be described again here.

[0091] Please refer to Figure 6a and Figure 6b The probe card 2000 may include a connecting member 100a, a redistribution structure 200F, a substrate 500, and a conductive probe 600.

[0092] The connecting member 100a includes a connector 102 and an insulating layer 104 surrounding the connector 102. In some embodiments, the connector 102 may include an electrical connection structure 102a, a pad 102b, and a pad 102c. Pad 102b connects one end of the electrical connection structure 102a to the redistribution structure 200F. Pad 102c connects the other end of the electrical connection structure 102a to the substrate 500.

[0093] A redistribution structure 200F is disposed on a first side of the connecting member 100a. In some embodiments, the redistribution structure 200F may include a first redistribution structure. The first redistribution structure may include a first dielectric layer 201, a first wiring pattern 202, and a first element D1. The first dielectric layer 201 may be disposed on the connecting member 100a. The first wiring pattern 202 may be disposed in the first dielectric layer 201. The first element D1 may be disposed above the first dielectric layer 201 and electrically connected to a connector 102 of the connecting member 100a. The first element D1 may be electrically connected to the substrate 500 via the first wiring pattern 202 and the connecting member 100a. That is, the first element D1 may be integrated into the first redistribution structure of the redistribution structure 200F to reduce the communication path length between elements and reduce the area occupied by the first element D1, thereby helping to improve the performance of the probe card 2000 and reduce the size of the probe card 2000.

[0094] In some embodiments, the first redistribution structure may include a plurality of dummy patterns 204 disposed in the first dielectric layer 201. In some embodiments, the dummy patterns 204 may be electrically isolated from the connector 102 of the connecting member 100a. The dummy patterns 204 may adjust the flatness of the first dielectric layer 201. For example, when the first element D1 includes a capacitor structure, the dummy patterns 204 may be configured to adjust the flatness of the first dielectric layer 201 to a range of about 40% to about 60%, such that the first dielectric layer 201 includes protrusions on the dummy patterns 204 and recesses between two adjacent dummy patterns 204. In other words, the first dielectric layer 201 can have a trench structure (also referred to as a self-forming trench structure) without the need for an additional trench forming process. In this way, the capacitor (i.e., the first element D1) formed on the protrusions and recesses of the first dielectric layer 201 can have an improved effective capacitor area, thereby reducing the area occupied by the first element D1 in the package structure 2000. In some embodiments, the area occupied by the first element D1 in the probe card 2000 can be reduced by about 10% to about 30% through the above design.

[0095] In some embodiments, the first redistribution structure may include a wiring layer 206 disposed on the first dielectric layer 201 and electrically connected to the first wiring pattern 202. In some embodiments, the wiring layer 206 may be electrically connected to a capacitor structure. In some embodiments, the fabrication process for forming the capacitor structure may be integrated into the fabrication process for forming the wiring layer 206.

[0096] In some embodiments, the capacitor structure may include a compensation structure 208 filled into the recesses of the first dielectric layer 201 to adjust the flatness of the film layer (e.g., the second dielectric layer 203) formed thereon.

[0097] In some embodiments, the redistribution structure 200F may further include a second redistribution structure disposed on the first redistribution structure. The second redistribution structure may include a second dielectric layer 203, a plurality of second wiring patterns 210, and a second element D2. The second dielectric layer 203 may be disposed on the first dielectric layer 201 and cover the wiring layer 206 and the first element D1. The second wiring patterns 210 may include vias disposed in the second dielectric layer 203 and wiring layers disposed on the second dielectric layer 203. The second element D2 may be disposed on the portion of the second dielectric layer 203 below which a compensation structure 208 is provided and is electrically connected to the first element D1.

[0098] In some embodiments, when the second element D2 includes an inductor structure, the compensation structure 208 makes the flatness of the second dielectric layer 203 located on the compensation structure 208 greater than about 95%. In this way, the inductor structure disposed on the portion below the second dielectric layer 203 where the compensation structure 208 is located can avoid electrical abnormalities caused by unevenness in the wiring pattern. In some embodiments, the fabrication process for forming the inductor structure can be integrated into the fabrication process for forming the wiring layer in the second redistribution structure. For example, the second redistribution structure may include a wiring layer 212 and a wiring layer 214 formed on the second wiring pattern 210. The wiring layer 212 may be disposed around the wiring layer 214 and include a portion electrically connected to the second wiring pattern 210. The wiring layer 214 may be formed as follows: Figure 1d The pattern shown serves as an inductor structure. In some embodiments, the wiring layer 212 may include portions electrically connected to a capacitor structure (i.e., the first element D1) and portions electrically connected to an inductor structure (i.e., the second element D2). In some embodiments, the portions of the wiring layer 212 electrically connected to the capacitor structure are spaced at least 10 μm from the inductor structure (i.e., the second element D2) to reduce inductance losses. For example, when the first element D1 is a capacitor structure and the second element D2 is an inductor structure, the portions of the wiring layer 212 electrically connected to the first element D1 (e.g., the second element D2) are spaced at least 10 μm apart. Figure 1b The portion of the wiring layer 212 located to the right of the second element D2 is horizontally spaced at least 10 μm from the inductor structure (i.e., the second element D2) from a top view.

[0099] In some embodiments, the second redistribution structure may include a third dielectric layer 205, a third wiring pattern 216, and a pad 218. The third dielectric layer 205 may cover the second element D2 and the second wiring pattern 210. The third wiring pattern 216 may include vias formed in the third dielectric layer 205 and wiring layers formed on the third dielectric layer 205. In some embodiments, the third wiring pattern 216 may be electrically connected to the second wiring pattern 210 through the wiring layer 212. The pad 218 may be formed on and electrically connected to the third wiring pattern 216.

[0100] A conductive probe 600 may be disposed above the redistribution structure 200F and electrically connected to the first element D1. For example, the conductive probe 600 may be bonded to a pad 218 and electrically connected to the first element D1 via the pad 218, the third wiring pattern 216, the wiring layer 212, and the second wiring pattern 210. In some embodiments, the second redistribution structure may include a fourth dielectric layer 207 disposed on the third dielectric layer 205. The fourth dielectric layer 207 may include an opening 207a exposing the pad 218, and the conductive probe 600 is disposed in the opening 207a and in contact with the pad 218 exposed by the opening 207a, thereby limiting the measurement range of the conductive probe 600.

[0101] The substrate 500 may be disposed on a second side of the connecting member 100a opposite to the first side. The circuit pattern 502 in the substrate 500 is electrically connected to a first element D1 of the first redistribution structure in the redistribution structure 200F via the connecting member 100a. In some embodiments, the substrate 500 may include a multilayer organic substrate (MLO substrate).

[0102] Figure 7a This is a cross-sectional schematic diagram of the packaging structure according to the seventh embodiment of the present invention. Figure 7b yes Figure 7a An enlarged schematic diagram of region A7 in the image. Figure 7a The package structure 2100 shown is... Figure 6a The packaging structure shown is similar to that of probe card 2000, both of which are applied to probe cards (hereinafter referred to as probe card 2000 and probe card 2100). The main difference between probe card 2100 and probe card 2000 is that probe card 2100 includes first elements D1a, D1b, and D1c applied to different areas. Other identical or similar components / films / patterns are represented by the same or similar element symbols, which will not be repeated here.

[0103] Please refer to Figure 7a and Figure 7b The redistribution structure 200G in the probe card 2100 can be disposed on the connecting member 100a and may include a first dielectric layer 201, a second dielectric layer 203, a first wiring pattern 202, first elements D1a, D1b, D1c, a second wiring pattern 213, a third wiring pattern 216, and a pad 218. The second dielectric layer 203, the first wiring pattern 202, the third wiring pattern 216, and the pad 218 have been described in detail in the foregoing embodiments and will not be repeated here.

[0104] The first dielectric layer 201 may be a planarization layer (hereinafter referred to as planarization layer 201), so the formation of the dummy pattern 204 in the planarization layer 201 may be omitted. In this embodiment, the material of the planarization layer 201 may be different from the material of the second dielectric layer 203. In some embodiments, the flatness of the planarization layer 201 is greater than about 95%, so that the first elements D1a, D1b and D1c disposed on the planarization layer 201 can avoid electrical abnormalities caused by unevenness in the circuit pattern.

[0105] The first elements D1a, D1b, and D1c may be disposed above the planarization layer 201. The second wiring pattern 213 may include vias disposed in the planarization layer 201 and wiring layers disposed on the planarization layer 201, as well as vias and wiring layers disposed in the second dielectric layer 203. In some embodiments, the fabrication process for forming the first elements D1a, D1b, and D1c may be integrated into the fabrication process for forming the second wiring pattern 213. For example, the first elements D1a, D1b, or D1c may be, for instance, high-frequency elements formed by wiring in the second wiring pattern 213. In some embodiments, the first elements D1a, D1b, and D1c may be configured in different circuit regions in the redistribution structure 200G. For example, the first element D1a may be configured in the fan-out circuit region; the first element D1b may be configured in the matching circuit region; and the first element D1c may be configured in the millimeter-wave circuit region.

[0106] Figure 8a This is a cross-sectional schematic diagram of the packaging structure according to the eighth embodiment of the present invention. Figure 8b yes Figure 8a An enlarged view of region A8 in the diagram. Figure 8a The package structure 2200 shown is... Figure 7a The packaging structure 2100 shown is similar, and both are applied to probe cards (hereinafter referred to as probe card 2100 and probe card 2200). The main difference between probe card 2200 and probe card 2100 is that the redistribution structure 200H of probe card 2200 includes a third dielectric layer 205 disposed on the second dielectric layer 203. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0107] Please refer to Figure 8a and Figure 8b The redistribution structure 200H of the probe card 2200 may include a third dielectric layer 205 disposed on the second dielectric layer 203. The third dielectric layer 205 may include an opening 205a exposing a pad 218, and a conductive probe 600 is disposed in the opening 205a and in contact with the pad 218 exposed by the opening 205a, thereby limiting the measurement range of the conductive probe 600.

[0108] Figure 9aThis is a cross-sectional schematic diagram of the packaging structure according to the ninth embodiment of the present invention. Figure 9b yes Figure 9a An enlarged schematic diagram of region A9 in the image. Figure 9a The package structure 2300 shown is... Figure 6a The packaging structure shown is similar to 2000, and both are applied to probe cards (hereinafter referred to as probe card 2000 and probe card 2300). The main difference between probe card 2300 and probe card 2000 is that the position of the first element D11 in the redistribution structure 200I of probe card 2300 is different from the position of the first element D1 in the redistribution structure 200F of probe card 2000. Other identical or similar components / films / patterns are represented by the same or similar element symbols, and will not be repeated here.

[0109] Please refer to Figure 9a and Figure 9b A redistribution structure 200I is disposed on the connecting member 100a. In some embodiments, the redistribution structure 200I may include a first redistribution structure. The first redistribution structure may include a first dielectric layer 201, a first wiring pattern 202, and a first element D11. The first dielectric layer 201 may be disposed on the connecting member 100a. The first wiring pattern 202 may be disposed in the first dielectric layer 201. The first element D11 may be disposed above the first dielectric layer 201 and electrically connected to a connector 102 of the connecting member 100a. The first element D11 may be electrically connected to the wiring pattern 502 in the substrate 500 via the first wiring pattern 202 and the connecting member 100a. That is, the first element D11 may be integrated into the first redistribution structure of the redistribution structure 200I to reduce the communication path length between elements and reduce the area occupied by the first element D11, thereby helping to improve the performance of the probe card 2300 and reduce the size of the probe card 2300.

[0110] In some embodiments, the first redistribution structure may include a plurality of dummy patterns 204, a wiring layer 206, a second dielectric layer 203, and a second wiring pattern 210. The dummy patterns 204 may be disposed in the first dielectric layer 201 and electrically isolated from the connector 102 of the connecting member 100a. The wiring layer 206 may be disposed on the first dielectric layer 201 and electrically connected to the first wiring pattern 202. The second dielectric layer 203 may be formed on the first dielectric layer 201 and cover the wiring layer 206. The second wiring pattern 210 may be formed on the second dielectric layer 203.

[0111] In some embodiments, when the first element D11 is disposed on the second dielectric layer 203 (e.g.) Figure 9bAs shown, the dummy pattern 204 can be used to adjust the flatness of the first dielectric layer 201 and the second dielectric layer 203. For example, when the first element D11 includes a capacitor structure, the dummy pattern 204 can be configured to adjust the flatness of the first dielectric layer 201 to a range of about 40% to about 60%, such that the first dielectric layer 201 includes a protrusion on the dummy pattern 204 and a recess between two adjacent dummy patterns 204, and the second dielectric layer 203 formed on the first dielectric layer 201 may also include a protrusion above the dummy pattern 204 (corresponding to the position of the protrusion of the first dielectric layer 201) and a recess between two adjacent dummy patterns 204 (corresponding to the position of the recess of the first dielectric layer 201). In other words, the first dielectric layer 201 and the second dielectric layer 203 can have a trench structure (also referred to as a self-forming trench structure) without the need for an additional trench forming process. In this way, the capacitor (i.e., the first element D11) formed on the protrusions and recesses of the second dielectric layer 203 can have an improved effective capacitance area, thereby reducing the area occupied by the first element D11 in the probe card 2300. In some embodiments, the area occupied by the first element D11 in the probe card 2300 can be reduced by about 10% to about 30% through the above design. In some embodiments, the fabrication process for forming the inductor structure can be integrated into the fabrication process for forming the second wiring pattern 210. In some embodiments, the capacitor structure may include a compensation structure 208 filled into the recesses of the second dielectric layer 203 to adjust the flatness of the film layer (e.g., the third dielectric layer 205) formed thereon.

[0112] In some embodiments, the redistribution structure 200I may further include a second redistribution structure disposed on the first redistribution structure. The second redistribution structure may include a third dielectric layer 205, a wiring layer 212, a third wiring pattern 216, and a pad 218. The third dielectric layer 205 may cover the first element D11 and the second wiring pattern 210. The wiring layer 212 may be formed on the second wiring pattern 210 and electrically connected to the first element D11. The third wiring pattern 216 may include vias formed in the third dielectric layer 205 and wiring layers formed on the third dielectric layer 205. In some embodiments, the third wiring pattern 216 may be electrically connected to the second wiring pattern 210 through the wiring layer 212. The pad 218 may be formed on the third wiring pattern 216 and electrically connected to the third wiring pattern 216.

[0113] In some embodiments, when the capacitor structure includes a compensation structure 208, the compensation structure 208 can make the flatness of the third dielectric layer 205 located on the compensation structure 208 greater than about 95%. In this way, the wiring pattern (e.g., the third wiring pattern 216) provided on the portion below the second dielectric layer 205 where the compensation structure 208 is located can avoid electrical abnormalities caused by uneven wiring patterns.

[0114] Figure 10a This is a cross-sectional schematic diagram of the packaging structure according to the tenth embodiment of the present invention. Figure 10b yes Figure 10a An enlarged schematic diagram of region A10 in the image. Figure 10a The package structure shown is 2400 and Figure 9a The packaging structure shown is similar to 2300, and both are used in probe cards (hereinafter referred to as probe card 2300 and probe card 2400). The main difference between probe card 2400 and probe card 2300 is that the redistribution structure 200J of probe card 2400 also includes a second element D22 and a fourth dielectric layer 207. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0115] Please refer to Figure 10a and Figure 10b The first redistribution structure in the redistribution structure 200J may include a second element D22 disposed on the first dielectric layer 201. In some embodiments, when the second element D22 includes an inductor structure, the dummy pattern 204 may be configured to adjust the flatness of the first dielectric layer 201 to greater than about 95%, so that the inductor structure (i.e., the second element D22) disposed on the first dielectric layer 201 can avoid electrical abnormalities caused by unevenness in the circuit pattern. In some embodiments, the fabrication process for forming the inductor structure may be integrated into the fabrication process for forming the wiring layer 206. For example, the wiring layer 206 may include wiring 206a and wiring 206b formed on the first dielectric layer 201. Wiring 206a may be disposed around wiring 206b and include a portion electrically connected to the first wiring pattern 202. Wiring 206b may be formed as described above. Figure 1d The pattern shown is used as an inductor structure.

[0116] In some embodiments, the pattern of the wiring 206b used to form the second element D22 can adjust the flatness of the second dielectric layer 203. For example, when the first element D11 includes a capacitor structure, the wiring 206b can be configured to adjust the flatness of the second dielectric layer 203 to a range of about 40% to about 60%, such that the second dielectric layer 203 includes protrusions on the wiring 206b and recesses between adjacent patterns in the wiring 206b. In this way, the capacitor structure (i.e., the first element D11) formed on the protrusions and recesses of the second dielectric layer 203 can have an improved effective capacitor area, thereby reducing the area occupied by the first element D11 in the probe card 2400.

[0117] The second redistribution structure in the redistribution structure 200J may include a fourth dielectric layer 207 disposed on the third dielectric layer 205. The fourth dielectric layer 207 may include an opening 207a exposing a pad 218, and a conductive probe 600 is disposed in the opening 207a and in contact with the pad 218 exposed by the opening 207a, thereby limiting the measurement range of the conductive probe 600.

[0118] Figure 11a This is a cross-sectional schematic diagram of the packaging structure according to the eleventh embodiment of the present invention. Figure 11b yes Figure 11a An enlarged schematic diagram of region A11 in the image. Figure 11a The package structure shown is 2500 and Figure 9a The package structure shown is similar to 2300, and both are used in probe cards (hereinafter referred to as probe card 2300 and probe card 2500). The main difference between probe card 2500 and probe card 2300 is that the redistribution structure 200K of probe card 2500 also includes a fourth dielectric layer 207. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0119] Please refer to Figure 11a and Figure 11b The second redistribution structure in the redistribution structure 200K of the probe card 2500 may include a fourth dielectric layer 207 disposed on the third dielectric layer 205. The fourth dielectric layer 207 may include an opening 207a exposing a pad 218, and a conductive probe 600 is disposed in the opening 207a and in contact with the pad 218 exposed by the opening 207a, thereby limiting the measurement range of the conductive probe 600.

[0120] Figure 12a This is a cross-sectional schematic diagram of the packaging structure according to the twelfth embodiment of the present invention. Figure 12b yes Figure 12a An enlarged schematic diagram of region A12 in the image. Figure 12a The package structure shown is 3000 and Figure 2a The encapsulation structure 3000 shown is similar to that of the encapsulation structure 1100. The main difference is that the encapsulation structure 3000 is applied to an antenna module (hereinafter referred to as antenna module 3000). Therefore, the antenna element D11 in the redistribution structure 200L of the antenna module 3000 is different from the first element D1 of the encapsulation structure 1100 in terms of pattern and / or function. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0121] Please refer to Figure 12a and Figure 12bThe redistribution structure 200L in the antenna module 3000 may be disposed on a first side of the connecting member 100a and may include a first redistribution structure. The first redistribution structure may include a first dielectric layer 201, a first wiring pattern 202, and an antenna element D11. The first wiring pattern 202 may be disposed on the first side of the connecting member 100a and electrically connected to the connector 102 of the connecting member 100a. The first dielectric layer 201 may be disposed on the first side of the connecting member 100a and cover the first wiring pattern 202. The antenna element D11 may be disposed above the first dielectric layer 201 and configured to transmit and / or receive signals, wherein the antenna element D11 is electrically connected to the first wiring pattern 202. The antenna element D11 may be electrically connected to the integrated circuit 402 through the first wiring pattern 202, the connecting member 100a, and the redistribution structure 300. In other words, antenna element D11 can be integrated into the first redistribution structure of redistribution structure 200L to reduce the communication path length between elements and reduce the area occupied by antenna element D11, thereby helping to improve the performance of antenna module 3000 and reduce the size of antenna module 3000. Antenna element D11 may include an active antenna, a passive antenna, or a combination thereof. In some embodiments, the dielectric layer in antenna module 3000 may be made of a transparent material, such as the material used in spin-on glass (SOG) process, to create a transparent antenna structure.

[0122] In some embodiments, the first redistribution structure may include a plurality of dummy patterns 204 disposed in the first dielectric layer 201 and a wiring layer 206 disposed on the first dielectric layer 201 and electrically connected to the first wiring pattern 202. In some embodiments, the dummy patterns 204 may be electrically isolated from the connector 102 of the connecting member 100a. The dummy patterns 204 may adjust the flatness of the first dielectric layer 201. For example, the dummy patterns 204 may be configured to adjust the flatness of the first dielectric layer 201 to greater than about 95% so that the antenna element D11 disposed on the first dielectric layer 201 can avoid electrical abnormalities caused by unevenness in the wiring pattern. In some embodiments, the fabrication process for forming the antenna element D11 may be integrated into the fabrication process for forming the wiring layer 206. For example, the wiring layer 206 may include wiring 206a and wiring 206b formed on the first dielectric layer 201. Wiring 206a may be disposed around wiring 206b and include a portion electrically connected to the first wiring pattern 202. The pattern of wiring 206b can form antenna element D11.

[0123] In some embodiments, the redistribution structure 200L may further include a second redistribution structure disposed on the first redistribution structure. The second redistribution structure may include a second dielectric layer 203 and a plurality of second wiring patterns 210. The second dielectric layer 203 may be disposed on the first dielectric layer 201 and cover the wiring layer 206. The second wiring patterns 210 may be disposed in the second dielectric layer 203 and electrically connect the antenna element D11 to the wiring layer 206.

[0124] Figure 13a This is a cross-sectional schematic diagram of the packaging structure according to the thirteenth embodiment of the present invention. Figure 13b yes Figure 13a An enlarged schematic diagram of region A13 in the image. Figure 13a The package structure 3100 shown is... Figure 5a The packaging structure 3100 shown is similar to that of the antenna module (hereinafter referred to as antenna module 3100). The main difference is that the packaging structure 3100 is applied to the antenna module (hereinafter referred to as antenna module 3100). Therefore, the redistribution structure 200M of antenna module 3100 also includes antenna element D3. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0125] Please refer to Figure 13a and Figure 13b Compared to Figure 5a The illustrated packaging structure 1400 and the redistribution structure 200M in the antenna module 3100 further include an antenna element D3 disposed in the third dielectric layer 205. The antenna element D3 is disposed above the second element D22 and is electrically connected to the second element D22 via a third wiring pattern 216, a wiring layer 212, and a second wiring pattern 210. In some embodiments, the dielectric layer in the antenna module 3100 may be made of a transparent material, such as the material used in spin-on glass (SOG) processes, to create a transparent antenna structure.

[0126] Figure 14a This is a cross-sectional schematic diagram of the packaging structure according to the fourteenth embodiment of the present invention. Figure 14b yes Figure 14a An enlarged schematic diagram of region A14 in the image. Figure 14a The package structure 3200 shown is... Figure 12a The packaging structures shown are similar to 3000, both being used in antenna modules (hereinafter referred to as antenna module 3000 and antenna module 3200). The main difference between antenna module 3200 and antenna module 3000 is that the connecting member 100b of antenna module 3200 also includes component 110, and the redistribution structure 200N of antenna module 3200 differs from the redistribution structure 200L of antenna module 3000. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0127] Please refer to Figure 14a and Figure 14b The antenna module 3200's connecting member 100b includes a connector 102, an insulating layer 104 surrounding the connector 102, a component 110 disposed in the insulating layer 104, and a connector 106 electrically connecting the component 110 to the redistribution structure 200N. In some embodiments, the component 110 includes a first component 110a and a second component 110b. The first wiring pattern 202 of the redistribution structure 200N may include a wiring layer 202a electrically connected to the wiring layer 206 and a wiring layer 202b electrically connected to the first component 110a and the second component 110b. In some embodiments, the wiring layer 202b may adjust the flatness of the first dielectric layer 201. For example, the wiring layer 202b may be configured to adjust the flatness of the first dielectric layer 201 to greater than about 95% so that the antenna element D11 disposed on the first dielectric layer 201 can avoid electrical abnormalities caused by uneven wiring patterns. The first component 110a and the second component 110b may be electrically connected to the antenna element D11 and / or the integrated circuit 402.

[0128] Figure 15 This is a cross-sectional schematic diagram of the packaging structure according to the fifteenth embodiment of the present invention. Figure 15 The package structure 3300 shown is... Figure 14a The illustrated packaging structure 3200 is similar, and both are applied to antenna modules (hereinafter referred to as antenna module 3200 and antenna module 3300). The main difference between antenna module 3300 and antenna module 3200 is that the redistribution structure 301 of antenna module 3300 is different from the redistribution structure 300 of antenna module 3200, and the size of component 111 of connecting member 100c is different from the size of component 110 of connecting member 100b. Other identical or similar components / films / patterns are represented by the same or similar element symbols and will not be repeated here.

[0129] Please refer to Figure 15 The redistribution structure 301 of the antenna module 3300 may include a redistribution layer 302 and an insulating layer 305. The redistribution layer 302 may be formed in the insulating layer 305, and the insulating layer 305 may include a groove 305a for accommodating the component 111 of the connecting member 100c, thereby allowing a larger component 111 to be embedded in the connecting member 100c while maintaining the thickness of the antenna module 3300.

[0130] In summary, the packaging structure, antenna module, and probe card in the above embodiments of the present invention can reduce the communication path length between components and reduce the area occupied by active / passive components by integrating components such as active or passive components into a redistributed structure design, thereby helping to improve component performance and reduce component size.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that, include: A connecting member, including a connector and an insulating layer surrounding the connector; as well as A first redistribution structure is disposed on the connecting member and includes: A first dielectric layer is disposed on the connecting member; A first wiring pattern is disposed in the first dielectric layer; and A first element is disposed above the first dielectric layer and electrically connected to the connector. The first redistribution structure includes multiple dummy patterns, and the dummy patterns are disposed in the first dielectric layer and electrically isolated from the connector. The dummy pattern wherein the flatness of the first dielectric layer is in the range of 40% to 60% includes protrusions on the dummy pattern and recesses between two adjacent dummy patterns, and the first element is disposed on the protrusions and recesses of the first dielectric layer. The first element includes a capacitor structure, the capacitor structure comprising: The first electrode is disposed on the surface of the recess and the protrusion of the first dielectric layer; A dielectric material is disposed on the first electrode; A second electrode is disposed on the dielectric; and A compensation structure is disposed on the second electrode and fills the recess in the first dielectric layer.

2. The packaging structure according to claim 1, characterized in that, It also includes a second redistribution structure disposed on the first redistribution structure, and the second redistribution structure includes: A second dielectric layer is disposed on the capacitor structure, wherein the compensation structure makes the flatness of the second dielectric layer located on the compensation structure greater than 95%; Multiple second wiring patterns are disposed on the second dielectric layer; and The second element is disposed on the portion of the second dielectric layer below which the compensation structure is provided and is electrically connected to the first element.

3. The packaging structure according to claim 2, characterized in that, From a top-down view, the second wiring pattern that is electrically connected to the capacitor structure in the plurality of second wiring patterns is spaced at least 10 μm apart from the second element.

4. A packaging structure, characterized in that, include: A connecting member, including a connector and an insulating layer surrounding the connector; as well as A first redistribution structure is disposed on the connecting member and includes: A first dielectric layer is disposed on the connecting member; A first wiring pattern is disposed in the first dielectric layer; and A first element is disposed above the first dielectric layer and electrically connected to the connector. The first redistribution structure includes multiple dummy patterns, which are disposed in the first dielectric layer and electrically isolated from the connector. The dummy patterns ensure that the flatness of the first dielectric layer is greater than 95%. The encapsulation structure further includes a second redistribution structure disposed on the first redistribution structure, and the second redistribution structure includes: A second dielectric layer is disposed on the first element; The second element is disposed on the second dielectric layer and electrically connected to the first wiring pattern; A third dielectric layer is disposed on the second element; and A second wiring pattern is disposed in the third dielectric layer and electrically connected to the second component, and The first element includes a circuit pattern that causes the flatness of the second dielectric layer to be between 40% and 60%, including protrusions on the circuit pattern and recesses between two adjacent circuit patterns, and the second element is disposed on the recesses and protrusions of the second dielectric layer. The second element includes a capacitor structure, the capacitor structure comprising: The first electrode is disposed on the surface of the recess and the protrusion of the second dielectric layer; A dielectric material is disposed on the first electrode; A second electrode is disposed on the dielectric; and A compensation structure is disposed on the second electrode and fills the recess of the second dielectric layer.

5. The packaging structure according to claim 4, characterized in that, The second redistribution structure includes a third element disposed in the third dielectric layer, and the third element is electrically connected to the second element through the second wiring pattern.

6. An antenna module, characterized in that, include: A connecting member, including a connector and an insulating layer surrounding the connector; A redistribution structure is disposed on the first side of the connecting member and includes: A first wiring pattern is disposed on the connecting member and electrically connected to the connecting member; A first dielectric layer is disposed on the connecting member and covers the first wiring pattern; and An antenna element, disposed above the first dielectric layer and configured to transmit and / or receive signals, wherein the antenna element is electrically connected to the first wiring pattern; and A chip is disposed above the second side of the connecting member relative to the first side, wherein the chip is electrically connected to the antenna element. The redistribution structure includes multiple dummy patterns, which are disposed in the first dielectric layer and electrically isolated from the connector. The dummy patterns ensure that the flatness of the first dielectric layer is greater than 95%. The redistribution structure includes a first element disposed on the first dielectric layer and a second dielectric layer disposed on the first dielectric layer and covering the first element, wherein the antenna element is disposed above the second dielectric layer. The first element includes a circuit pattern that causes the flatness of the second dielectric layer to be between 40% and 60% to include protrusions on the circuit pattern and recesses between two adjacent circuit patterns. The redistribution structure includes a second element disposed on the protrusion and the recess of the second dielectric layer, and the second element is disposed between the antenna element and the first element and electrically connected to the antenna element and the first element. The second element includes a capacitor structure, the capacitor structure comprising: The first electrode is disposed on the surface of the recess and the protrusion of the second dielectric layer; A dielectric material is disposed on the first electrode; A second electrode is disposed on the dielectric; and A compensation structure is disposed on the second electrode and fills the recess of the second dielectric layer.

7. A probe card, characterized in that, include: A connecting member, including a connector and an insulating layer surrounding the connector; A first redistribution structure is disposed on a first side of the connecting member and includes: A first dielectric layer is disposed on the connecting member; A first wiring pattern is disposed in the first dielectric layer; and A first element is disposed above the first dielectric layer and electrically connected to the connector; A conductive probe is disposed above the first redistribution structure and electrically connected to the first element; and A substrate is disposed on a second side of the connecting member opposite to the first side, and the circuit pattern in the substrate is electrically connected to the first element in the first redistribution structure through the connecting member. The first redistribution structure includes a plurality of dummy patterns disposed in the first dielectric layer and electrically isolated from the connector. The dummy patterns cause the flatness of the first dielectric layer to be in the range of 40% to 60%, including protrusions on the dummy patterns and recesses between two adjacent dummy patterns. The first element is disposed on the protrusions and recesses of the first dielectric layer. The first element includes a capacitor structure, the capacitor structure comprising: The first electrode is disposed on the surface of the recess and the protrusion of the first dielectric layer; A dielectric material is disposed on the first electrode; A second electrode is disposed on the dielectric; and A compensation structure is disposed on the second electrode and fills the recess in the first dielectric layer.

8. The probe card according to claim 7, characterized in that, It also includes a second redistribution structure disposed on the first redistribution structure, and the second redistribution structure includes: A second dielectric layer is disposed on the first element; Multiple second wiring patterns are disposed in the second dielectric layer; A second element, disposed in the second dielectric layer and electrically connected to the first element; and A connecting pad is disposed on the second dielectric layer and electrically connected to the conductive probe.

9. A probe card, characterized in that, include: A connecting member, including a connector and an insulating layer surrounding the connector; A first redistribution structure is disposed on the connecting member and includes: A first dielectric layer is disposed on the connecting member; The first wiring pattern is disposed in the first dielectric layer; A first element, disposed above the first dielectric layer and electrically connected to the connector; and Multiple dummy patterns are disposed in the first dielectric layer and electrically isolated from the connector, wherein the dummy patterns make the flatness of the first dielectric layer greater than 95%; The second redistribution structure is disposed on the first redistribution structure and includes: A second dielectric layer is disposed on the first element; The second element is disposed on the second dielectric layer and electrically connected to the first wiring pattern; A third dielectric layer is disposed on the second element; and A second wiring pattern is disposed in the third dielectric layer and electrically connected to the second component. The first element includes a circuit pattern, the circuit pattern causing the flatness of the second dielectric layer to be in the range of 40% to 60% to include protrusions on the circuit pattern and recesses between two adjacent circuit patterns, and the second element is disposed on the recesses and protrusions of the second dielectric layer; and A conductive probe is disposed above the second redistribution structure and electrically connected to the second element; The second element includes a capacitor structure, the capacitor structure comprising: The first electrode is disposed on the surface of the recess and the protrusion of the second dielectric layer; A dielectric material is disposed on the first electrode; A second electrode is disposed on the dielectric; and A compensation structure is disposed on the second electrode and fills the recess of the second dielectric layer.

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