An overcurrent protection circuit for a power transistor
By implementing an overcurrent protection circuit for power transistors using logic devices, the problems of comparator decision delay and high power consumption are solved, achieving fast response and low power consumption overcurrent protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMIMENT TECH (SHANGHAI) CO LTD
- Filing Date
- 2022-12-06
- Publication Date
- 2026-07-31
AI Technical Summary
In existing power transistor overcurrent protection circuits, the comparator decision delay is too large, which causes the power transistor to fail to turn off in time under overcurrent conditions, resulting in damage. At the same time, the complex circuit structure and large quiescent current lead to high power consumption.
Logic devices are used to replace comparators, and overcurrent protection is achieved by processing voltage signals through logic. Clamping protection circuits and multiple logic devices are used to quickly determine whether the current is overcurrent and generate an overcurrent decision signal to control the on/off state of the power transistor.
It achieves a fast response for power transistor overcurrent protection, avoids damage caused by current exceeding the safe operating range for a long time, and reduces the static power consumption of the circuit.
Smart Images
Figure CN115733123B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuits, and more specifically to an overcurrent protection circuit for a power transistor. Background Technology
[0002] In the current field of electronic circuits, metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) are commonly used as power transistors to drive loads. Taking MOSFETs as an example, if a MOSFET operates outside its safe operating region, it will burn out, causing the load to malfunction. Therefore, the proper functioning of the power transistor is crucial for the normal driving of the load. The safe operating region of a power transistor is called the SOA (Safe Operating Area). The SOA curve defines the current, voltage, and time at which the power transistor can operate safely for an extended period. If the power transistor operates above the SOA, overheating and burnout may occur. Therefore, overcurrent protection is generally implemented for power transistors to prevent overheating and burnout due to overcurrent.
[0003] Overcurrent protection for power transistors (PTZs) involves controlling the transistor to disconnect after detecting overcurrent to prevent it from exceeding its SOA (Self-Operating Aspect Ratio) operating range. Traditional overcurrent protection schemes convert the current signal flowing through the power transistor into a voltage signal via a resistor, then compare this voltage signal with a reference voltage to output an overcurrent protection signal. The conventional approach to comparing the voltage signal with a reference voltage is based on a comparator for decision-making. However, comparator circuitry is relatively complex and costly. Furthermore, due to power consumption limitations and parasitic capacitance, comparators have significant decision delays, which can prevent the power transistor from shutting off promptly under overcurrent conditions, leading to damage. To minimize the comparator's decision delay, comparators are often designed to be complex or require very large quiescent currents, which in turn increase the power transistor's quiescent power consumption. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide an overcurrent protection circuit for a power transistor, which can quickly turn off the power transistor when an overcurrent occurs. The circuit is simple and has a low cost.
[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: an overcurrent protection circuit for a power transistor, comprising a control circuit, a power drive circuit, and an overcurrent decision circuit;
[0006] The power drive circuit for driving the load includes a plurality of power transistors to be protected against overcurrent, and is used to convert the current signal flowing through the plurality of power transistors to be protected against overcurrent into a voltage signal.
[0007] The overcurrent decision circuit is electrically connected to the power drive circuit and includes multiple logic devices. The multiple logic devices perform logic processing on the voltage signal to determine whether the current signal corresponding to the voltage signal is overcurrent and generate an overcurrent decision signal.
[0008] The control circuit is electrically connected to the overcurrent decision circuit and the power drive circuit respectively. The control circuit generates a power transistor on / off signal through the overcurrent decision signal to control the on / off of the plurality of power transistors to be protected against overcurrent in the power drive circuit.
[0009] Based on the above technical solution, the present invention can be further improved as follows.
[0010] Furthermore, the power transistor is specifically a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.
[0011] Furthermore, it also includes a clamping protection circuit; the overcurrent decision circuit is electrically connected to the power drive circuit through the clamping protection circuit;
[0012] The clamping protection circuit is used to clamp the voltage signal and generate a clamping voltage signal.
[0013] The multiple logic devices in the overcurrent decision circuit specifically determine whether the current signal corresponding to the clamping voltage signal is overcurrent after performing logical processing on the clamping voltage signal, and generate an overcurrent decision signal.
[0014] Furthermore, the plurality of power transistors to be protected against overcurrent include a first P-type power transistor, a second P-type power transistor, a first N-type power transistor, and a second N-type power transistor; the gates of the first P-type power transistor, the second P-type power transistor, the first N-type power transistor, and the second N-type power transistor are all used to connect to the power transistor on / off signal output by the control circuit; the sources of the first P-type power transistor and the second P-type power transistor are both used to connect to a first voltage level, and the sources of the first N-type power transistor and the second N-type power transistor are both grounded; the drain of the first P-type power transistor is connected to the first N-type power transistor. The drains of the first P-type power transistor and the second N-type power transistor are connected; the nodes between the drains of the first P-type power transistor and the first N-type power transistor, and the nodes between the drains of the second P-type power transistor and the second N-type power transistor, are both outputs of the power drive circuit and are used to connect to the two ends of the load respectively; the nodes between the drains of the first P-type power transistor and the first N-type power transistor, and the nodes between the drains of the second P-type power transistor and the second N-type power transistor, are also used to output the voltage signal to the clamping protection circuit.
[0015] Furthermore, the clamping protection circuit includes a first P-type clamping protection transistor, a second P-type clamping protection transistor, a first N-type clamping protection transistor, and a second N-type clamping protection transistor; the gates of the first P-type clamping protection transistor and the second P-type clamping protection transistor are both connected to a second voltage level; the gate of the first N-type clamping protection transistor is connected to the gate of the first N-type power transistor; the gate of the second N-type clamping protection transistor is connected to the gate of the second N-type power transistor; and the source and drain of the first P-type clamping protection transistor are both connected to the second P-type clamping protection transistor. At the node between the drain of a P-type power transistor and the drain of the first N-type power transistor, the source of the second P-type clamping protection transistor and the drain of the second N-type clamping protection transistor are both connected to the node between the drain of the second P-type power transistor and the drain of the second N-type power transistor; the drain of the first P-type clamping protection transistor, the drain of the second P-type clamping protection transistor, the source of the first N-type clamping protection transistor and the source of the second N-type clamping protection transistor are all outputs of the clamping protection circuit, and are used to output the clamping processing voltage signal to the overcurrent decision circuit.
[0016] Furthermore, the plurality of logic devices include a first inverter, a second inverter, a first buffer, and a second buffer; the input terminal of the first inverter is connected to the drain of the first P-type clamping protection transistor, the input terminal of the second inverter is connected to the drain of the second P-type clamping protection transistor, the input terminal of the first buffer is connected to the source of the first N-type clamping protection transistor, and the input terminal of the second buffer is connected to the source of the second N-type clamping protection transistor; the output terminals of the first inverter, the second inverter, the first buffer, and the second buffer are all outputs of the overcurrent decision circuit, and are used to output the overcurrent decision signal to the control circuit.
[0017] Furthermore, the control circuit includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first NOR gate, a second NOR gate, a third NOR gate, and a fourth NOR gate; the input terminal of the first NOR gate is connected to the output terminal of the first inverter, the output terminal of the first NOR gate is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the gate of the first P-type power transistor; the input terminal of the third NOR gate is connected to the output terminal of the second inverter, the output terminal of the third NOR gate is connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the gate of the second P-type power transistor; the input terminal of the second NOR gate... The output of the second NOR gate is connected to the output of the first buffer, the output of the second NOR gate is connected to the input of the fourth inverter, and the output of the fourth inverter is connected to the gate of the first N-type power transistor; the input of the fourth NOR gate is connected to the output of the second buffer, the output of the fourth NOR gate is connected to the input of the sixth inverter, and the output of the sixth inverter is connected to the gate of the second N-type power transistor; the outputs of the third inverter, the fourth inverter, the fifth inverter, and the sixth inverter are all outputs of the control circuit and are used to output the power transistor on / off signal to the power drive circuit.
[0018] Furthermore, the input terminal of the first NOR gate is also used to input a first external signal, specifically a switching control signal of the first P-type power transistor; the input terminal of the second NOR gate is also used to input a second external signal, specifically a switching control signal of the first N-type power transistor; the input terminal of the third NOR gate is also used to input a third external signal, specifically a switching control signal of the second P-type power transistor; and the input terminal of the fourth NOR gate is also used to input a fourth external signal, specifically a switching control signal of the second N-type power transistor.
[0019] Furthermore, the power supply terminals of the first inverter, the second inverter, the third inverter, and the fifth inverter are all connected to the first voltage level, and the ground terminals of the first inverter, the second inverter, the third inverter, and the fifth inverter are all connected to the second voltage level; the power supply terminals of the first buffer, the second buffer, the fourth inverter, and the sixth inverter are all connected to the third voltage level, and the ground terminals of the first buffer, the second buffer, the fourth inverter, and the sixth inverter are all grounded.
[0020] Furthermore, the first voltage level is a high-voltage power supply level, the second voltage level is a high-voltage power supply level and is 5V lower than the first voltage level, and the third voltage level is a 5V voltage level.
[0021] The beneficial effects of this invention are as follows: The overcurrent protection circuit for a power transistor provided by this invention is a circuit that achieves overcurrent protection without using a comparator, but instead uses logic devices. The response speed of a comparator is on the order of hundreds of nanoseconds, while the response speed of logic devices is generally on the order of nanoseconds. Therefore, the response speed of overcurrent protection achieved through logic circuits is much faster than that of comparators in related technologies, solving the problem of power transistor damage caused by the current flowing through the power transistor being greater than the SOA current for a long time. In addition, the overcurrent protection circuit implemented by logic devices in this invention has a simple structure, does not consume static current, ensures the low power consumption design of the circuit, and solves the problem of large static current required by complex comparator circuits, which leads to large static power consumption of the circuit. Attached Figure Description
[0022] Figure 1 This is a structural block diagram of an overcurrent protection circuit for a power transistor according to the present invention;
[0023] Figure 2 This is another structural block diagram of an overcurrent protection circuit for a power transistor according to the present invention;
[0024] Figure 3 This is a circuit diagram of an overcurrent protection circuit for a power transistor according to the present invention.
[0025] Figure 4 This is the signal timing diagram when the power drive circuit does not trigger overcurrent protection.
[0026] Figure 5 This is the signal timing diagram when the power drive circuit experiences overcurrent protection. Detailed Implementation
[0027] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.
[0028] like Figure 1 As shown, an overcurrent protection circuit for a power transistor includes a control circuit 101, a power drive circuit 102, and an overcurrent decision circuit 104.
[0029] The power drive circuit 102 for driving the load RL includes a plurality of power transistors to be protected against overcurrent, and is used to convert the current signal flowing through the plurality of power transistors to be protected against overcurrent into a voltage signal.
[0030] The overcurrent decision circuit 104 is electrically connected to the power drive circuit 102 and includes multiple logic devices. The multiple logic devices perform logic processing on the voltage signal to determine whether the current signal corresponding to the voltage signal is overcurrent and generate an overcurrent decision signal.
[0031] The control circuit 101 is electrically connected to the overcurrent decision circuit 104 and the power drive circuit 102 respectively. The control circuit 101 generates a power transistor on / off signal through the overcurrent decision signal to control the on / off of the plurality of power transistors to be overcurrent protected in the power drive circuit 102.
[0032] In this invention, while the power drive circuit 102 drives the load RL using a power transistor, current flows through the power transistor. Due to the on-resistance of the power transistor, the current signal flowing through the power transistor is converted into a voltage signal. The overcurrent decision circuit 104 uses logic devices to process the voltage signal generated by the power drive circuit 102, thereby generating an overcurrent decision signal indicating whether the current signal corresponding to the voltage signal is overcurrent. When the current signal flowing through the power transistor is overcurrent, the control circuit 101 controls the power transistor in the power drive circuit 102 to quickly turn off according to the overcurrent decision signal, thereby stopping the power drive circuit 102 from driving the load RL. Since the overcurrent protection circuit of the power transistor in this invention does not use a comparator for overcurrent discrimination, but instead uses a logic device to directly output an overcurrent decision signal to control the power transistor's on / off state, the response speed of the logic device is much higher than that of the comparator. Therefore, this invention can avoid the damage problem caused by the power transistor not turning off in time due to the current flowing through it being greater than the SOA current for a long time. In addition, this invention uses logic devices to implement overcurrent protection, which has a simple circuit structure, does not consume static current, and ensures the low power consumption design of the circuit.
[0033] In this specific embodiment, the power transistor is specifically a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). MOSFETs and IGBTs are commonly used as power transistors to drive loads.
[0034] In this specific embodiment: the overcurrent protection circuit of the power transistor of the present invention further includes a clamping protection circuit 103. Specifically, as shown below... Figure 2 As shown, the overcurrent decision circuit 104 is electrically connected to the power drive circuit 102 through the clamping protection circuit 103; the clamping protection circuit 103 is used to clamp the voltage signal and generate a clamping voltage signal; the multiple logic devices in the overcurrent decision circuit 104 specifically determine whether the current signal corresponding to the clamping voltage signal is overcurrent after performing logic processing on the clamping voltage signal, and generate an overcurrent decision signal.
[0035] Combination Figure 2 The working process of the overcurrent protection circuit for a power transistor according to the present invention is as follows:
[0036] The power drive circuit 102 drives the load through the plurality of power transistors to be protected from overcurrent, and converts the current signal flowing through the plurality of power transistors to be protected from overcurrent into a voltage signal and outputs it to the clamping protection circuit 103.
[0037] The clamping protection circuit 103 clamps the voltage signal output by the power drive circuit 102, generates a clamping voltage signal for protecting the overcurrent decision circuit 104, and outputs it to the overcurrent decision circuit 104.
[0038] The overcurrent decision circuit 104 performs logic processing on the clamping processing voltage signal output by the clamping protection circuit 103 through the multiple logic devices, generates an overcurrent decision signal, and outputs it to the control circuit 101.
[0039] The control circuit 101 generates a power transistor on / off signal through the overcurrent decision signal to control the on / off of the plurality of power transistors to be protected against overcurrent in the power drive circuit 102.
[0040] In this invention, the clamping processing circuit 103 is used to protect the overcurrent decision circuit 104, protect the logic devices in the overcurrent decision circuit 104 from burning out, and improve the stability of the circuit operation of this invention.
[0041] In this specific embodiment: as Figure 3As shown, the plurality of power transistors to be protected from overcurrent in the power drive circuit 102 include a first P-type power transistor H1, a second P-type power transistor H2, a first N-type power transistor L1, and a second N-type power transistor L2; the gates of the first P-type power transistor H1, the second P-type power transistor H2, the first N-type power transistor L1, and the second N-type power transistor L2 are all used to connect to the power transistor on / off signal output by the control circuit 101; the sources of the first P-type power transistor H1 and the second P-type power transistor H2 are both used to connect to a first level VM, and the sources of the first N-type power transistor L1 and the second N-type power transistor L2 are both grounded; the drain of the first P-type power transistor H1... The drain of the first P-type power transistor H1 is connected to the drain of the first N-type power transistor L1, and the drain of the second P-type power transistor H2 is connected to the drain of the second N-type power transistor L2. The nodes between the drains of the first P-type power transistor H1 and the first N-type power transistor L1, and between the drains of the second P-type power transistor H2 and the second N-type power transistor L2, are all outputs of the power drive circuit 102 and are used to connect to the two ends of the load RL respectively. The nodes between the drains of the first P-type power transistor H1 and the first N-type power transistor L1, and between the drains of the second P-type power transistor H2 and the second N-type power transistor L2, are also used to output the voltage signal to the clamping protection circuit 103.
[0042] Specifically, the load RL is an inductive load, such as a motor.
[0043] Specifically, in the power drive circuit 102, when the gate of the first P-type power transistor H1 receives a high level power transistor on / off signal GH1 from the control circuit 101, the first P-type power transistor H1 is turned off, and no current flows through the first P-type power transistor H1; when the first P-type power transistor H1 is turned on, and if the current flowing through the first P-type power transistor H1 is greater than a preset current value, due to the existence of the on-resistance of the first P-type power transistor H1 and the large voltage drop of the on-resistance, the drain voltage of the first P-type power transistor H1 is low, that is, the node OUT1 between the drain of the first P-type power transistor H1 and the drain of the first N-type power transistor L1 generates a low-level signal, and the low-level signal generated by the node OUT1 is output to the clamping protection circuit 103.
[0044] The operation of the second P-type power transistor H2 is the same as that of the first P-type power transistor H1.
[0045] The operation of the first N-type power transistor L1 is the same as that of the second N-type power transistor L2, and is similar to that of the first P-type power transistor H1. The only difference is that the turn-off levels of the first N-type power transistor L1 and the second N-type power transistor L2 are opposite to the turn-off level of the first P-type power transistor H1.
[0046] The first P-type power transistor H1 is turned on when its gate voltage is V lower than its source voltage. thp or V thp The above; V thp The turn-on voltage threshold of the first P-type power transistor H1 is typically around 1 to 2V. When GH1 is high, the first P-type power transistor H1 is turned off; when GH1 is low, the first P-type power transistor H1 can be fully turned on.
[0047] The first N-type power transistor L1 is turned on when its gate voltage is V higher than its source voltage. thn or V thn The above; V thn GL1 is the turn-on voltage threshold for the first N-type power transistor L1, typically around 1 to 2V. When GL1 is high, the first N-type power transistor L1 can be fully turned on; when GL1 is low, the first N-type power transistor L1 is turned off.
[0048] When there is no overcurrent in the power drive circuit 102, the first P-type power transistor H1 and the second N-type power transistor L2 are turned on simultaneously, or the second P-type power transistor H2 and the first N-type power transistor L1 are turned on simultaneously; the first P-type power transistor H1 and the first N-type power transistor L1 or the second P-type power transistor H2 and the second N-type power transistor L2 are not allowed to be turned on simultaneously.
[0049] In this invention, the first P-type power transistor H1, the second P-type power transistor H2, the first N-type power transistor L1, and the second N-type power transistor L2 form an H-type full-bridge drive circuit. The intermediate load RL is the driven load, typically an inductive motor. The function of this type of circuit is to drive the motor to rotate. In one state, the first P-type power transistor H1 and the second N-type power transistor L2 are simultaneously turned on, while the second P-type power transistor H2 and the first N-type power transistor L1 are simultaneously turned off. The current flows from the first level VM through the first P-type power transistor H1, the load RL, the second N-type power transistor L2, and then to GND. In the next state, the first P-type power transistor H1 and the second N-type power transistor L2 are simultaneously turned off, while the second P-type power transistor H2 and the first N-type power transistor L1 are simultaneously turned on. The current flows from the first level VM through the second P-type power transistor H2, the load RL, the first N-type power transistor L1, and then to GND. The power drive circuit 102 typically alternates between these two states to drive the motor. Whether the first P-type power transistor H1 and the second N-type power transistor L2 are simultaneously turned on for a longer period, or whether the second P-type power transistor H2 and the first N-type power transistor L1 are simultaneously turned on for a longer period, determines the direction of the current and the magnitude of the average current in the load RL; the alternation frequency determines the magnitude of the current ripple.
[0050] In this specific embodiment: as Figure 3 As shown, the clamping protection circuit 103 includes a first P-type clamping protection transistor PM1, a second P-type clamping protection transistor PM2, a first N-type clamping protection transistor NM1, and a second N-type clamping protection transistor NM2. The gates of both the first P-type clamping protection transistor PM1 and the second P-type clamping protection transistor PM2 are connected to the second voltage level VM-5. The gate of the first N-type clamping protection transistor NM1 is connected to the gate of the first N-type power transistor L1, and the gate of the second N-type clamping protection transistor NM2 is connected to the gate of the second N-type power transistor L2. The source of the first P-type clamping protection transistor PM1 and the drain of the first N-type clamping protection transistor NM1 are both connected to… At the node between the drain of the first P-type power transistor H1 and the drain of the first N-type power transistor L1, the source of the second P-type clamping protection transistor PM2 and the drain of the second N-type clamping protection transistor NM2 are both connected to the node between the drain of the second P-type power transistor H2 and the drain of the second N-type power transistor L2; the drain of the first P-type clamping protection transistor PM1, the drain of the second P-type clamping protection transistor PM2, the source of the first N-type clamping protection transistor NM1, and the source of the second N-type clamping protection transistor NM2 are all outputs of the clamping protection circuit 103, and are used to output the clamping processing voltage signal to the overcurrent decision circuit 104.
[0051] Specifically, in the clamping protection circuit 103, the four clamping protection transistors (first P-type clamping protection transistor PM1, second P-type clamping protection transistor PM2, first N-type clamping protection transistor NM1, and second N-type clamping protection transistor NM2) operate in the same way. The following explanation uses the first P-type clamping protection transistor PM1 as an example to illustrate its operation:
[0052] When the source of the first P-type clamping protection transistor PM1 receives a high level output from the power drive circuit 102, the first P-type clamping protection transistor PM1 will simultaneously output a high level to the overcurrent decision circuit 104 at its drain, and at the same time, the first P-type clamping protection transistor PM1 will protect the overcurrent decision circuit 104 to operate in the safe area; when the source of the first P-type clamping protection transistor PM1 receives a low level output from the power drive circuit 102, the first P-type clamping protection transistor PM1 will simultaneously output a low level to the overcurrent decision circuit 104 at its drain, and at the same time, the first P-type clamping protection transistor PM1 will protect the overcurrent decision circuit 104 to operate in the safe area.
[0053] In this specific embodiment: as Figure 3 As shown, the plurality of logic devices in the overcurrent decision circuit 104 include a first inverter INV1, a second inverter INV2, a first buffer BUF1, and a second buffer BUF2. The input terminal of the first inverter INV1 is connected to the drain of the first P-type clamping protection transistor PM1, the input terminal of the second inverter INV2 is connected to the drain of the second P-type clamping protection transistor PM2, the input terminal of the first buffer BUF1 is connected to the source of the first N-type clamping protection transistor NM1, and the input terminal of the second buffer BUF2 is connected to the source of the second N-type clamping protection transistor NM2. The output terminals of the first inverter INV1, the second inverter INV2, the first buffer BUF1, and the second buffer BUF2 are all outputs of the overcurrent decision circuit 104 and are used to output the overcurrent decision signal to the control circuit 101.
[0054] Specifically, in the overcurrent decision circuit 104, the operation of the first inverter INV1 is the same as that of the second inverter INV2. The operation of the first inverter INV1 is explained below using the first inverter INV1 as an example: When the input terminal of the first inverter INV1 receives a low level output from the clamping protection circuit 103, the inverter INV1 will output a high level, and the overcurrent decision circuit 104 will output this high level to the control circuit 101; when the input terminal of the first inverter INV1 receives a high level output from the clamping protection circuit 103, the inverter INV1 will output a low level, and the overcurrent decision circuit 104 will output this low level to the control circuit 101.
[0055] Specifically, in the overcurrent decision circuit 104, the operation of the first buffer BUF1 is the same as that of the second buffer BUF2. The operation of the first buffer BUF1 is explained below using the first buffer BUF1 as an example: When the input terminal of the first buffer BUF1 receives a low level output from the clamping protection circuit 103, the first buffer BUF1 will output a low level, and at this time the overcurrent decision circuit 104 outputs this low level to the control circuit 101; when the input terminal of the first buffer BUF1 receives a high level output from the clamping protection circuit 103, the first buffer BUF1 will output a high level, and at this time the overcurrent decision circuit 104 outputs this high level to the control circuit 101.
[0056] In this specific embodiment: as Figure 3As shown, the control circuit 101 includes a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, and a fourth NOR gate NOR4; the input terminal of the first NOR gate NOR1 is connected to the output terminal of the first inverter INV1, the output terminal of the first NOR gate NOR1 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is connected to the gate of the first P-type power transistor H1; the input terminal of the third NOR gate NOR3 is connected to the output terminal of the second inverter INV2, the output terminal of the third NOR gate NOR3 is connected to the input terminal of the fifth inverter INV5, and the output terminal of the fifth inverter INV5 is connected to the gate of the second P-type power transistor H2; the second NOR gate NOR4... The input of the NOT gate NOR2 is connected to the output of the first buffer BUF1, the output of the second NOR gate NOR2 is connected to the input of the fourth inverter INV4, and the output of the fourth inverter INV4 is connected to the gate of the first N-type power transistor L1; the input of the fourth NOR gate NOR4 is connected to the output of the second buffer BUF2, the output of the fourth NOR gate NOR2 is connected to the input of the sixth inverter INV6, and the output of the sixth inverter INV6 is connected to the gate of the second N-type power transistor L2; the outputs of the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6 are all outputs of the control circuit 101, and are used to output the power transistor on / off signal to the power drive circuit 102. The input terminal of the first NOR gate NOR1 is also used to input a first external signal INH1, which is specifically the switching control signal of the first P-type power transistor H1; the input terminal of the second NOR gate NOR2 is also used to input a second external signal INL1, which is specifically the switching control signal of the first N-type power transistor L1; the input terminal of the third NOR gate NOR3 is also used to input a third external signal INH2, which is specifically the switching control signal of the second P-type power transistor H2; the input terminal of the fourth NOR gate NOR4 is also used to input a fourth external signal INL2, which is specifically the switching control signal of the second N-type power transistor L2.
[0057] Specifically, in the control circuit 101, the first NOR gate NOR1 and the third inverter INV3 form one control circuit, the second NOR gate NOR2 and the fourth inverter INV4 form one control circuit, the third NOR gate NOR3 and the fifth inverter INV5 form one control circuit, and the fourth NOR gate NOR4 and the sixth inverter INV6 form one control circuit. The following example uses the first NOR gate NOR1 and the third inverter INV3: When the input terminal OCP_H1 of the first NOR gate NOR1 is high, the first NOR gate NOR1 outputs a low level to the third inverter INV3; at this time, the third inverter INV3 outputs a high-level turn-off signal to the power drive circuit 102.
[0058] Specifically, the first P-type power transistor H1, the second P-type power transistor H2, the first N-type power transistor L1, and the second N-type power transistor L2 form an H-type full-bridge drive circuit. The intermediate load RL is the driven load, typically an inductive motor. The function of this type of circuit is to drive the motor to rotate. In one state, the first P-type power transistor H1 and the second N-type power transistor L2 are simultaneously turned on, while the second P-type power transistor H2 and the first N-type power transistor L1 are simultaneously turned off. The current flows from the first level VM through the first P-type power transistor H1, the load RL, the second N-type power transistor L2, and then to GND. In the next state, the first P-type power transistor H1 and the second N-type power transistor L2 are simultaneously turned off, while the second P-type power transistor H2 and the first N-type power transistor L1 are simultaneously turned on. The current flows from the first level VM through the second P-type power transistor H2, the load RL, the first N-type power transistor L1, and then to GND. The power drive circuit 102 typically alternates between these two states to drive the motor. If the power transistors in the power drive circuit 102 are not experiencing overcurrent, and the motor needs to be driven normally, then the two pairs of power transistors need to be controlled to alternately turn on and off. Therefore, the first external signal INH1, the second external signal INL1, the third external signal INH2, and the fourth external signal INL2 are the switching control signals for these four power transistors, and these signals are typically square wave signals. For example, the second NOR gate NOR2 and the fourth inverter INV4 are the driving and control circuits for the first N-type power transistor L1; the first external signal INL1 is the input control signal. When the input level of the first external signal INL1 is high (VDD), the voltage at node GL1 is also high, and the gate-source voltage difference of the first N-type power transistor L1 will be higher than VDD. thn At a much higher voltage, such as 5V, the first N-type power transistor L1 can be fully turned on.
[0059] In this specific embodiment: the power supply terminals of the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fifth inverter INV5 are all connected to the first voltage level VM; the ground terminals of the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fifth inverter INV5 are all connected to the second voltage level VM-5; the power supply terminals of the first buffer BUF1, the second buffer BUF2, the fourth inverter INV4, and the sixth inverter INV6 are all connected to the third voltage level VDD; the ground terminals of the first buffer BUF1, the second buffer BUF2, the fourth inverter INV4, and the sixth inverter INV6 are all grounded. Preferably, the first voltage level VM is a high-voltage power supply level, the second voltage level VM-5 is a high-voltage power supply level and is 5V lower than the first voltage level VM, and the third voltage level VDD is a 5V level.
[0060] Specifically, VDD generally refers to a 5V level, and GND is ground. VM is a high-voltage power supply, and VM-5 is generated by another voltage conversion module, which is 5V lower than VM. VM-5 is ground relative to VM. If the ground terminals of the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fifth inverter INV5 are directly grounded instead of VM-5, then for the first P-type power transistor H1, the second P-type power transistor H2, the first P-type clamping protection transistor PM1, and the second P-type clamping protection transistor PM2, devices capable of withstanding the VM voltage between their gate and source stages would be required, which places high demands on the manufacturing process and may even be difficult to achieve. However, if only 5V needs to be withstood (the difference between the first level VM and the second level VM-5 is 5V), the manufacturing process requirements will be much lower, and the applicability will be greatly improved.
[0061] Figure 4 This is the signal timing diagram for the power drive circuit 102 when overcurrent protection is not triggered. (Refer to...) Figure 4 Here, the process protection process is explained using the first P-type power transistor H1, the first P-type clamping protection transistor PM1, the first inverter INV1, the first NOR gate NOR1, and the third inverter INV3 as an example: When the current I_H1 flowing through the first P-type power transistor H1 does not exceed the preset current Vth_OCP_H1, node OUT1 is always at a high level. After receiving the high-level signal output by node OUT1, the first P-type clamping protection transistor PM1 outputs a high level to the first inverter INV1. The output OCP_H1 of the first inverter INV1 is set to a low level. At this time, the first NOR gate NOR1 and the third inverter INV3 work normally, and the power transistor H1 is normally switched on and off.
[0062] Figure 5This is the signal timing diagram for the power drive circuit 102 when overcurrent protection occurs. (Refer to...) Figure 5 The process of process protection is explained using the first P-type power transistor H1, the first P-type clamping protection transistor PM1, the first inverter INV1, the first NOR gate NOR1, and the third inverter INV3 as an example: When the current I_H1 flowing through the first P-type power transistor H1 exceeds the preset current Vth_OCP_H1, node OUT1 is always at a low level. After receiving the low-level signal output by node OUT1, the first P-type clamping protection transistor PM1 outputs a low level to the first inverter INV1. The output OCP_H1 of the first inverter INV1 is set to a high level. At this time, the output of the first NOR gate NOR1 is low, and then the third inverter INV3 outputs a high-level power transistor on / off signal, causing the first P-type power transistor H1 to turn off.
[0063] This invention provides an overcurrent protection circuit for a power transistor that does not use a comparator for overcurrent protection, but instead employs logic devices. The response speed of a comparator is on the order of hundreds of nanoseconds, while the response speed of logic devices is generally on the order of nanoseconds. Therefore, the response speed of overcurrent protection implemented using logic circuits is much faster than that of a comparator, solving the problem of power transistor damage caused by the current flowing through it exceeding the SOA current for an extended period. Furthermore, the overcurrent protection circuit implemented using logic devices in this invention has a simple structure, does not consume quiescent current, ensures low power consumption, and solves the problem of high quiescent power consumption caused by complex comparator circuits requiring large quiescent current.
[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An overcurrent protection circuit for a power transistor, characterized by: It includes a control circuit (101), a power drive circuit (102), and an overcurrent decision circuit (104). The power drive circuit (102) for driving the load (RL) includes a plurality of power transistors to be overcurrent protected, and is used to convert the current signal flowing through the plurality of power transistors to be overcurrent protected into a voltage signal. The overcurrent decision circuit (104) is electrically connected to the power drive circuit (102) and includes multiple logic devices. The multiple logic devices perform logic processing on the voltage signal to determine whether the current signal corresponding to the voltage signal is overcurrent and generate an overcurrent decision signal. The control circuit (101) is electrically connected to the overcurrent decision circuit (104) and the power drive circuit (102) respectively. The control circuit (101) generates a power transistor on / off signal through the overcurrent decision signal to control the on / off of the plurality of power transistors to be overcurrent protected in the power drive circuit (102). It also includes a clamping protection circuit (103); the overcurrent decision circuit (104) is electrically connected to the power drive circuit (102) through the clamping protection circuit (103); The clamping protection circuit (103) is used to clamp the voltage signal and generate a clamping voltage signal; The multiple logic devices in the overcurrent decision circuit (104) specifically determine whether the current signal corresponding to the clamping voltage signal is overcurrent after performing logic processing on the clamping voltage signal, and generate the overcurrent decision signal. The plurality of power transistors to be overcurrent protected include a first P-type power transistor (H1), a second P-type power transistor (H2), a first N-type power transistor (L1), and a second N-type power transistor (L2). The clamping protection circuit (103) includes a first P-type clamping protection transistor (PM1), a second P-type clamping protection transistor (PM2), a first N-type clamping protection transistor (NM1), and a second N-type clamping protection transistor (NM2). The plurality of logic devices include a first inverter (INV1), a second inverter (INV2), a first buffer (BUF1), and a second buffer (BUF2); the input terminal of the first inverter (INV1) is connected to the drain of the first P-type clamping protection transistor (PM1), the input terminal of the second inverter (INV2) is connected to the drain of the second P-type clamping protection transistor (PM2), the input terminal of the first buffer (BUF1) is connected to the source of the first N-type clamping protection transistor (NM1), and the input terminal of the second buffer (BUF2) is connected to the source of the second N-type clamping protection transistor (NM2); the output terminals of the first inverter (INV1), the second inverter (INV2), the first buffer (BUF1), and the second buffer (BUF2) are all outputs of the overcurrent decision circuit (104) and are used to output the overcurrent decision signal to the control circuit (101).
2. The overcurrent protection circuit for a power tube according to claim 1, characterized by: The power transistor is specifically a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor.
3. The overcurrent protection circuit for the power transistor according to claim 1 or 2, characterized in that: The gates of the first P-type power transistor (H1), the second P-type power transistor (H2), the first N-type power transistor (L1), and the second N-type power transistor (L2) are all used to connect to the power transistor on / off signal output by the control circuit (101); the sources of the first P-type power transistor (H1) and the second P-type power transistor (H2) are both used to connect to a first level (VM), and the sources of the first N-type power transistor (L1) and the second N-type power transistor (L2) are both grounded; the drain of the first P-type power transistor (H1) is connected to the drain of the first N-type power transistor (L1), and the drain of the second P-type power transistor (H2) is connected to the first N-type power transistor (L1). The drain connection of the second N-type power transistor (L2) is described; the node between the drain of the first P-type power transistor (H1) and the drain of the first N-type power transistor (L1) and the node between the drain of the second P-type power transistor (H2) and the drain of the second N-type power transistor (L2) are both outputs of the power drive circuit (102) and are used to connect to the two ends of the load (RL) respectively; the node between the drain of the first P-type power transistor (H1) and the drain of the first N-type power transistor (L1) and the node between the drain of the second P-type power transistor (H2) and the drain of the second N-type power transistor (L2) are also used to output the voltage signal to the clamping protection circuit (103).
4. The overcurrent protection circuit for the power transistor according to claim 3, characterized in that: The gates of the first P-type clamping protection transistor (PM1) and the second P-type clamping protection transistor (PM2) are both used to connect to the second voltage level (VM-5). The gate of the first N-type clamping protection transistor (NM1) is connected to the gate of the first N-type power transistor (L1), and the gate of the second N-type clamping protection transistor (NM2) is connected to the gate of the second N-type power transistor (L2). The source of the first P-type clamping protection transistor (PM1) and the drain of the first N-type clamping protection transistor (NM1) are both connected to the junction between the drain of the first P-type power transistor (H1) and the drain of the first N-type power transistor (L1). At the point, the source of the second P-type clamping protection transistor (PM2) and the drain of the second N-type clamping protection transistor (NM2) are both connected to the node between the drain of the second P-type power transistor (H2) and the drain of the second N-type power transistor (L2); the drain of the first P-type clamping protection transistor (PM1), the drain of the second P-type clamping protection transistor (PM2), the source of the first N-type clamping protection transistor (NM1), and the source of the second N-type clamping protection transistor (NM2) are all outputs of the clamping protection circuit (103) and are used to output the clamping processing voltage signal to the overcurrent decision circuit (104).
5. The overcurrent protection circuit for the power transistor according to claim 4, characterized in that: The control circuit (101) includes a third inverter (INV3), a fourth inverter (INV4), a fifth inverter (INV5), a sixth inverter (INV6), a first NOR gate (NOR1), a second NOR gate (NOR2), a third NOR gate (NOR3), and a fourth NOR gate (NOR4); the input of the first NOR gate (NOR1) is connected to the output of the first inverter (INV1), and the output of the first NOR gate (NOR1) is connected to the third inverter (INV4). The input terminal of the third inverter (INV3) is connected to the input terminal of the first P-type power transistor (H1), and the output terminal of the third NOR gate (NOR3) is connected to the output terminal of the second inverter (INV2). The output terminal of the third NOR gate (NOR3) is connected to the input terminal of the fifth inverter (INV5), and the output terminal of the fifth inverter (INV5) is connected to the gate of the second P-type power transistor (H2). The input of the NOR gate (NOR2) is connected to the output of the first buffer (BUF1), the output of the second NOR gate (NOR2) is connected to the input of the fourth inverter (INV4), and the output of the fourth inverter (INV4) is connected to the gate of the first N-type power transistor (L1); the input of the fourth NOR gate (NOR4) is connected to the output of the second buffer (BUF2), the output of the fourth NOR gate (NOR2) is connected to the input of the sixth inverter (INV6), and the output of the sixth inverter (INV6) is connected to the gate of the second N-type power transistor (L2); the outputs of the third inverter (INV3), the fourth inverter (INV4), the fifth inverter (INV5), and the sixth inverter (INV6) are all outputs of the control circuit (101) and are used to output the power transistor on / off signal to the power drive circuit (102).
6. The overcurrent protection circuit for the power transistor according to claim 5, characterized in that: The input terminal of the first NOR gate (NOR1) is also used to input a first external signal (INH1), which is specifically the switching control signal of the first P-type power transistor (H1); the input terminal of the second NOR gate (NOR2) is also used to input a second external signal (INL1), which is specifically the switching control signal of the first N-type power transistor (L1); the input terminal of the third NOR gate (NOR3) is also used to input a third external signal (INH2), which is specifically the switching control signal of the second P-type power transistor (H2); the input terminal of the fourth NOR gate (NOR4) is also used to input a fourth external signal (INL2), which is specifically the switching control signal of the second N-type power transistor (L2).
7. The overcurrent protection circuit for the power transistor according to claim 5, characterized in that: The power supply terminals of the first inverter (INV1), the second inverter (INV2), the third inverter (INV3), and the fifth inverter (INV5) are all connected to the first voltage level (VM), and the ground terminals of the first inverter (INV1), the second inverter (INV2), the third inverter (INV3), and the fifth inverter (INV5) are all connected to the second voltage level (VM-5); the power supply terminals of the first buffer (BUF1), the second buffer (BUF2), the fourth inverter (INV4), and the sixth inverter (INV6) are all connected to the third voltage level (VDD), and the ground terminals of the first buffer (BUF1), the second buffer (BUF2), the fourth inverter (INV4), and the sixth inverter (INV6) are all grounded.
8. The overcurrent protection circuit for the power transistor according to claim 7, characterized in that: The first level (VM) is a high-voltage power supply level, the second level (VM-5) is a high-voltage power supply level and is 5V lower than the first level (VM), and the third level (VDD) is a 5V level.