signal detection circuit

Abstract

Disclosed is a signal detection circuit, characterized in that the circuit comprises an amplifier, a signal selector and an amplitude detector; an input end of the amplifier is used for inputting a to-be-detected signal and is connected with a first input end of the signal selector; an output end of the amplifier is used for outputting an amplified signal and is connected with a second input end of the signal selector; an output end of the signal selector is connected with an input end of the amplitude detector; the signal selector is used for periodically selecting the to-be-detected signal or the amplified signal to input to the amplitude detector; and the amplitude detector is used for outputting a trigger signal in the case that an output signal of the signal selector reaches a set threshold. Through periodic selection of the to-be-detected signal or the amplified signal for detection, the average power consumption of the signal detection circuit can be reduced while the detection sensitivity is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of circuit design, specifically to a signal detection circuit. Background Technology

[0002] Contactless communication systems such as Near Field Communication (NFC) are increasingly widely used in the Internet of Things (IoT) and wearable devices. Currently, these contactless communication systems mostly use dedicated circuits to detect external radio frequency (RF) fields. When no external RF field is detected, the main control circuit and RF front-end are in standby mode. When an external RF field is detected, the system wakes up from standby mode and enters normal communication mode to save system power consumption.

[0003] For radio frequency (RF) field detection circuits, on the one hand, they need to have sufficiently high sensitivity to ensure that they can still be detected even when the RF field strength is weak, thereby improving wireless communication distance and success rate. On the other hand, improving detection sensitivity requires more complex circuit design, which comes at the cost of increased power consumption, limiting the overall power consumption and lifespan of the system. Therefore, there is an urgent need for a circuit solution to address the problem of excessive power consumption in high-sensitivity RF field detection. Summary of the Invention

[0004] The purpose of this disclosure is to provide a signal detection circuit through one or more embodiments.

[0005] The signal detection circuit provided in this disclosure includes an amplifier, a signal selector, and an amplitude detector;

[0006] The amplifier's input terminal is used to input the signal to be detected and is connected to the first input terminal of the signal selector; the amplifier's output terminal is used to output an amplified signal and is connected to the second input terminal of the signal selector.

[0007] The output of the signal selector is connected to the input of the amplitude detector. The signal selector is used to periodically select the signal to be detected or the amplified signal to be input to the amplitude detector.

[0008] The amplitude detector is used to output a trigger signal when the output signal of the signal selector reaches a set threshold.

[0009] In some embodiments, the signal selector is specifically used for:

[0010] The signal to be detected is selected and input to the amplitude detector during the first duration of each cycle, and the amplified signal is selected and input to the amplitude detector during the second duration of the cycle, wherein the sum of the first duration and the second duration is equal to the duration of the cycle.

[0011] In some embodiments, the signal selector includes a first switch and a second switch.

[0012] The first terminal of the first switch is used to receive the signal to be detected, and the second terminal is connected to the amplitude detector;

[0013] The first terminal of the second switch is connected to the output terminal of the amplifier, and the second terminal is connected to the amplitude detector;

[0014] The first switch and the second switch are controlled to be switched on and off by mutually exclusive signals.

[0015] In some embodiments, the first switch is turned on and the second switch is turned off during a first duration of each cycle, and the first switch is turned off and the second switch is turned on during a second duration of the cycle, wherein the sum of the first duration and the second duration is equal to the duration of the cycle.

[0016] In some embodiments, the amplitude detector includes:

[0017] The first transistor has a first terminal coupled to the input signal through a first capacitor, a second terminal connected to the power supply voltage through a first pull-up circuit, and a third terminal grounded.

[0018] The second transistor has a first terminal connected to the second terminal of the first transistor, the second terminal connected to the power supply voltage, and a third terminal as the output terminal, which is connected in parallel with the second capacitor and the pull-down circuit.

[0019] In some embodiments, the amplitude detector further includes a bias circuit and a shaping circuit;

[0020] The bias circuit is used to provide a first bias voltage to the first transistor, the first bias voltage being set below a threshold voltage of the first transistor;

[0021] The shaping circuit is used to shape the output signal of the second transistor.

[0022] In some embodiments, the first pull-up circuit includes a third transistor; the bias circuit includes:

[0023] The fourth transistor has a first terminal connected to an external bias voltage and a second terminal connected to a power supply voltage. The fourth transistor is used to convert the external bias voltage into an input bias current.

[0024] The fifth transistor has a first terminal connected to a third terminal, and the third terminal and the second terminal are respectively connected to the third terminal of the fourth transistor and ground. The fifth transistor is used to output the first bias voltage of the first transistor.

[0025] The sixth transistor has its first terminal connected to the first terminal of the fifth transistor and its second terminal grounded. The sixth transistor is used to replicate the input bias current.

[0026] The seventh transistor has its first terminal connected to its third terminal, and its third terminal and second terminal are respectively connected to the third terminal of the sixth transistor and the power supply voltage. The seventh transistor is used to output the second bias voltage of the third transistor.

[0027] In some embodiments, the bias circuit further includes an eighth transistor connected in parallel with the sixth transistor, and the eighth transistor is connected in series with a switch.

[0028] In some embodiments, the amplitude detector is specifically used to: after outputting the trigger signal, stop outputting the trigger signal before detecting that the signal output by the signal selector is less than the set threshold.

[0029] In some embodiments, the circuit is used to detect radio frequency signals.

[0030] This disclosure discloses a signal detection circuit with one or more embodiments, including an amplifier, a signal selector, and an amplitude detector. The amplifier's input terminal is used to input a signal to be detected and is connected to a first input terminal of the signal selector. The amplifier's output terminal is used to output an amplified signal and is connected to a second input terminal of the signal selector. The signal selector's output terminal is connected to the amplitude detector's input terminal. The signal selector is used to periodically select either the signal to be detected or the amplified signal to be input to the amplitude detector. The amplitude detector is used to output a trigger signal when the output signal of the signal selector reaches a set threshold. By periodically selecting either the signal to be detected or the amplified signal for detection, the average power consumption of the signal detection circuit can be reduced while maintaining detection sensitivity. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of the structure of a circuit detection circuit provided in at least one embodiment of this disclosure;

[0033] Figure 2AA structural diagram of an amplitude detector in a circuit detection circuit provided in at least one embodiment of the present disclosure;

[0034] Figure 2B A structural diagram of another amplitude detector in a circuit detection circuit provided in at least one embodiment of this disclosure;

[0035] Figure 3 A flowchart illustrating a control method for a signal selector provided in at least one embodiment of this disclosure. Detailed Implementation

[0036] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0037] At least one embodiment of this disclosure provides a signal detection circuit for detecting external signals, such as radio frequency signals, and issuing a trigger signal when a signal is detected to wake up the main control circuit and radio frequency front-end circuit of a contactless communication system.

[0038] like Figure 1 As shown, the signal detection circuit includes an amplifier 101, a signal selector 102, and an amplitude detector 103.

[0039] The amplifier 101 has an input terminal for receiving the signal to be detected 111 and is connected to the first input terminal of the signal selector 102. The amplifier 101 also has an output terminal for outputting an amplified signal 112 and is connected to the second input terminal of the signal selector 102. The signal to be detected can be a radio frequency signal existing in external space.

[0040] That is, the signal to be detected 111 is input to the amplifier 101 on one hand and to the first input terminal of the signal selector 102 on the other hand, and the second input terminal of the signal selector 102 receives the amplified signal 112 output by the amplifier 101.

[0041] The output of the signal selector 102 is connected to the input of the amplitude detector 103. The signal selector 102 is used to periodically select the signal to be detected 111 or the amplified signal 112 to be input to the amplitude detector 103.

[0042] Specifically, the signal selector 102 allows only one signal to be output at any given time. By alternately outputting the signal to be detected 111 and the amplified signal 112 for a set duration, the signal to be detected 111 or the amplified signal 112 can be periodically selected.

[0043] The amplitude detector 103 is used to output a trigger signal 114 when the output signal of the signal selector 102 reaches a set threshold.

[0044] When the signal selector 102 selects the signal to be detected 111, the amplifier 101 is disabled, and the amplitude detector 103 directly detects the signal to be detected. That is, when the signal to be detected reaches the set threshold, the trigger signal 114 is output. At this time, the signal detection circuit is in a low-sensitivity mode. When the signal selector 102 selects the amplified signal 112 output by the amplifier 101, the amplifier 101 is enabled, and the amplitude detector 103 detects the amplified signal, which is in a high-sensitivity mode. In the high-sensitivity mode, if the gain of the amplifier 101 is N (N is a positive number greater than 1), the intensity of the signal to be detected 111 only needs to reach one-Nth of the detection value of the amplitude detector 103 to be detected, thus increasing the sensitivity by N times.

[0045] In this embodiment, the signal detection circuit includes an amplifier, a signal selector, and an amplitude detector. The input terminal of the amplifier is used to input the signal to be detected and is connected to the first input terminal of the signal selector. The output terminal of the amplifier is used to output an amplified signal and is connected to the second input terminal of the signal selector. The output terminal of the signal selector is connected to the input terminal of the amplitude detector. The signal selector is used to periodically select either the signal to be detected or the amplified signal to be input to the amplitude detector. The amplitude detector is used to output a trigger signal when the output signal of the signal selector reaches a set threshold. By periodically selecting either the signal to be detected or the amplified signal for detection, the average power consumption of the signal detection circuit can be reduced while ensuring detection sensitivity.

[0046] After introducing the basic principles of this disclosure, the following describes various non-limiting embodiments of this disclosure, taking the signal to be detected as a radio frequency signal as an example.

[0047] In some embodiments, the signal selector 102 is specifically configured to select the radio frequency signal to be detected to be input to the amplitude detector within a first duration t1 of each period T, and to select the amplified signal to be output to the amplitude detector within a second duration t2 of the period, wherein the sum of the first duration t1 and the second duration t2 is equal to the duration T of the period.

[0048] That is, under the control of the signal selector 102, radio frequency signal detection is performed in low sensitivity mode. If no radio frequency signal is detected after a first time delay t1, the system switches to high sensitivity mode. If no radio frequency signal is detected after a second time delay t2, the system switches to low sensitivity mode. This process is repeated, with a fixed delay, until a radio frequency signal is detected.

[0049] Assuming the first settable duration t1 is k times the second duration t2 (k is a positive number greater than 1), since amplifier 101 is only enabled in high-sensitivity mode, the signal detection circuit proposed in this embodiment can reduce the average power consumption of amplifier 101 by a factor of 1+k compared to high-sensitivity mode throughout the entire cycle. To minimize power consumption, the value of k can be increased as much as possible, that is, t1 can be set as large as possible and t2 can be set as small as possible, where the minimum value of t2 should be greater than the settling time after amplifier 101 is enabled to ensure that the high-sensitivity mode has correct output. Furthermore, the minimum duration t0 of the effective radio frequency field can be determined according to the actual application scenario, and t1 can be determined based on the difference between t0 and t2.

[0050] Furthermore, for radio frequency fields lasting longer than t1+t2, the detection sensitivity of this signal detection circuit can reach the same level as high sensitivity.

[0051] In some embodiments, amplifier 101 can use a closed-loop structure such as an inverting proportional amplifier to obtain stable gain and ensure consistent sensitivity of RF signal detection when the operating environment changes. To avoid identification errors caused by amplified low-frequency and high-frequency noise, resulting in false wake-ups of the circuit, amplifier 101 can amplify only signals with frequencies close to the RF field carrier frequency fc of the signal to be detected. To achieve this, on the one hand, a capacitor can be added to the input terminal of amplifier 101 to enable high-pass filtering of the input signal 111 through capacitive coupling; on the other hand, the bandwidth of amplifier 101 itself can be used to achieve low-pass filtering, thereby achieving band-pass filtering of the amplifier.

[0052] Those skilled in the art will understand that appropriate input capacitors and amplifier bandwidths can be selected based on the carrier frequency range of the radio frequency field to be identified, ensuring that the passband center frequency equals fc. Furthermore, since the gain of amplifier 101 determines the sensitivity of radio frequency field detection, the largest possible gain can be selected while ensuring bandwidth.

[0053] In some embodiments, the signal selector 102 may include a first switch and a second switch. The first switch has a first terminal for receiving a signal to be detected and a second terminal connected to an amplitude detector 103. The second switch has a first terminal connected to the output of an amplifier 101 and a second terminal connected to the amplitude detector 103. The first and second switches are controlled by mutually exclusive signals. That is, at any given time, only one set of switches (the first and second switches) is active, thereby enabling selection between the signal to be detected and the amplified signal.

[0054] In one example, during the first duration of each cycle, the first switch is on and the second switch is off, the signal selector outputs the signal to be detected, and the signal detection circuit is in a low-sensitivity mode; during the second duration of the cycle, the first switch is off and the second switch is on, the signal selector outputs an amplified signal, and the signal detection circuit is in a high-sensitivity mode. In this case, the sum of the first duration and the second duration equals the duration of the cycle.

[0055] In some embodiments, the main structure of the amplitude detector includes an AC / DC conversion circuit, which converts an AC input signal into a DC signal. The AC / DC conversion circuit may include a first transistor, whose first terminal is coupled to the input signal through a first capacitor, its second terminal is connected to the power supply voltage through a first pull-up circuit, and its third terminal is grounded; and a second transistor, whose first terminal is connected to the second terminal of the first transistor, its second terminal is connected to the power supply voltage, and its third terminal is the output terminal of the amplitude detector, connected in parallel with the second capacitor and the pull-down circuit.

[0056] Taking a MOSFET as an example in the amplitude detector, see [link to relevant documentation]. Figure 2A The diagram shows the structure of the amplitude detector. The AC / DC conversion circuit 201 includes an N-type first transistor M1 and a P-type second transistor M2. The gate of the first transistor M1 is connected to a first bias voltage VB1 via a resistor R1 and to a first capacitor C1, to convert the input signal 211 (i.e., ...) into a DC / DC converter. Figure 1 The output signal 113 of the signal selector 102 is coupled to the gate of the first transistor M1. The source of the first transistor M1 is connected to the common ground terminal VSS, and the drain is connected to the power supply voltage VDD via the first pull-up circuit 21. The gate of the second transistor M2 is connected to the drain of the first transistor M1, the source is connected to the power supply voltage VDD, and the drain is connected to the common ground terminal VSS via the pull-down circuit 22. A second capacitor C2 is also connected in parallel between the drain and VSS.

[0057] The second transistor M2 is a transconductance amplifier. It generates different pull-up currents depending on the gate voltage 212. The output voltage 213 of the AC / DC converter circuit 201, which is also the output voltage across the second capacitor C2, is determined by the pull-up current generated by the transconductance amplifier M2 and the pull-down current generated by the pull-down circuit 22. Since the gate of the transconductance amplifier M2 is connected between the first pull-up circuit 21 and the drain of the first transistor M1, when the first pull-up circuit 21 generates a fixed pre-pull-up current, the first transistor M1 acts as a pre-pull-down circuit. Because the gate of the first transistor M1 is connected to the input signal via AC coupling, it can generate a varying pre-pull-down current. Therefore, changes in the input signal 211 will cause changes in the output voltage 213.

[0058] In this embodiment, the first bias voltage VB1 is set slightly lower than the threshold voltage of the first transistor M1. For example, if the first bias voltage VB1 is lower than the threshold voltage of the first transistor M1 by a set difference Δ, then when the amplitude of the input signal 211 is lower than Δ, the first transistor M1 is always in the weak inversion region, the current is low and the change with the amplitude of the input signal 211 is small, the gate voltage 212 of the second transistor M2 is high, and the output voltage 213 is low. When the amplitude of the input signal 211 is greater than Δ, the gate voltage of the first transistor M1 is higher than the threshold voltage and it is turned on. The gate voltage 212 decreases, causing the second transistor M2 to turn on. The resulting pull-up current and the positive terminal voltage of the second capacitor C2 increase accordingly, thereby realizing the discrimination of the amplitude of the input signal 211 by the output voltage 213.

[0059] In some embodiments, the amplitude detector further includes a bias circuit and a shaping circuit; wherein the bias circuit is used to provide a first bias voltage VB1 to the first transistor; and the shaping circuit is used to shape the output signal of the second transistor. The shaping circuit may, for example, be an amplifier circuit used to amplify the positive terminal voltage of the second capacitor C2, converting the discrimination result into a digital signal with a magnitude equal to the power supply voltage or ground.

[0060] refer to Figure 2B The circuit diagram of the amplitude detector shown illustrates that the shaping circuit 203 can employ a structure of two cascaded inverters to shape the output signal 213 of the AC / DC conversion circuit 201 into a digital signal 214, facilitating further processing by the main control circuit of the contactless communication system. The flip threshold of the shaping circuit corresponds to the voltage of the output signal 213 when the input signal 211 reaches the RF field identification point. This flip threshold can be adjusted by changing the size of the transistors in the first-stage inverter.

[0061] Still referencing Figure 2BThe circuit diagram of the amplitude detector shown includes a first pull-up circuit 21 in the AC / DC conversion circuit 201, which may include a P-type third transistor M3, and a pull-down circuit 22, which may include a second resistor R2. The gate of the third transistor M3 is used to input a second bias voltage VB2, its source is connected to the power supply voltage VDD, and its drain is connected to the drain of the first transistor M1. In this case, voltage 212 is determined by both the third transistor M3 and the first transistor M1. The DC operating point of the third transistor M3 is determined by the fixed second bias voltage VB2, and the DC operating point of the first transistor M1 is determined by the fixed first bias voltage VB1. The bias circuit 202, which provides bias voltages to the first transistor M1 and the third transistor M3, includes:

[0062] The fourth transistor M4 has its first terminal (gate) connected to the external bias voltage VB and its second terminal (source) connected to the power supply voltage VDD. The fourth transistor M4 is used to convert the external bias voltage VB into an input bias current.

[0063] The fifth transistor M5 has its first terminal (gate) connected to its third terminal (drain), and its third terminal (drain) and second terminal (source) connected to the third terminal (drain) of the fourth transistor M4 and ground VSS, respectively. The fifth transistor M5 is used to output the first bias voltage VB1 of the first transistor M1.

[0064] The sixth transistor M6 has its first terminal (gate) connected to the first terminal (gate) of the fifth transistor M5, and its second terminal (source) grounded. The sixth transistor M6 is used to replicate the input bias current.

[0065] The seventh transistor M7 has its first terminal (gate) connected to its third terminal (drain), and its third terminal (drain) and second terminal (source) connected to the third terminal (drain) of the sixth transistor M6 and the power supply voltage VDD, respectively. The seventh transistor M7 is used to cooperate with the sixth transistor M6 to generate the second bias voltage VB2 of the third transistor M3.

[0066] In some embodiments, the bias circuit 202 further includes an eighth transistor M8 connected in parallel with the sixth transistor M6, and the eighth transistor M8 is connected in series with the switch S1.

[0067] By controlling the on or off state of switch S1, it can be determined whether the eighth transistor M8 is connected to the circuit. When switch S1 is on, the eighth transistor M8 is connected to the circuit, and the pull-up current of the third transistor M3 increases. At this time, a larger pull-down current is required, that is, a larger amplitude input signal 211, in order to make the output signal 214 flip. Therefore, the eighth transistor M8 and switch S1 realize the adjustment of detection sensitivity.

[0068] In some embodiments, the amplitude detector is specifically used to: after outputting the trigger signal, stop outputting the trigger signal before detecting that the signal output by the signal selector is less than the set threshold. That is, for continuous radio frequency signals, only one trigger signal is output to activate the contactless communication system.

[0069] In some embodiments, the signal selector can utilize Figure 3 Control is performed using the method shown. For example... Figure 3 As shown, the control method begins at step 301; at step 302, variables count1 and count2 are set to 0, and these variables are used to count to generate delays t1 and t2; at step 303, the control signal selector selects the signal to be detected 111 to be input to the amplitude detector, that is, the circuit detects the radio frequency field in a low-sensitivity mode; at step 304, based on the trigger signal 114 output by the amplitude detection circuit 103, it is determined whether a radio frequency field is detected. If a radio frequency field is detected, the detection is completed at step 311; otherwise, at step 305, the variable count1 is set to 0. The value of 1 is incremented by 1. At step 306, it is confirmed whether the value of variable count1 is less than P1. If the value of variable count1 is less than P1, the process returns to step 303 to continue detection in low-sensitivity mode. Otherwise, at step 307, the control signal selector selects the amplified signal 112 to be input to the amplitude detector, i.e., switching to high-sensitivity mode for detection. At step 308, based on the trigger signal 114 output by the amplitude detection circuit 103, it is determined whether a radio frequency field is detected. If a radio frequency field is detected, the detection is completed at step 311. Otherwise, at step 309, the value of variable count2 is incremented by 1. At step 310, it is checked whether the value of variable count2 is less than P2. If the value of variable count2 is less than P2, the process returns to step 307 to continue detection in high-sensitivity mode. Otherwise, at step 302, variables count1 and count2 are set to 0, and the next round of detection is performed. In this method, the values ​​of P1 and P2 are set according to the expected delays t1 and t2.

[0070] Those skilled in the art will understand that one or more embodiments of this specification can be provided as a method, circuit, or computer program product. Therefore, one or more embodiments of this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0071] The same or similar parts between the various embodiments in this specification can be referred to in relation to each other, and each embodiment focuses on describing the differences from other embodiments.

[0072] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0073] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.

[0074] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various circuit modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and circuits can generally be integrated together in a single software product or packaged into multiple software products.

[0075] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0076] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the protection scope of one or more embodiments of this specification.

Claims

1. A signal detection circuit, characterized in that, The circuit includes an amplifier, a signal selector, and an amplitude detector; The amplifier's input terminal is used to input the signal to be detected and is connected to the first input terminal of the signal selector; the amplifier's output terminal is used to output an amplified signal and is connected to the second input terminal of the signal selector. The output of the signal selector is connected to the input of the amplitude detector. The signal selector is used to periodically select the signal to be detected or the amplified signal to be input to the amplitude detector. The amplitude detector includes: The first transistor has a first terminal coupled to the input signal through a first capacitor, a second terminal connected to the power supply voltage through a first pull-up circuit, and a third terminal grounded. The second transistor has a first terminal connected to the second terminal of the first transistor, the second terminal connected to the power supply voltage, and the third terminal as the output terminal, which is connected to a second capacitor in parallel and a pull-down circuit. The amplitude detector is used to output a trigger signal when the output signal of the signal selector reaches a set threshold.

2. The circuit according to claim 1, characterized in that, The signal selector is specifically used for: The signal to be detected is selected and input to the amplitude detector during the first duration of each cycle, and the amplified signal is selected and input to the amplitude detector during the second duration of the cycle, wherein the sum of the first duration and the second duration is equal to the duration of the cycle.

3. The circuit according to claim 1, characterized in that, The signal selector includes a first switch and a second switch. The first terminal of the first switch is used to receive the signal to be detected, and the second terminal is connected to the amplitude detector; The first terminal of the second switch is connected to the output terminal of the amplifier, and the second terminal is connected to the amplitude detector; The first switch and the second switch are controlled to be switched on and off by mutually exclusive signals.

4. The circuit according to claim 3, characterized in that, During the first duration of each cycle, the first switch is turned on and the second switch is turned off, and during the second duration of the cycle, the first switch is turned off and the second switch is turned on, wherein the sum of the first duration and the second duration is equal to the duration of the cycle.

5. The circuit according to claim 1, characterized in that, The amplitude detector also includes a bias circuit and a shaping circuit; The bias circuit is used to provide a first bias voltage to the first transistor, the first bias voltage being set below a threshold voltage of the first transistor; The shaping circuit is used to shape the output signal of the second transistor.

6. The circuit according to claim 5, characterized in that, The first pull-up circuit includes a third transistor; the bias circuit includes: The fourth transistor has a first terminal connected to an external bias voltage and a second terminal connected to a power supply voltage. The fourth transistor is used to convert the external bias voltage into an input bias current. The fifth transistor has a first terminal connected to a third terminal, and the third terminal and the second terminal are respectively connected to the third terminal of the fourth transistor and ground. The fifth transistor is used to output the first bias voltage of the first transistor. The sixth transistor has its first terminal connected to the first terminal of the fifth transistor and its second terminal grounded. The sixth transistor is used to replicate the input bias current. The seventh transistor has its first terminal connected to its third terminal, and its third terminal and second terminal are respectively connected to the third terminal of the sixth transistor and the power supply voltage. The seventh transistor is used to output the second bias voltage of the third transistor.

7. The circuit according to claim 6, characterized in that, The bias circuit also includes an eighth transistor connected in parallel with the sixth transistor, and the eighth transistor is connected in series with the switch.

8. The circuit according to claim 1, characterized in that, The amplitude detector is specifically used to: after outputting the trigger signal, stop outputting the trigger signal before detecting that the signal output by the signal selector is less than the set threshold.

9. The circuit according to any one of claims 1 to 8, characterized in that, The circuit is used to detect radio frequency signals.

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