Delay-locked loop device and delay method

Abstract

A delay method includes the operations of a delay line delaying a first clock signal by a delay time to generate an output signal, a controller delaying the output signal by a first time interval to generate a first signal, the controller delaying the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal, and the controller controlling the delay line to adjust the delay time according to the first signal and the second clock signal. Also disclosed is a delay-locked loop apparatus.

Description

Technical Field

[0001] This disclosure relates to a delay technology, and more particularly to a delay phase-locked loop device and delay method. Background Technology

[0002] Delay-locked loop (PLL) devices are used to delay clock signals by a certain time to output a corresponding signal. However, PLL devices require an external voltage to operate. When the external voltage is unstable, the delay time is affected, and latency jumps can occur. Therefore, technological development to overcome these problems is an important issue in this field. Summary of the Invention

[0003] This invention includes a delay method. The delay method includes the following operations: a delay line delays a first clock signal by a delay time to generate an output signal; a controller delays the output signal by a first time interval to generate a first signal; the controller delays the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal; and the controller controls the delay line to adjust the delay time based on the first signal and the second clock signal.

[0004] In some embodiments, the delay method further includes: generating a second signal based on the first signal, wherein the frequency of the second signal is equal to or less than half the frequency of the first signal, and the edge of the second signal and the edge of the first signal are at the same time.

[0005] In some embodiments, adjusting the delay time includes adjusting the delay time based on the voltage level of the second signal at the edge of the second clock signal.

[0006] In some embodiments, adjusting the delay time includes: increasing the delay time in response to the voltage level being a first voltage level; and decreasing the delay time in response to the voltage level being a second voltage level different from the first voltage level.

[0007] In some embodiments, the time interval between the edge of the second clock signal and the edge of the first clock signal is substantially equivalent to the second time interval, and adjusting the delay time further includes adjusting the delay time until the edge of the output signal is aligned with the edge of the first clock signal.

[0008] In some embodiments, the delay method further includes: delaying the first signal by the first time interval to generate a third signal; generating a bit based on the voltage level of the second signal at that time and the voltage level of the third signal at that time, wherein the bit indicates the time interval between the edge of the output signal and the edge of the first clock signal; and adjusting the delay time based on the bit.

[0009] In some embodiments, the delay method further includes: increasing the delay time in response to a bit corresponding to the second signal having a first logic value; and decreasing the delay time in response to a bit corresponding to the second signal having a second logic value different from the first logic value.

[0010] In some embodiments, adjusting the delay time includes: generating a bit having a first logic value in response to a third time interval between the edge of the output signal and the edge of the first clock signal being greater than or equal to a fourth time interval; generating the bit having a second logic value different from the first logic value in response to the third time interval being less than the fourth time interval; adjusting the delay time with a fifth time interval in response to the bit having the first logic value; and adjusting the delay time with a sixth time interval different from the fifth time interval in response to the bit having the second logic value.

[0011] In some embodiments, the fourth time interval is approximately three-eighths of the clock cycle of the first clock signal, and the fifth time interval is greater than the sixth time interval.

[0012] This invention also includes a delay phase-locked loop (PLL) device. The delay PLL device includes a first delay line and a controller. The first delay line delays a first clock signal by a delay time to generate an output signal. The controller controls the first delay line based on a plurality of bits to adjust the delay time. The controller includes a second delay line, a frequency divider, and a flip-flop circuit. The second delay line generates a second clock signal based on the first clock signal. The frequency divider generates a first signal based on the output signal, wherein the frequency of the first signal is less than the frequency of the output signal. The flip-flop circuit generates bits based on the first signal and the second clock signal.

[0013] In some embodiments, the controller further includes a plurality of delay lines for delaying the output signal to generate a second signal, and the frequency divider is further used to generate the first signal based on the second signal, wherein the frequency of the first signal is less than or equal to half the frequency of the second signal.

[0014] In some embodiments, the delay lines include: a third delay line for delaying the second signal by a first time interval to generate a third signal; a fourth delay line for delaying the third signal by the first time interval to generate a fourth signal; and a fifth delay line for delaying the fourth signal by the first time interval to generate a fifth signal, wherein the duration of the first time interval is substantially equal to one-eighth of a clock cycle of the first clock signal.

[0015] In some embodiments, the delay lines include: a third delay line for delaying the output signal by a first time interval to generate a second signal, wherein the frequency divider is further configured to receive the second signal and generate the first signal based on the second signal; and the second delay line is further configured to delay the first clock signal by a second time interval to generate the second clock signal, wherein the second time interval is shorter than the first time interval.

[0016] In some embodiments, the first flip-flop circuit of the flip-flop circuit is triggered by the edge of the second clock signal to generate the first bit of the bits based on the voltage level of the first signal at the moment of the edge of the second clock signal.

[0017] In some embodiments, the controller is further configured to increase the delay time in response to the first bit having a first logic value, and to decrease the delay time in response to the first bit having a second logic value different from the first logic value.

[0018] In some embodiments, the controller further includes: logic circuitry for performing multiple logic operations based on the bits to generate a second bit, the second bit indicating the time interval at which the output signal is offset, wherein the controller is further configured to adjust the delay time based on the second bit.

[0019] In some embodiments, the first delay line includes a plurality of buffers for delaying the first clock signal to generate the output signal, and the controller is further configured to adjust the number of the buffers by a first number in response to the second bit having a first logic value, and the controller is further configured to adjust the number of the buffers by a second number different from the first number in response to the second bit having a second logic value different from the first logic value.

[0020] This invention also includes a delay method. The delay method includes the following operations: a delay line delays a first clock signal by a delay time to generate an output signal; a controller delays the output signal by a first time interval to generate a first signal; the controller delays the first clock signal by a second time interval approximately half the first time interval to generate a second clock signal; the controller generates the second signal based on the first signal, wherein the frequency of the second signal is less than or equal to the frequency of the first signal, and the edge of the second signal is at the same time as the edge of the first signal; the controller delays the first signal by the first time interval to generate a third signal; and the controller controls the delay line to adjust the delay time based on the voltage level of the second signal at the edge of the second clock signal and the voltage level of the third signal at the edge of the second clock signal.

[0021] In some embodiments, adjusting the delay time includes: increasing the delay time in response to the voltage level of the second signal being a first voltage level; and decreasing the delay time in response to the voltage level of the second signal being a second voltage level different from the first voltage level.

[0022] In some embodiments, adjusting the delay time includes: generating a first element based on the voltage level of the second signal and the voltage level of the third signal, wherein the first element indicates whether a third time interval between the edge of the output signal and the edge of the first clock signal is less than a fourth time interval; adjusting the delay time with a fifth time interval in response to the third time interval being less than the fourth time interval; and adjusting the delay time with a sixth time interval greater than the fifth time interval in response to the third time interval being greater than or equal to the fourth time interval. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a delay phase-locked loop device according to some embodiments of the present invention.

[0024] Figure 2 A schematic diagram of delay lines illustrated for some embodiments of the system architecture according to the present invention.

[0025] Figure 3 Timing diagrams illustrating the operation of a delay phase-locked loop device according to some embodiments of the present invention.

[0026] Figure 4 This is a schematic diagram of a controller according to some embodiments of the present invention.

[0027] Figure 5 This is a schematic diagram of a controller according to some embodiments of the present invention.

[0028] Figure 6 Timing diagrams of signals relating to a delay phase-locked loop device and a controller, as illustrated in some embodiments of the present invention.

[0029] Figures 7A to 7H Timing diagrams of signals relating to a delay phase-locked loop device and a controller, as illustrated in some embodiments of the present invention.

[0030] Figure 7I This is a truth table of bits for the delay and forward shift of the corresponding output signal as illustrated in some embodiments of the present invention.

[0031] Figure 8 This is a schematic diagram of a controller according to some embodiments of the present invention.

[0032] Figures 9A to 9NTiming diagrams of signals relating to a delay phase-locked loop device and a controller, as illustrated in some embodiments of the present invention.

[0033] Figure 10 This is a schematic diagram of a logic circuit according to some embodiments of the present invention.

[0034] Figure 11 This is a truth table of bits for the delay and forward shift of the corresponding output signal as illustrated in some embodiments of the present invention. Detailed Implementation

[0035] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0038] It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, relative terms, such as "below" or "bottom" and "above" or "top," are used to describe the relationship between one element and another shown in the accompanying drawings. It is understood that relative terms are used to describe different orientations of the device beyond those depicted in the drawings. For example, if the device in the drawings is flipped, an element that was originally located "below" another element will be oriented "above" another element. The illustrative term "below" may include both "below" and "above" orientations depending on the specific orientation of the drawing. Similarly, if the device in the drawings is flipped, an element that was originally located "below" or "under" another element will be oriented "above" another element. The illustrative term "below" or "under" may include both "above" and "above" orientations.

[0039] The terms “about,” “approximately,” or “roughly about” as used in this document generally refer to an error or range of approximately 20 percent, preferably approximately 10 percent, and more preferably approximately 5 percent. Unless otherwise specified, all values ​​mentioned herein are considered approximate, i.e., the error or range indicated by “about,” “approximately,” or “roughly about.”

[0040] The following describes several embodiments of this invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the invention. That is, these practical details are not essential in some embodiments disclosed herein. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0041] Figure 1 This is a schematic diagram illustrating a delay-locked loop device 100 according to some embodiments of the present invention. Figure 1 As shown, the delay phase-locked loop device 100 is used to generate an output signal SOUT1 based on the clock signal CLKIN, and to output the output signal SOUT1 to the pad 114.

[0042] like Figure 1As shown, the delay phase-locked loop device 100 includes a receiver 102, a command decoder 104, a delay line 106, an amplifier 108, a clock tree 110, an output current driver 112, and a controller 150. The receiver 102 receives a clock signal CLKIN and a reference voltage VRF, and generates a signal S1 and a clock signal CLK1. In some embodiments, the waveforms of signal S1 and clock signal CLK1 are substantially equivalent to the waveform of clock signal CLKIN. The command decoder 104 generates a signal S2 based on signal S1. In some embodiments, the waveform of signal S2 is substantially equivalent to the waveform of signal S1. The delay line 106 delays signal S2 to generate signal S3. In other words, signal S3 has a waveform similar to signal S2, but the waveform of signal S3 is delayed by a time interval, which is also referred to as the delay time of the delay phase-locked loop device 100. The amplifier 108 amplifies signal S3 to generate signal S4. Clock tree 110 is used to calculate and generate signal S5 based on signal S4. In some embodiments, the waveform of signal S5 is substantially equivalent to the waveform of signal S4 or an amplified version of the waveform of signal S4. Output current driver 112 is used to generate output signals SOUT1 and SOUT2 based on signal S5. In some embodiments, the waveforms of output signals SOUT1 and SOUT2 are substantially equivalent to the waveform of signal S5. Controller 150 is used to generate a plurality of control signals SC based on clock signal CLK1 and output signal SOUT2 to control delay line 106.

[0043] like Figure 1 As shown, controller 150 performs operations OP1 and OP2 based on clock signal CLK1 and output signal SOUT2. Operation OP1 determines the direction of adjustment of the delay time caused by delay line 106. Operation OP2 determines the amount of time interval used to adjust the delay time. Details of operations OP1 and OP2 are described below. Figure 2 , Figure 3 , Figure 4 , Figure 8 and Figure 10 The embodiments are further illustrated below.

[0044] Figure 2 This is a schematic diagram illustrating a delay line 200 according to some embodiments of the system architecture of the present invention. The delay line 200 is... Figure 1 The diagram shows one embodiment of delay line 106. In some embodiments, delay line 200 is used to delay the signal ZIN to generate the signal ZOUT. In other words, the signal ZOUT has a waveform similar to the signal ZIN, but the waveform of the signal ZOUT is delayed by a time interval, which is also referred to as the delay time. In some embodiments, the signal ZIN corresponds to... Figure 1The signals S1 and S2 are shown, along with the clock signals CLKIN and CLK1. The signal ZOUT corresponds to... Figure 1 The signals S3 to S5 and the output signals SOUT1 and SOUT2 are shown.

[0045] like Figure 2 As shown, delay line 200 includes multiple buffers IN(1) to IN(n), where n is a positive integer. Each of buffers IN(1) to IN(n) is coupled to voltage VDD and ground voltage GND. In some embodiments, the delay time between signals ZIN and ZOUT is proportional to the number of buffers IN(1) to IN(n). In some embodiments, buffers IN(1) to IN(n) are implemented as inverters.

[0046] Please refer to Figure 1 and Figure 2 The controller 150 controls the number of buffers IN(1) to IN(n) to increase or decrease the delay time between signals ZIN and ZOUT. In operation OP1, the controller 150 increases or decreases the delay time based on bit B5. In some other embodiments, the controller 150 may increase or decrease the delay time based on bit B1. Details of bits B1 and B5 are provided below. Figure 4 and Figure 8 The embodiments are further illustrated below.

[0047] In some embodiments, the delay time between signals ZIN and ZOUT may be affected by the voltage level of voltage VDD. For example, when the voltage level of voltage VDD increases, the delay time decreases, and when the voltage level of voltage VDD decreases, the delay time increases.

[0048] Figure 3 Timing diagram 300 illustrating the operation of a delay phase-locked loop device 100 according to some embodiments of the present invention. Figure 3 As shown, timing diagram 300 comprises six periods P31 to P36. Each of periods P31 to P36 corresponds to the clock cycle of the clock signal CLKIN. Each of periods P31 to P36 has a duration twice the time interval T31. The clock signal CLKIN has rising edges R31 to R36 corresponding to periods P31 to P36 respectively. The clock signal CLKIN is pulled to voltage level VH at each of the rising edges R31 to R36, and is pulled from voltage level VH to voltage level VL during each of periods P31 to P36.

[0049] Please refer to Figure 1 and Figure 3 ,exist Figure 3In the illustrated embodiment, the delay phase-locked loop device 100 delays the clock signal CLKIN by three clock cycles (for example, during periods P31 to P33) to generate the output signal SOUT2. In other words, the waveform of the output signal SOUT2 is similar to that of the clock signal CLKIN, but the waveform of the signal SOUT2 is delayed by a delay time DT of three clock cycles. Correspondingly, the first rising edge R37 of the output signal SOUT2 corresponds to the first rising edge R31 of the clock signal CLKIN, and the rising edge R37 is aligned with the fourth rising edge R34 of the clock signal CLKIN.

[0050] Please refer to Figure 2 and Figure 3 When the voltage VDD changes, the rising edge R37 may not align with the rising edge R34. For example, when the voltage level of VDD increases, the delay time DT decreases, the waveform of the output signal SOUT2 is shifted to the left, and the rising edge R37 is to the left of the rising edge R34. When the voltage level of VDD decreases, the delay time DT increases, the waveform of the output signal SOUT2 is shifted to the right, and the rising edge R37 is to the right of the rising edge R34.

[0051] Please refer to Figure 1 and Figure 3 When the rising edge R37 is not aligned with the rising edge R34, the controller 150 adjusts the output signal SOUT2 to align the rising edge R37 with the rising edge R34.

[0052] For example, in operation OP1, when the rising edge R37 is to the left of the rising edge R34, the controller 150 generates bit B5 with a logic value of 1, indicating that the delay time DT of the output signal SOUT2 should be increased. Correspondingly, the controller 150 increases the number of buffers IN(1) to IN(n) used to delay the clock signal CLKIN, causing the output signal SOUT2 to be shifted to the right until the rising edge R37 aligns with the rising edge R34. Similarly, when the rising edge R37 is to the right of the rising edge R34, the controller 150 generates bit B5 with a logic value of 0, indicating that the delay time DT of the output signal SOUT2 should be decreased. Correspondingly, the controller 150 decreases the number of buffers IN(1) to IN(n) used to delay the clock signal CLKIN, causing the output signal SOUT2 to be shifted to the left until the rising edge R37 aligns with the rising edge R34.

[0053] Please refer to Figure 1 and Figure 3The controller 150 is also used to adjust the time interval for adjusting the delay time DT based on bit A1. In some embodiments, the controller 150 adjusts the time interval for adjusting the delay time DT by adjusting the number of buffers IN(1) to IN(n).

[0054] In some embodiments, in response to the rising edge R37 being offset from the rising edge R34 by a larger time interval, the controller 150 adjusts the delay time DT by a larger time interval. In response to the rising edge R37 being offset from the rising edge R34 by a smaller time interval, the controller 150 adjusts the delay time DT by a smaller time interval.

[0055] For example, in operation OP2, in response to a time interval in which the rising edge R37 is offset from the rising edge R34 by a time interval greater than or equal to three-quarters of a time interval T31, the controller 150 generates bit A1 with a logic value of 1, indicating that the delay time DT of the output signal SOUT2 should be adjusted by a time interval T31. Correspondingly, the controller 150 adjusts the number of buffers IN(1) to IN(n) by the corresponding number of time intervals T31 (for example, increasing or decreasing the number of buffers IN(1) to IN(n) by ten buffers), so that the rising edge R37 moves towards the rising edge R34 by a time interval T31. Similarly, in response to a time interval in which the rising edge R37 is offset from the rising edge R34 by a time interval less than three-quarters of a time interval T31, the controller 150 generates bit A1 with a logic value of 0, indicating that the delay time DT of the output signal SOUT2 should be adjusted by a time interval T31. Correspondingly, the controller 150 adjusts the number of buffers IN(1) to IN(n) by a number corresponding to one-tenth of a time interval T31 (for example, by increasing or decreasing the number of buffers IN(1) to IN(n) by one buffer), so that the rising edge R37 moves toward the rising edge R34 by one-tenth of a time interval T31.

[0056] In some prior art, in response to a time interval greater than half a clock cycle in which the output signal of the delay-locked loop (DLL) is offset, the DLL may adjust the rising edge of the output signal to an incorrect rising edge of the clock signal. In these approaches, the amount of time interval used to adjust the delay time of the output signal cannot be adjusted.

[0057] Compared to the above approach, in some embodiments of this disclosure, the controller 150 adjusts the rising edge R37 of the output signal SOUT2 to the corresponding rising edge R34 based on bit B5, and adjusts the time interval used to adjust the delay time DT of the output signal SOUT2 based on bit A1. Details of bits B5 and A1 are further explained below.

[0058] Figure 4 This is a schematic diagram illustrating a controller 400 according to some embodiments of the present invention. The controller 400 is... Figure 1 One embodiment of the controller 150 is shown. In some embodiments, the controller 400 is used to receive the output signal SOUT2 and generate signals D1 to D4 based on the output signal SOUT2.

[0059] like Figure 4 As shown, controller 400 includes delay lines DL41 to DL44. Delay line DL41 delays the output signal SOUT2 by a quarter time interval T31 to generate signal D1. Delay line DL42 delays signal D1 by a quarter time interval T31 to generate signal D2. Delay line DL43 delays signal D2 by a quarter time interval T31 to generate signal D3. Delay line DL44 delays signal D3 by a quarter time interval T31 to generate signal D4. In various embodiments, controller 400 may include N delay lines, each of the N delay lines being able to receive a signal delayed by a fraction of N time interval T31 by the preceding delay line, where N is a positive integer greater than four.

[0060] Figure 5 This is a schematic diagram illustrating a controller 500 according to some embodiments of the present invention. The controller 500 is... Figure 1 The controller 150 shown is one embodiment. In some embodiments, the controller 500 is used to receive clock signal CLK1 and signals D1-D4, and generate bits B1-B4 based on clock signal CLK1 and signals D1-D4. Please refer to... Figure 1 and Figure 5 The controller 500 is used to control the delay line 106 based on bits B1 to B4. In some embodiments, the controller 500 includes... Figure 4 The delay lines shown are DL41 to DL44.

[0061] like Figure 5As shown, the controller 500 includes a delay line DLC5 and flip-flop circuits FF51 to FF54. The delay line DLC5 delays the clock signal CLK1 by an eighth of a time interval T31 to generate the clock signal CLK2. In various embodiments, the delay line DLC5 can delay the clock signal CLK1 by a time interval smaller than the time interval by which the delay line DL41 delays the output signal SOUT2. In some embodiments, the delay line DLC5 can delay the clock signal CLK1 by approximately half the time interval by which the delay line DL41 delays the output signal SOUT2. For example, in some embodiments, the delay line DLC5 delays the clock signal CLK1 by a two-seventeenth of a time interval T31 to generate the clock signal CLK2.

[0062] like Figure 5 As shown, flip-flop circuit FF51 generates bit B1 based on clock signal CLK2 and signal D1. Flip-flop circuit FF52 generates bit B2 based on clock signal CLK2 and signal D2. Flip-flop circuit FF53 generates bit B3 based on clock signal CLK2 and signal D3. Flip-flop circuit FF54 generates bit B4 based on clock signal CLK2 and signal D4. In some embodiments, flip-flop circuits FF51 to FF54 are triggered by the rising edge of clock signal CLK2.

[0063] Figure 6 Timing diagram 600 for signals relating to delay phase-locked loop device 100 and controllers 400 and 500 according to some embodiments of the present invention.

[0064] like Figure 6 As shown, clock signal CLK1 includes a rising edge R61. Clock signal CLK2 has a waveform similar to clock signal CLK1, but the waveform of clock signal CLK2 is delayed by one-eighth of a time interval T31. Clock signal CLK2 includes a rising edge R62 corresponding to rising edge R61. The rising edge R62 of clock signal CLK2 is shown in timing diagram 600; for simplicity, other parts of clock signal CLK2 are omitted in timing diagram 600.

[0065] like Figure 6 As shown, the output signal SOUT2 includes a rising edge R63. Please refer to... Figure 3 and Figure 6 Rising edges R61 and R63 correspond to rising edges R34 and R37, respectively.

[0066] exist Figure 6 In the illustrated embodiment, the output signal SOUT2 is offset by a time interval less than a quarter of a time interval T31. The rising edge R63 is considered to be aligned with the rising edge R61.

[0067] Please refer to Figure 5 and Figure 6 The flip-flop circuits FF51-FF54 are triggered by the rising edge R62 and are used to generate bits B1-B4 based on the voltage levels of signals D1-D4 at the rising edge R62. In some embodiments, voltage level VH corresponds to logic value 1, and voltage level VL corresponds to logic value 0. For example... Figure 6 As shown, each of signals D1 to D4 has a voltage level VL at the rising edge R62. Correspondingly, the logic values ​​of bits B1 to B4 are 0, 0, 0, and 0, respectively.

[0068] Figure 7A Timing diagram 700A for signals relating to delay phase-locked loop device 100 and controllers 400 and 500 according to some embodiments of the present invention.

[0069] like Figure 7A As shown, clock signal CLK1 includes a rising edge R71. Clock signal CLK2 has a waveform similar to clock signal CLK1, but the waveform of clock signal CLK2 is delayed by one-eighth of a time interval T31. Clock signal CLK2 includes a rising edge R72 corresponding to rising edge R71. Output signal SOUT2 has a waveform similar to clock signal CLK1, but the waveform of output signal SOUT2 is delayed by one-quarter of a time interval T31. Output signal SOUT2 includes a rising edge RA7 corresponding to rising edge R71. The rising edge R72 of clock signal CLK2 and the rising edge RA7 of output signal SOUT2 are shown in timing diagram 700A. For simplicity, other parts of clock signal CLK2 and output signal SOUT2 are omitted in timing diagram 700A. Please refer to... Figure 3 and Figure 7A Rising edges R71 and RA7 correspond to rising edges R34 and R37, respectively.

[0070] exist Figure 7A In the illustrated embodiment, the output signal SOUT2 is delayed by approximately a quarter time interval T31. The rising edge RA7 is located to the right of the rising edge R71 and is a quarter time interval T31 away from the rising edge R71.

[0071] Please refer to Figure 5 and Figure 7A The flip-flop circuits FF51 to FF54 are triggered by the rising edge R72 and are used to generate bits B1 to B4 based on the voltage levels of signals D1 to D4 at the rising edge R72. Figure 7AAs shown, signals D1 to D4 have voltage levels VL, VL, VL, and VH at the rising edge R72, respectively. Correspondingly, the logic values ​​of bits B1 to B4 are 0, 0, 0, and 1, respectively.

[0072] Figures 7B to 7H Timing diagrams 700B to 700H are illustrated for signals relating to the delay phase-locked loop device 100 and controllers 400 and 500 according to some embodiments of the present invention. Each of timing diagrams 700B to 700H is similar to Figure 7A For the sake of simplicity, some details will not be repeated in the timing diagram 700A shown.

[0073] like Figure 7B As shown, the output signal SOUT2 includes the rising edge RB7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7B Rising edges R71 and RB7 correspond to rising edges R34 and R37, respectively.

[0074] exist Figure 7B In the illustrated embodiment, the output signal SOUT2 is delayed by approximately half a time interval T31. The rising edge RB7 is located to the right of the rising edge R71 and is located half a time interval T31 away from the rising edge R71.

[0075] like Figure 7B As shown, signals D1 to D4 have voltage levels VL, VL, VH, and VH at the rising edge R72, respectively. Correspondingly, the logic values ​​of bits B1 to B4 are 0, 0, 1, and 1, respectively.

[0076] like Figure 7C As shown, the output signal SOUT2 includes the rising edge RC7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7C Rising edges R71 and RC7 correspond to rising edges R34 and R37, respectively.

[0077] exist Figure 7C In the illustrated embodiment, the output signal SOUT2 is delayed by approximately three-quarters of a time interval T31. The rising edge RC7 is located to the right of the rising edge R71 and is three-quarters of a time interval T31 away from the rising edge R71.

[0078] like Figure 7C As shown, signals D1 to D4 have voltage levels VL, VH, VH, and VH respectively at the rising edge R72. Correspondingly, the logic values ​​of bits B1 to B4 are 0, 1, 1, and 1, respectively.

[0079] like Figure 7DAs shown, the output signal SOUT2 includes the rising edge RD7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7D Rising edges R71 and RD7 correspond to rising edges R34 and R37, respectively.

[0080] exist Figure 7D In the illustrated embodiment, the output signal SOUT2 is delayed by approximately one time interval T31. The rising edge RD7 is located to the right of the rising edge R71 and is separated from the rising edge R71 by one time interval T31.

[0081] like Figure 7D As shown, signals D1 to D4 have voltage levels VH, VH, VH, and VH respectively at the rising edge R72. Correspondingly, the logic values ​​of bits B1 to B4 are 1, 1, 1, and 1, respectively.

[0082] like Figure 7E As shown, the output signal SOUT2 includes the rising edge RE7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7E Rising edges R71 and RE7 correspond to rising edges R34 and R37, respectively.

[0083] exist Figure 7E In the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately a quarter time interval T31. The rising edge RE7 is located to the left of the rising edge R71 and is a quarter time interval T31 away from the rising edge R71.

[0084] like Figure 7E As shown, signals D1 to D4 have voltage levels VH, VL, VL, and VL respectively at the rising edge R72. Correspondingly, the logic values ​​of bits B1 to B4 are 1, 0, 0, and 0, respectively.

[0085] like Figure 7F As shown, the output signal SOUT2 includes the rising edge RF7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7F Rising edges R71 and RF7 correspond to rising edges R34 and R37, respectively.

[0086] exist Figure 7F In the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately half a time interval T31. The rising edge RF7 is located to the left of the rising edge R71 and is half a time interval T31 away from the rising edge R71.

[0087] like Figure 7FAs shown, signals D1 to D4 have voltage levels VH, VH, VL, and VL respectively at the rising edge R72. Correspondingly, the logic values ​​of bits B1 to B4 are 1, 1, 0, and 0, respectively.

[0088] like Figure 7G As shown, the output signal SOUT2 includes the rising edge RG7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7G Rising edges R71 and RG7 correspond to rising edges R34 and R37, respectively.

[0089] exist Figure 7G In the illustrated embodiment, the output signal SOUT2 is advanced by approximately three-quarters of a time interval T31. The rising edge RG7 is located to the left of the rising edge R71 and is three-quarters of a time interval T31 away from the rising edge R71.

[0090] like Figure 7G As shown, signals D1 to D4 have voltage levels VH, VH, VH, and VL at the rising edge R72, respectively. Correspondingly, the logic values ​​of bits B1 to B4 are 1, 1, 1, and 0, respectively.

[0091] like Figure 7H As shown, the output signal SOUT2 includes the rising edge RH7 corresponding to the rising edge R71. Please refer to... Figure 3 and Figure 7H Rising edges R71 and RH7 correspond to rising edges R34 and R37, respectively.

[0092] exist Figure 7H In the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately one time interval T31. The rising edge RH7 is located to the left of the rising edge R71 and is a time interval T31 away from the rising edge R71.

[0093] like Figure 7H As shown, signals D1 to D4 have voltage levels VH, VH, VH, and VH respectively at the rising edge R72. Correspondingly, the logic values ​​of bits B1 to B4 are 1, 1, 1, and 1, respectively.

[0094] Figure 7I This is a truth table of bits B1 to B4 illustrating the delay and forward shift of the corresponding output signal SOUT2 according to some embodiments of the present invention. Figure 7I As shown, some combinations of the logical values ​​of bits B1 to B4 will not occur. For example, in Figures 7A to 7H In this embodiment, bits B1 to B4 do not have a combination of logic values ​​0, 0, 1, 0. Figure 7I The truth table shown corresponds to eight states of the output signal SOUT2.

[0095] This disclosure is not limited to the embodiments described above. Various numbers of delay lines, signals delayed by the delay lines, corresponding bits, and various time intervals used to delay the clock signal CLK1 are all within the scope of this disclosure. For example, in some other embodiments, the controller 150 may include eight delay lines for generating eight signals, eight flip-flop circuits for generating eight bits corresponding to the eight signals, and delay lines for delaying the clock signal CLK1 by a sixteenth of a time interval T31.

[0096] Figure 8 This is a schematic diagram illustrating a controller 800 according to some embodiments of the present invention. The controller 800 is... Figure 1 The controller 150 shown is one embodiment, and is Figure 5 The controller 500 shown is a variation. In some embodiments, the controller 800 receives clock signal CLK1 and signals D1-D4, and generates bits B5 and B2-B4 based on clock signal CLK1 and signals D1-D4. Please refer to... Figure 1 and Figure 8 The controller 800 controls the delay line 106 based on bits B5 and B2-B4. In some embodiments, the controller 800 includes... Figure 4 The delay lines shown are DL41 to DL44.

[0097] like Figure 8 As shown, the controller 800 includes a delay line DLC8, a frequency divider FD8, and flip-flop circuits FF81 to FF84. In some embodiments, the frequency divider FD8 is implemented as a T-type flip-flop circuit. The delay line DLC8 corresponds to... Figure 5 The delay line DLC5 shown is used to delay the clock signal CLK1 by an eighth of a time interval T31 to generate the clock signal CLK2. The frequency divider FD8 is used to divide the frequency of the signal D1 to generate a signal D1P with a frequency lower than that of the signal D1.

[0098] For example, please refer to Figure 8 , Figure 9A and Figure 7D The frequency divider FD8 receives signal D1 and converts it into signal D1P, which has half the frequency of signal D1, with the rising edge RA92 of signal D1P and the rising edge RD72 of signal D1 occurring at the same time. In some embodiments, the frequency of signal D1P is less than or equal to half the frequency of signal D1.

[0099] like Figure 8As shown, flip-flop circuit FF81 generates bit B5 based on clock signal CLK2 and signal D1P. Flip-flop circuit FF82 generates bit B2 based on clock signal CLK2 and signal D2. Flip-flop circuit FF83 generates bit B3 based on clock signal CLK2 and signal D3. Flip-flop circuit FF84 generates bit B4 based on clock signal CLK2 and signal D4. In some embodiments, flip-flop circuits FF81 to FF84 are triggered by the rising edge of clock signal CLK2.

[0100] Figure 9A Timing diagram 900A for signals relating to delay phase-locked loop device 100 and controllers 500 and 800 according to some embodiments of the present invention.

[0101] like Figure 9A As shown, clock signal CLK1 includes a rising edge R91. Clock signal CLK2 has a waveform similar to clock signal CLK1, but the waveform of clock signal CLK2 is delayed by one-eighth of a time interval T31. Clock signal CLK2 includes a rising edge R92 corresponding to rising edge R91. Output signal SOUT2 has a waveform similar to clock signal CLK1, but the waveform of output signal SOUT2 is delayed by one time interval T31. Output signal SOUT2 includes a rising edge RA9 corresponding to rising edge R91. The rising edge R92 of clock signal CLK2 and the rising edge RA9 of output signal SOUT2 are shown in timing diagram 900A. For simplicity, other parts of clock signal CLK2 and output signal SOUT2 are omitted in timing diagram 900A. Please refer to... Figure 3 and Figure 6 Rising edges R91 and RA9 correspond to rising edges R34 and R37, respectively.

[0102] exist Figure 9A In the illustrated embodiment, the output signal SOUT2 is delayed by approximately one time interval T31. The rising edge RA9 is located to the right of the rising edge R91 and is separated from the rising edge R91 by one time interval T31.

[0103] Please refer to Figure 8 and Figure 9A The flip-flop circuits FF81-FF84 are triggered by the rising edge R92 and are used to generate bits B5 and B2-B4 based on the voltage levels of signals D1P and D2-D4 at the rising edge R92. For example... Figure 9A As shown, signals D1P, D2, D3, and D4 have voltage levels VL, VH, VH, and VH at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 1, 1, and 1, respectively.

[0104] Figures 9B to 9N Timing diagrams 900B to 900N are illustrated for signals relating to the delay phase-locked loop device 100 and controllers 500 and 800 according to some embodiments of the present invention. Each of timing diagrams 900B to 900N is similar to Figure 9A For the sake of simplicity, some details will not be repeated in the timing diagram 900A shown.

[0105] like Figure 9B As shown, the output signal SOUT2 includes the rising edge RB9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9B Rising edges R91 and RB9 correspond to rising edges R34 and R37, respectively.

[0106] exist Figure 9B In the illustrated embodiment, the output signal SOUT2 is delayed by approximately one and a quarter time intervals T31. The rising edge RB9 is located to the right of the rising edge R91 and is at a distance of one and a quarter time intervals T31 from the rising edge R91.

[0107] like Figure 9B As shown, signals D1P, D2, D3, and D4 have voltage levels VL, VH, VH, and VL respectively at the rising edge R92. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 1, 1, and 0, respectively.

[0108] like Figure 9C As shown, the output signal SOUT2 includes the rising edge RC9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9C Rising edges R91 and RC9 correspond to rising edges R34 and R37, respectively.

[0109] exist Figure 9C In the illustrated embodiment, the output signal SOUT2 is delayed by approximately one and a half time intervals T31. The rising edge RC9 is located to the right of the rising edge R91 and is a distance of one and a half time intervals T31 from the rising edge R91.

[0110] like Figure 9C As shown, signals D1P, D2, D3, and D4 have voltage levels VL, VH, VL, and VL respectively at the rising edge R92. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 1, 0, and 0, respectively.

[0111] like Figure 9D As shown, the output signal SOUT2 includes the rising edge RD9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9DRising edges R91 and RD9 correspond to rising edges R34 and R37, respectively.

[0112] exist Figure 9D In the illustrated embodiment, the output signal SOUT2 is delayed by approximately three-quarters of a time interval T31. The rising edge RD9 is located to the right of the rising edge R91 and is located three-quarters of a time interval T31 away from the rising edge R91.

[0113] like Figure 9D As shown, signals D1P, D2, D3, and D4 have voltage levels VL, VH, VH, and VH at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 1, 1, and 1, respectively.

[0114] like Figure 9E As shown, the output signal SOUT2 includes the rising edge RE9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9E Rising edges R91 and RE9 correspond to rising edges R34 and R37, respectively.

[0115] exist Figure 9E In the illustrated embodiment, the output signal SOUT2 is delayed by approximately half a time interval T31. The rising edge RE9 is located to the right of the rising edge R91 and is located half a time interval T31 away from the rising edge R91.

[0116] like Figure 9E As shown, signals D1P, D2, D3, and D4 have voltage levels VL, VL, VH, and VH at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 0, 1, and 1, respectively.

[0117] like Figure 9F As shown, the output signal SOUT2 includes the rising edge RF9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9F Rising edges R91 and RF9 correspond to rising edges R34 and R37, respectively.

[0118] exist Figure 9F In the illustrated embodiment, the output signal SOUT2 is delayed by approximately a quarter time interval T31. The rising edge RF9 is located to the right of the rising edge R91 and is a quarter time interval T31 away from the rising edge R91.

[0119] like Figure 9FAs shown, signals D1P, D2, D3, and D4 have voltage levels VL, VL, VL, and VH at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 0, 0, and 1, respectively.

[0120] like Figure 9G As shown, the output signal SOUT2 includes the rising edge RG9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9G Rising edges R91 and RG9 correspond to rising edges R34 and R37, respectively.

[0121] exist Figure 9G In the illustrated embodiment, the output signal SOUT2 is either not delayed or advanced, or it is delayed or advanced by a time interval less than a quarter of a time interval T31. The rising edge RG9 is considered to be aligned with the rising edge R91.

[0122] like Figure 9G As shown, signals D1P, D2, D3, and D4 have voltage levels VL, VL, VL, and VL respectively at the rising edge R92. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 0, 0, 0, and 0, respectively.

[0123] like Figure 9H As shown, the output signal SOUT2 includes the rising edge RH9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9H Rising edges R91 and RH9 correspond to rising edges R34 and R37, respectively.

[0124] exist Figure 9H In the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately a quarter time interval T31. The rising edge RH9 is located to the left of the rising edge R91 and is a quarter time interval T31 away from the rising edge R91.

[0125] like Figure 9H As shown, signals D1P, D2, D3, and D4 have voltage levels VH, VL, VL, and VL at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 0, 0, and 0, respectively.

[0126] like Figure 9I As shown, the output signal SOUT2 includes the rising edge RI9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9I Rising edges R91 and RI9 correspond to rising edges R34 and R37, respectively.

[0127] exist Figure 9IIn the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately half a time interval T31. The rising edge RI9 is ​​located to the left of the rising edge R91 and is half a time interval T31 away from the rising edge R91.

[0128] like Figure 9I As shown, signals D1P, D2, D3, and D4 have voltage levels VH, VH, VL, and VL at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 1, 0, and 0, respectively.

[0129] like Figure 9J As shown, the output signal SOUT2 includes the rising edge RJ9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9J Rising edges R91 and RJ9 correspond to rising edges R34 and R37, respectively.

[0130] exist Figure 9J In the illustrated embodiment, the output signal SOUT2 is advanced by approximately three-quarters of a time interval T31. The rising edge RJ9 is located to the left of the rising edge R91 and is three-quarters of a time interval T31 away from the rising edge R91.

[0131] like Figure 9J As shown, signals D1P, D2, D3, and D4 have voltage levels VH, VH, VH, and VL at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 1, 1, and 0, respectively.

[0132] like Figure 9K As shown, the output signal SOUT2 includes the rising edge RK9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9K Rising edges R91 and RK9 correspond to rising edges R34 and R37, respectively.

[0133] exist Figure 9K In the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately one time interval T31. The rising edge RK9 is located to the left of the rising edge R91 and is a time interval T31 away from the rising edge R91.

[0134] like Figure 9K As shown, signals D1P, D2, D3, and D4 have voltage levels VH, VH, VH, and VH respectively at the rising edge R92. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 1, 1, and 1, respectively.

[0135] like Figure 9LAs shown, the output signal SOUT2 includes the rising edge RL9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9L Rising edges R91 and RL9 correspond to rising edges R34 and R37, respectively.

[0136] exist Figure 9L In the illustrated embodiment, the output signal SOUT2 is forwarded by approximately one and a quarter time intervals T31. The rising edge RL9 is located to the left of the rising edge R91 and is at a distance of one and a quarter time intervals T31 from the rising edge R91.

[0137] like Figure 9L As shown, signals D1P, D2, D3, and D4 have voltage levels VH, VH, VH, and VH respectively at the rising edge R92. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 1, 1, and 1, respectively.

[0138] like Figure 9M As shown, the output signal SOUT2 includes the rising edge RM9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9M Rising edges R91 and RM9 correspond to rising edges R34 and R37, respectively.

[0139] exist Figure 9M In the illustrated embodiment, the output signal SOUT2 is advanced by approximately one and a half time intervals T31. The rising edge RM9 is located to the left of the rising edge R91 and is a distance of one and a half time intervals T31 from the rising edge R91.

[0140] like Figure 9M As shown, signals D1P, D2, D3, and D4 have voltage levels VH, VL, VH, and VH respectively at the rising edge R92. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 0, 1, and 1, respectively.

[0141] like Figure 9N As shown, the output signal SOUT2 includes the rising edge RN9 corresponding to the rising edge R91. Please refer to... Figure 3 and Figure 9N Rising edges R91 and RN9 correspond to rising edges R34 and R37, respectively.

[0142] exist Figure 9N In the illustrated embodiment, the output signal SOUT2 is shifted forward by approximately one and three-quarters of a time interval T31. The rising edge RN9 is located to the left of the rising edge R91 and is a distance of one and three-quarters of a time interval T31 from the rising edge R91.

[0143] like Figure 9NAs shown, signals D1P, D2, D3, and D4 have voltage levels VH, VL, VL, and VH at the rising edge R92, respectively. Correspondingly, the logic values ​​of bits B5, B2, B3, and B4 are 1, 0, 0, and 1, respectively.

[0144] Figure 10 This is a schematic diagram illustrating a logic circuit 1000 according to some embodiments of the present invention. In some embodiments, the logic circuit 1000 includes... Figure 1 and Figure 8 At least one of the controllers 150 and 800 shown is used to generate bit A1 based on the logic values ​​of signals D1P and D2 to D4. In some embodiments, the logic values ​​of signals D1P, D2, D3 and D4 correspond to bits B5, B2, B3 and B4, respectively.

[0145] like Figure 10 As shown, logic circuit 1000 includes inverters INV1 and INV2, AND gates AND1 to AND3, and OR gate OR1. The first input of AND gate AND1 receives signal D3, and the second input of AND gate AND1 is coupled to the output of inverter INV1. The input of inverter INV1 receives signal D4. The first input of AND gate AND2 receives signal D2, and the second input of AND gate AND2 is coupled to the output of inverter INV2. The input of inverter INV2 receives signal D1P. The first input of AND gate AND3 receives signal D1P, and the second input of AND gate AND3 receives signal D4. Multiple inputs of OR gate OR1 are coupled to the outputs of AND gates AND1 to AND3. The output of OR gate OR1 outputs bit A1. In binary representation, bit A1 equals...

[0146] This disclosure is not limited to the embodiments described above. Various logic combinations included in the logic circuit 1000 for generating bits different from bit A1 are also within the scope of this disclosure.

[0147] Figure 11 This is a truth table of bits B2-B5 and A1 illustrating the delay and forward shift of the corresponding output signal SOUT2 according to some embodiments of the present invention. Figure 11 As shown, some combinations of logic values ​​for bits B2 to B5 will not occur. For example, in Figures 9A to 9N In the embodiment, bits B5, B2, B3, and B4 do not have a combination of logic values ​​0, 0, 1, and 0. Figure 11 The truth table shown corresponds to twelve states of the output signal SOUT2.

[0148] Please refer to Figure 1and Figure 11 In operation OP1, in response to the output signal SOUT2 being delayed, bit B5 has a logic value of 0 indicating that the output signal SOUT2 is delayed. Correspondingly, controller 150 reduces the number of buffers in delay line 106 to reduce the delay time of output signal SOUT2. Similarly, in response to the output signal SOUT2 being shifted forward, bit B5 has a logic value of 1 indicating that the output signal SOUT2 is shifted forward. Correspondingly, controller 150 increases the number of buffers in delay line 106 to increase the delay time of output signal SOUT2.

[0149] Please refer to Figure 1 and Figure 11 In operation OP2, in response to the output signal SOUT2 being offset by a time interval greater than or equal to a first time interval (for example, the first time interval could be three-quarters of a time interval T31), bit A1 has a logic value of 1. Correspondingly, controller 150 adjusts the number of buffers in delay line 106 by a first amount, such as ten, to adjust the delay time of output signal SOUT2 to a second time interval, such as time interval T31. Similarly, in response to the output signal SOUT2 being offset by a time interval less than the first time interval, bit A1 has a logic value of 0. Correspondingly, controller 150 adjusts the number of buffers in delay line 106 by a second amount, such as one, to adjust the delay time of output signal SOUT2 to a third time interval, such as one-tenth of a time interval T31. In some embodiments, the second time interval is greater than the third time interval.

[0150] This disclosure is not limited to the above embodiments. Various time lengths of the first time interval, the second time interval, and the third time interval, as well as various quantities of the first and second quantities of buffers, are all within the scope of this disclosure.

[0151] In summary, in the embodiments disclosed herein, when the output signal SOUT2 is offset, the controller 150 adjusts the delay time DT of the output signal SOUT2 according to bits B5 and A1 corresponding to various cases of the output signal SOUT2 being offset.

[0152] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0153] [Symbol Explanation]

[0154] 100: Delayed Phase-Locked Loop Device

[0155] CLKIN, CLK1: Clock signals

[0156] SOUT1, SOUT2: Output signals

[0157] SC: Control Signal

[0158] 114: Gasket

[0159] 102: Receiver

[0160] 104: Instruction Decoder

[0161] 106, 200, DL41~DL44, DLC5, DLC8: Delay lines

[0162] 108: Amplifier

[0163] 110: Clock Tree

[0164] 112: Output current driver

[0165] 150, 400, 500: Controller

[0166] VRF: Reference Voltage

[0167] S1~S5, ZIN, ZOUT, D1~D4, D1P: Signals

[0168] OP1, OP2: Operation

[0169] IN(1)~IN(n): Buffer

[0170] VDD: Voltage

[0171] GND: Grounding voltage

[0172] 300, 600, 700A~700H, 900A~900N: Timing Diagram

[0173] P31~P36: Period

[0174] T31: Time Interval

[0175] rising edge

[0176] VH, VL: Voltage levels

[0177] DT: Delay Time

[0178] B1~B5, A1: Bits

[0179] FF51~FF54, FF81~FF84: Flip-Flip Circuits

[0180] FD8: Frequency divider

[0181] 1000: Logic Circuits

[0182] INV1, INV2: Inverters

[0183] AND1~AND3: AND gate

[0184] OR1: OR gate.

Claims

1. A delay method, characterized in that, include: The delay line delays the first clock signal by a delay time to generate the output signal; The controller delays the output signal by a first time interval to generate the first signal; The controller delays the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal; The controller controls the delay line to adjust the delay time based on the first signal and the second clock signal; and A second signal is generated based on the first signal, wherein the frequency of the second signal is equal to or less than half the frequency of the first signal, and the edge of the second signal and the edge of the first signal are at the same time.

2. The delay method according to claim 1, wherein adjusting the delay time includes: The delay time is adjusted based on the voltage level of the second signal at the edge of the second clock signal.

3. The delay method according to claim 2, wherein adjusting the delay time includes: In response that the voltage level is the first voltage level, the delay time is increased; as well as In response to the voltage level being a second voltage level different from the first voltage level, the delay time is reduced.

4. The delay method according to claim 2, wherein the time interval between the edge of the second clock signal and the edge of the first clock signal is substantially equal to the second time interval, and Adjusting the delay time also includes adjusting the delay time until the edge of the output signal aligns with the edge of the first clock signal.

5. The delay method according to claim 4, further comprising: The first signal is delayed by the first time interval to generate the third signal; A bit is generated based on the voltage level of the second signal at that moment and the voltage level of the third signal at that moment, wherein the bit indicates the time interval between the edge of the output signal and the edge of the first clock signal; and Adjust the delay time based on this bit.

6. The delay method according to claim 1, further comprising: In response to the bit corresponding to the second signal having a first logic value, the delay time is increased; as well as In response to the bit corresponding to the second signal having a second logic value different from the first logic value, the delay time is reduced.

7. The delay method according to claim 1, wherein adjusting the delay time includes: In response to a third time interval between the edge of the output signal and the edge of the first clock signal being greater than or equal to a fourth time interval, a bit with a first logic value is generated. In response to the third time interval being less than the fourth time interval, the bit is generated having a second logic value different from the first logic value; In response that the bit has the first logical value, the delay time is adjusted by the fifth time interval; as well as In response to the bit having the second logic value, the delay time is adjusted to a sixth time interval that is different from the fifth time interval.

8. The delay method according to claim 7, wherein The duration of this fourth time interval is approximately three-eighths of the clock cycle of the first clock signal, and The fifth time interval is greater than the sixth time interval.

9. A delay-locked loop device, characterized in that, include: The first delay line is used to delay the first clock signal by a delay time to generate an output signal; as well as A controller for controlling the first delay line based on a complex number of bits to adjust the delay time, and the controller includes: The second delay line is used to generate a second clock signal based on the first clock signal; A frequency divider is used to generate a first signal based on the output signal, wherein the frequency of the first signal is less than the frequency of the output signal; and A plurality of flip-flop circuits are used to generate the bits based on the first signal and the second clock signal.

10. The delay-locked loop device of claim 9, wherein the controller further comprises a plurality of delay lines for delaying the output signal to generate a second signal, and The frequency divider is also used to generate the first signal based on the second signal, wherein the frequency of the first signal is less than or equal to half the frequency of the second signal.

11. The delay phase-locked loop apparatus of claim 10, wherein the delay lines comprise: The third delay line is used to delay the second signal by a first time interval to generate the third signal; The fourth delay line is used to delay the third signal by the first time interval to generate the fourth signal; as well as The fifth delay line is used to delay the fourth signal by the first time interval to generate the fifth signal, wherein... The duration of the first time interval is essentially equivalent to one-eighth of the clock cycle of the first clock signal.

12. The delay-locked loop device according to claim 9, wherein the controller comprises: The third delay line is used to delay the output signal by a first time interval to generate the second signal. The frequency divider is also used to receive the second signal and generate the first signal based on the second signal, and The second delay line is also used to delay the first clock signal by a second time interval to generate the second clock signal, wherein the second time interval is shorter than the first time interval.

13. The delay phase-locked loop apparatus of claim 12, wherein a first flip-flop circuit of the flip-flop circuits is triggered by an edge of the second clock signal to generate the first bit of the bits based on the voltage level of the first signal at the moment of the edge of the second clock signal.

14. The delay phase-locked loop device of claim 13, wherein the controller is further configured to increase the delay time in response to the first bit having a first logic value, and to decrease the delay time in response to the first bit having a second logic value different from the first logic value.

15. The delay-locked loop device according to claim 13, wherein the controller further comprises: A logic circuit is used to perform multiple logic operations based on these bits to generate a second bit, which indicates the time interval at which the output signal is offset. The controller is also used to adjust the delay time based on the second bit.

16. The delay-locked loop device according to claim 15, wherein... The first delay line includes multiple buffers for delaying the first clock signal to generate the output signal. The controller is also configured to adjust the number of buffers by a first amount in response to the second bit having a first logic value, and The controller is also configured to adjust the number of the buffers by a second number different from the first number in response to the second bit having a second logic value different from the first logic value.

17. A delay method, characterized in that, include: The delay line delays the first clock signal by a delay time to generate the output signal; The controller delays the output signal by a first time interval to generate the first signal; The controller delays the first clock signal by a second time interval that is approximately half of the first time interval to generate a second clock signal; The controller generates a second signal based on the first signal, wherein the frequency of the second signal is less than or equal to the frequency of the first signal, and the edge of the second signal is at the same time as the edge of the first signal; The controller delays the first signal by the first time interval to generate a third signal; as well as The controller controls the delay line based on the voltage level of the second signal at the edge of the second clock signal and the voltage level of the third signal at the edge of the second clock signal at that time, so as to adjust the delay time.

18. The delay method of claim 17, wherein adjusting the delay time comprises: The voltage level in response to the second signal is the first voltage level, and the delay time is increased; as well as The voltage level responding to the second signal is a second voltage level that is different from the first voltage level, thereby reducing the delay time.

19. The delay method of claim 17, wherein adjusting the delay time comprises: A first element is generated based on the voltage level of the second signal and the voltage level of the third signal, wherein the first element indicates whether the third time interval between the edge of the output signal and the edge of the first clock signal is less than the fourth time interval. In response to the third time interval being less than the fourth time interval, the delay time is adjusted to a fifth time interval; as well as In response to the third time interval being greater than or equal to the fourth time interval, the delay time is adjusted to a sixth time interval that is greater than the fifth time interval.

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