Method for manufacturing a memory device

Abstract

The application discloses a manufacturing method of a memory device, comprising the following steps: providing a substrate, the substrate comprises a first region and a second region, the first region is used for integrating the memory device, the second region is a peripheral region, a stack is formed on the substrate, the stack comprises, from bottom to top, an oxide layer, a first polysilicon layer, a first isolation layer, a second polysilicon layer and a hard mask layer, a via is formed in the stack of the first region, and a second isolation layer is formed on the side of the via; forming a third polysilicon layer on the stack, the third polysilicon layer fills the via; etching, removing the third polysilicon layer outside the via, and the height of the third polysilicon layer in the via is lower than the height of the hard mask layer; forming a buffer layer on the stack and the third polysilicon layer, the buffer layer and the hard mask layer are layers of the same film quality; and performing a planarization treatment, removing the buffer layer, and the height of the third polysilicon layer is the same as that of the hard mask layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and specifically to a method for manufacturing a memory device. Background Technology

[0002] Memory using non-volatile memory (NVM) technology is currently widely used in electronic products with storage functions such as smartphones, tablets, digital cameras, and universal serial bus flash disks (USB flash drives, or "U disks" for short).

[0003] In NVM memory, NORD flash memory features high density, low price, and high transfer efficiency. It has a stacked gate structure, which includes a floating gate (FG) and a control gate (CG) located on top of the floating gate. The stacked gate structure is located on both sides of the word line (WL).

[0004] In related technologies, during the fabrication of NORD flash memory devices, after filling the word line polysilicon layer, planarization is required to form the word lines. However, during the planarization process, the oxide layer planarization suffers from a loading effect, resulting in unevenness and defects on the top of the word line polysilicon, which in turn affects subsequent processes and reduces the reliability and yield of the device. Summary of the Invention

[0005] This application provides a method for fabricating a memory device, which can solve the problem of morphology defects on the top of the polysilicon layer of the word line that are easily encountered in the fabrication methods of memory devices provided in the related art. The method includes:

[0006] A substrate is provided, which, when viewed from a top view, includes a first region and a second region. The first region is used to integrate the memory device, and the second region is a peripheral region. A stack is formed on the substrate, which, from bottom to top, includes an oxide layer, a first polysilicon layer, a first isolation layer, a second polysilicon layer, and a hard mask layer. A via is formed in the stack in the first region, and a second isolation layer is formed around the via.

[0007] A third polysilicon layer is formed on the stacked layers, and the third polysilicon layer fills the via.

[0008] Etching is performed to remove the third polysilicon layer outside the via, wherein the height of the third polysilicon layer inside the via is lower than the height of the hard mask layer;

[0009] A buffer layer is formed on the stacked layers and the third polysilicon layer, wherein the buffer layer and the hard mask layer are of the same film material.

[0010] A planarization process is performed to remove the buffer layer, and the third polysilicon layer and the hard mask layer have the same height.

[0011] In some embodiments, the buffer layer and the hard mask layer comprise a silicon dioxide layer.

[0012] In some embodiments, forming a buffer layer on the stack and the third polysilicon layer includes:

[0013] The buffer layer is formed by depositing a silica layer using the PETEOS process.

[0014] In some embodiments, the storage device is a NORD flash memory device.

[0015] In some embodiments, the planarization process includes:

[0016] Planarization is performed using the CMP process.

[0017] In some embodiments, the first isolation layer includes an ONO layer.

[0018] In some embodiments, the second isolation layer includes a silicon dioxide layer.

[0019] In some embodiments, a silicon nitride layer is formed in the second isolation layer between the third polysilicon layer and the second polysilicon layer.

[0020] The technical solution of this application has at least the following advantages:

[0021] During the fabrication of memory devices, after depositing the word line polysilicon layer, the word line polysilicon layer is etched down to below the hard mask layer, and then a buffer layer is deposited. The buffer layer is then removed through planarization so that the height of the word line polysilicon layer is the same as that of the hard mask layer. Since the buffer layer and the hard mask layer are homogeneous films, the loading effect between the polysilicon layer and the hard mask layer can be reduced during the planarization process, improving the top morphological defects of the word line polysilicon layer and thus improving the reliability and yield of the device to a certain extent. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a method for manufacturing a storage device provided in an exemplary embodiment of this application;

[0024] Figures 2 to 5 This is a flowchart illustrating the fabrication process of a storage device provided in an exemplary embodiment of this application. Detailed Implementation

[0025] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0029] refer to Figure 1 It illustrates a flowchart of a method for manufacturing a storage device provided in an exemplary embodiment of this application, wherein the storage device may be a NORD flash memory device, such as... Figure 1 As shown, the method includes:

[0030] Step S1: A substrate is provided. Viewed from a top angle, the substrate includes a first region and a second region. The first region is used to integrate memory devices, and the second region is a peripheral region. A stack is formed on the substrate. The stack includes, from bottom to top, an oxide layer, a first polysilicon layer, a first isolation layer, a second polysilicon layer, and a hard mask layer. A via is formed in the stack in the first region, and a second isolation layer is formed around the via.

[0031] Step S2: A third polysilicon layer is formed on the stack, and the third polysilicon layer fills the vias.

[0032] refer to Figure 2 This shows a schematic cross-sectional view after the formation of the third polysilicon layer. For example, as shown... Figure 2 As shown, viewed from a top-down perspective, substrate 210 includes a first region 201, a second region 202, and a third region 203. The first region 201 is used to integrate memory devices and is also referred to as a cell area. The second region 202 is a periarea, and the third region 203 is a word line strap area. The first region 201 further includes a first sub-region 2011 and a second sub-region 2012. Viewed from a top-down perspective, the patterns of the devices formed in the first sub-region 2011 and the second sub-region 2012 are perpendicular to each other.

[0033] A stack of layers is formed on the substrate 210, which, from bottom to top, includes an oxide layer 220, a first polysilicon layer 231, a first isolation layer, a second polysilicon layer 232, and a hard mask layer 243. The first polysilicon layer 231 is used to form the floating gate of the memory device, the second polysilicon layer 232 is used to form the control gate of the memory device, and the first isolation layer includes an ONO layer, which, from bottom to top, includes a silicon dioxide layer 2411, a silicon nitride layer 2413, and a silicon dioxide layer 2412. A via 300 is formed in the stack of layers in the first region 201, and the second isolation layer 242 is formed around the via 300. The oxide layer 220 at the bottom of the via 300 is exposed.

[0034] Shallow trench isolation (STI) structures are formed in the substrate 210: a first STI structure 211, a second STI structure 212, a third STI structure 213, and a fourth STI structure 214 are formed in the first region 201. The STI structures in the first region 201 are ring-shaped when viewed from a top view. The area surrounded by this ring is the active area (AA) of the memory device. A fifth STI structure 215 is formed in the second region 202, and a sixth STI structure 216 is formed in the third region 203. The widths of the fifth STI structure 215 and the sixth STI structure 216 are greater than the widths of the first STI structure 211, the second STI structure 212, the third STI structure 213, and the fourth STI structure 214, and the width of the sixth STI structure 216 is greater than the width of the fifth STI structure 215.

[0035] For example, a third polysilicon layer 233 may be formed on the stack using a chemical vapor deposition (CVD) process. The third polysilicon layer 233 fills the vias 300, which are used to form word lines for memory devices. A silicon nitride layer is also formed in the second isolation layer 242 between the third polysilicon layer 233 and the second polysilicon layer 232.

[0036] Step S3: Etch to remove the third polysilicon layer outside the via. The height of the third polysilicon layer inside the via is lower than the height of the hard mask layer.

[0037] refer to Figure 3 This illustrates a cross-sectional view after etching the third polysilicon layer. For example, as shown... Figure 3 As shown, the third polysilicon layer 233 can be etched using a dry etching process to remove the third polysilicon layer 233 outside the via 300 until the height of the third polysilicon layer 233 inside the via 300 is lower than the hard mask layer 243.

[0038] Step S4: A buffer layer is formed on the stacked layers and the third polysilicon layer. The buffer layer and the hard mask layer are of the same film material.

[0039] refer to Figure 4 It shows a schematic cross-sectional view after the buffer layer has been formed. For example, as shown... Figure 4 As shown, the buffer layer 244 and the hard mask layer 243 are of the same film material; for example, they can both include a silicon dioxide layer. The buffer layer 244 can be formed by depositing the silicon dioxide layer using a plasma-enhanced tetraethyl orthosilicate (PETEOS) deposition process.

[0040] Step S5: Perform planarization, remove the buffer layer, and ensure that the third polysilicon layer and the hard mask layer have the same height.

[0041] refer to Figure 5 This illustrates a cross-sectional view after planarization. For example, as shown... Figure 5 As shown, planarization can be achieved through a chemical mechanical polishing (CMP) process until the buffer layer 244 is removed and the third polysilicon layer 233 and the hard mask layer 243 have the same height.

[0042] In summary, in the embodiments of this application, during the fabrication of the memory device, after depositing and forming the word line polysilicon layer, the word line polysilicon layer is etched down to the area below the hard mask layer, and then a buffer layer is deposited. The buffer layer is removed through planarization so that the height of the word line polysilicon layer is the same as that of the hard mask layer. Since the buffer layer and the hard mask layer are homogeneous films, the loading effect between the polysilicon layer and the hard mask layer can be reduced during the planarization process, improving the top morphological defects of the word line polysilicon layer and improving the reliability and yield of the device to a certain extent.

[0043] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing a storage device, characterized in that, include: A substrate is provided, which, when viewed from a top view, includes a first region and a second region. The first region is used to integrate the memory device, and the second region is a peripheral region. A stack is formed on the substrate, which, from bottom to top, includes an oxide layer, a first polysilicon layer, a first isolation layer, a second polysilicon layer, and a hard mask layer. A via is formed in the stack in the first region, and a second isolation layer is formed around the via. The hard mask layer includes a silicon dioxide layer. A third polysilicon layer is formed on the stacked layers, and the third polysilicon layer fills the via. The third polysilicon layer outside the via is removed by a dry etching process, and the height of the third polysilicon layer inside the via is lower than the height of the hard mask layer. A buffer layer is formed by depositing a silicon dioxide layer on the stacked layers and the third polysilicon layer using the PETEOS process. The buffer layer and the hard mask layer are of the same film material. A planarization process is performed to remove the buffer layer, and the third polysilicon layer and the hard mask layer have the same height.

2. The method according to claim 1, characterized in that, The storage device is a NORD flash memory device.

3. The method according to claim 2, characterized in that, The flattening process includes: Planarization is performed using the CMP process.

4. The method according to claim 3, characterized in that, The first isolation layer includes an ONO layer.

5. The method according to claim 4, characterized in that, The second isolation layer includes a silicon dioxide layer.

6. The method according to claim 5, characterized in that, A silicon nitride layer is formed in the second isolation layer between the third polysilicon layer and the second polysilicon layer.

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