Microelectronic devices and related memory devices and electronic systems

Abstract

This application relates to microelectronic devices, memory devices, and electronic systems. A microelectronic device includes a local digital line structure, a global digital line structure, a source line structure, a sensing transistor, a read transistor, and a write transistor. The local digital line structure is coupled to a memory cell string. The global digital line structure overlays the local digital line structure. The source line structure is inserted between the local digital line structure and the global digital line structure. The sensing transistor is inserted between the source line structure and the global digital line structure and coupled to both the local digital line structure and the source line structure. The read transistor is inserted between the sensing transistor and the global digital line structure and coupled to both. The write transistor is inserted between the global digital line structure and the local digital line structure and coupled to both.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 446,340, filed August 30, 2021, entitled “Microelectronic Devices, and Related Memory Devices and Electronic Systems,” the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to microelectronic devices comprising local digital line structures and global digital line structures, and to related memory devices and electronic systems. Background Technology

[0004] Microelectronic device designers typically aim to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by decreasing the spacing between adjacent features. Furthermore, they often seek architectures that are not only compact but also offer performance advantages, as well as simplified designs that are easier and cheaper to manufacture.

[0005] An example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. Many types of memory devices exist, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also known as a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array comprises strings of memory cells that extend vertically through a stacked structure containing conductive structures and insulating materials. Each string of memory cells may contain at least one selection device that is series-coupled to a series combination of vertically stacked memory cells. Compared to structures with a conventional planar (e.g., two-dimensional (2D)) transistor arrangement, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0006] In conventional non-volatile memory devices (e.g., conventional 3D NAND flash memory devices) that include a vertical memory array, digital lines (e.g., bit lines, data lines) are coupled to the strings of memory cells in the vertical memory array, and openings are provided close to the edge of the vertical memory array to accommodate digital line contacts for each of the digital lines. The digital line contacts electrically connect the digital lines to a logic circuit system to facilitate operations on the strings of memory cells in the vertical memory array (e.g., read operations, programming operations, erase operations). However, the conventional configuration of the digital lines and the logic circuit system may hinder improvements in the performance of the non-volatile memory device (e.g., data transfer rate, power consumption) and / or may impede reductions in the size of the non-volatile memory device's features (e.g., horizontal footprint). Summary of the Invention

[0007] In some embodiments, a microelectronic device includes a local digital line structure, a global digital line structure, a source line structure, a sensing transistor, a read transistor, and a write transistor. The local digital line structure is coupled to a memory cell string. The global digital line structure overlays the local digital line structure. The source line structure is inserted between the local digital line structure and the global digital line structure. The sensing transistor is inserted between the source line structure and the global digital line structure and coupled to both the local digital line structure and the source line structure. The read transistor is inserted between the sensing transistor and the global digital line structure and coupled to both. The write transistor is inserted between the global digital line structure and the local digital line structure and coupled to both.

[0008] In an additional embodiment, a microelectronic device includes a stacked structure, a local digital line hierarchy, a global digital line hierarchy, a source line hierarchy, a read / write electrode hierarchy, a layout hierarchy, a first pillar structure, and a second pillar structure. The stacked structure includes conductive structures and insulating structures vertically intersecting the conductive structures. The local digital line hierarchy vertically overlies the stacked structure and includes local digital line structures coupled to a string of memory cells extending vertically through the stacked structure. The global digital line hierarchy vertically overlies the local digital line hierarchy and includes global digital line structures. The source line hierarchy vertically inserts between the local digital line hierarchy and the global digital line hierarchy and includes source line structures. The read / write electrode hierarchy vertically inserts between the source line hierarchy and the global digital line hierarchy and includes read electrode structures and write electrode structures. The layout hierarchy vertically inserts between the source line hierarchy and the read / write electrode hierarchy and includes layout structures coupled to the local digital line structures. The first pillar structure comprises a semiconductor material. The first pillar structure extends vertically from the global digital line structure, through the read electrode structure and the layout structure, and at least reaches the source line structure. The second pillar structure includes additional semiconductor material. The second pillar structure extends vertically from the global digital line structure, through the write electrode structure, and at least reaches the local digital line structure.

[0009] In another embodiment, a memory device includes a source plate, a stacked structure, local digital lines, memory cell strings, global digital lines, sensing transistors, read transistors, and write transistors. The stacked structure overlays the source plate and includes: an access line region including local access line structures; a select gate region underlying the access line region and including a source-side select gate (SGS) structure; and an additional select gate region overlaying the access line region and including a drain-side select gate (SGD) structure. The local digital lines overlay the stacked structure. The memory cell strings extend through the stacked structure and are electrically connected to the source plate and the local digital lines. The global digital lines overlay the local digital lines and are electrically connected to a page buffer circuit system. The horizontal dimension of the global digital lines is larger than the horizontal dimension of the local digital lines. The sensing transistor overlays the local digital lines and is electrically connected to the local digital lines. The read transistor overlays the sensing transistor and is electrically connected to the sensing transistor and the global digital lines. The write transistor is overlaid on the local digital line and is electrically connected to both the local digital line and the global digital line.

[0010] In another embodiment, an electronic system includes: an input device; an output device; a processor device operably connected to the input device and the output device; and a memory device operably connected to the processor device. The memory device includes a memory cell string, a source plate, local digital lines, global digital lines, a source line, a first vertical transistor, a second vertical transistor, and a third vertical transistor. The memory cell string extends vertically through a stacked structure comprising a conductive material alternating vertically with an insulating material. The source plate lies vertically beneath the stacked structure and is electrically connected to the memory cell string. The local digital lines vertically overlap the stacked structure and are electrically connected to the memory cell string. The global digital lines vertically overlap the local digital lines and have a greater horizontal length than the local digital lines. The source line is vertically positioned between the local digital lines and the global digital lines. The first vertical transistor is vertically positioned between the source line and the global digital line. The first vertical transistor is electrically connected to the local digital lines and the source line. The second vertical transistor is vertically positioned between the first vertical transistor and the global digital line and is electrically connected to both the first vertical transistor and the global digital line. The third vertical transistor is vertically positioned between the global digital line and the local digital line and is electrically connected to both the global digital line and the local digital line. Attached Figure Description

[0011] Figure 1A This is a simplified partial perspective view of the microelectronic device structure according to embodiments of the present disclosure.

[0012] Figure 1B yes Figure 1A The diagram shows a simplified partial cross-sectional view of the microelectronic device structure.

[0013] Figure 1C yes Figure 1B The diagram shows a schematic of the circuit system of a segment of the microelectronic device structure.

[0014] Figure 2A This is a simplified partial schematic perspective view of the microelectronic device structure according to an additional embodiment of the present disclosure.

[0015] Figure 2B yes Figure 2A The diagram shows a schematic of the circuit system of a segment of the microelectronic device structure.

[0016] Figure 3 This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0017] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of the present disclosure. However, those skilled in the art will understand that embodiments of the present disclosure can be practiced without these specific details. In fact, embodiments of the present disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structure can be performed using conventional manufacturing techniques.

[0018] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include shape deviations, for example, due to manufacturing processes. For instance, areas illustrated or described as box-shaped may have coarse and / or non-linear characteristics, and areas illustrated or described as circular may contain some coarse and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Thus, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims of the invention. The drawings are not necessarily drawn to scale. Additionally, common elements between the drawings may retain the same numerical designation.

[0019] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory, such as conventional NAND memory; conventional volatile memory, such as conventional DRAM), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory of microelectronic devices, and graphics processing units (GPUs) incorporating memory.

[0020] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and device.

[0021] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surfaces of the structure that have a relatively large area compared to the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0022] As used herein, features described as “adjacent” to each other (e.g., regions, structures, devices) mean and include features that are most closely (e.g., closest to) positioned with the disclosed identifier (or more identifiers). Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identifier (or more identifiers) of “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include features that are most vertically adjacent (e.g., closest to) each other with the disclosed identifier (or more identifiers). Furthermore, features described as “horizontally adjacent” to each other mean and include features that are most horizontally adjacent (e.g., closest to) each other with the disclosed identifier (or more identifiers).

[0023] As used herein, the term "intersection" refers to and includes the location where two or more portions of two or more features (e.g., regions, structures, materials, devices) or, alternatively, a single feature meet. For example, the intersection between a first feature extending along a first direction (e.g., the X direction) and a second feature extending along a second direction different from the first direction (e.g., the Y direction) can be the location where the first and second features meet.

[0024] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” may be used for descriptive purposes to illustrate the relationship between one element or feature and another element or feature as shown in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, an element described as “below,” “under,” “lower,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relation descriptors used herein may be interpreted accordingly.

[0025] Unless the context clearly indicates otherwise, as used herein, the singular forms “a / an” and “the” are also intended to include the plural forms.

[0026] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] As used in this article, the phrase “coupled to” refers to structures that are operationally connected to each other (e.g., by direct ohmic connection or by indirect connection (e.g., by means of another structure) electrically connected).

[0028] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition is satisfied with a deviation (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, characteristic, or condition being substantially satisfied, the parameter, characteristic, or condition may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0029] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes the value, and those skilled in the art will understand that the deviation from the value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0030] As used herein, “conductive material” means and includes one or more of the following conductive materials: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys). Alloys based on Ni, alloys based on Fe and Ni, alloys based on Co and Ni, alloys based on Fe and Co, alloys based on Co, Ni, and Fe, alloys based on Al, alloys based on Cu, alloys based on magnesium (Mg), alloys based on Ti, steel, low-carbon steel, stainless steel; materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" refers to and includes structures formed from and containing conductive materials.

[0031] As used herein, “insulating material” means and includes one or more of the following electrically insulating materials: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following); at least one dielectric nitride material (e.g., silicon nitride (SiN)y At least one dielectric oxide material (e.g., silicon oxynitride (SiO2)). x N y At least one dielectric carbon oxide material (e.g., silicon dioxide (SiO2)). x C y At least one hydrogenated dielectric carbon oxide material (e.g., hydrogenated silicon carbide (SiC)). x O y H z )); and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2) x C z N y This document contains the chemical formula of one or more of "x", "y" and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C y SiC x O y H z SiO x C z N y A chemical formula represents a material containing "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because a chemical formula represents relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of an element that cannot be expressed by a ratio of clearly defined natural numbers and violates the law of definite proportions. Furthermore, "insulating structure" means and includes structures formed from and containing insulating materials.

[0032] As used herein, the term "homogeneous" means that the relative amounts of elements contained in a feature (e.g., region, material, structure) do not change throughout the different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "heterogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) change throughout the different parts of the feature. If a feature is heterogeneous, the amounts of one or more elements contained in the feature may change gradually (e.g., abruptly) or may change continuously throughout the different parts of the feature (e.g., gradually, such as linearly or parabolically). A feature may, for example, be formed by and contain a stack of at least two different materials.

[0033] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by a person skilled in the art. Additionally, unless the context otherwise indicates, the material removal described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0034] Figure 1A This is a simplified partial perspective view of a microelectronic device structure 100 (e.g., a memory device structure, such as a 3D NAND flash memory device structure) of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) according to embodiments of the present disclosure. Figure 1B It is about Figure 1A A simplified partial cross-sectional view of the microelectronic device structure 100 depicted by the dashed line AA. Figure 1C yes Figure 1B This is a schematic diagram of the circuit system of a segment of the microelectronic device structure 100 shown. For clarity and ease of understanding of the diagrams and related descriptions, it is not intended to depict... Figures 1A to 1C All features (e.g., regions, structures, materials, devices) of the microelectronic device structure 100 depicted in one or more figures are shown in [the figures]. Figures 1A to 1C One or more other figures are depicted herein. In conjunction with the description provided below, it will be readily apparent to those skilled in the art that the structures and apparatus described herein can be included within relatively large structures, apparatuses, and systems.

[0035] Common Reference Figure 1A and 1B The microelectronic device structure 100 may be configured to include a source layer 101; a stacked structure 104 vertically overlying (e.g., along the Z direction) the source layer 101; a local digital line layer 126 vertically overlying the stacked structure 104; a global digital line layer 134 vertically overlying the local digital line layer 126; a read / write electrode layer 138 vertically inserted between the local digital line layer 126 and the global digital line layer 134; a source line layer 144 vertically inserted between the local digital line layer 126 and the read / write electrode layer 138; and a layout layer 148 vertically inserted between the source line layer 144 and the read / write electrode layer 138. As described in further detail below, the microelectronic device structure 100 includes various features (e.g., regions, structures, materials, devices) that are operatively associated with one or more of the source layer 101, stack structure 104, local digital line layer 126, global digital line layer 134, read / write electrode layer 138, source line layer 144, and layout layer 148 (e.g., located within an additional feature of one or more of the aforementioned layers; extending into an additional feature, extending through an additional feature, and / or extending between additional features; physically connected to and / or electrically connected to an additional feature).

[0036] Source layer 101 may include at least one source structure 102 (e.g., a source plate), said source structure being at least partially positioned such that a horizontal region of stacked structure 104 vertically overlaps source layer 101. Source structure 102 may be formed of and include a conductive material, such as one or more of a metal, alloy, and a material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). As a non-limiting example, source structure 102 may be formed of and include W.

[0037] The stacked structure 104 of the microelectronic device structure 100 may be formed as a vertically alternating (e.g., along the Z direction) sequence of conductive structures 106 and insulating structures 108 arranged in layers 110. The conductive structures 106 may be vertically staggered with the insulating structures 108. Each of the layers 110 of the stacked structure 104 may include at least one of the conductive structures 106 vertically adjacent to at least one of the insulating structures 108. The stacked structure 104 may be formed as having any desired number of layers 110, such as more than or equal to sixteen (16) layers 110, more than or equal to thirty-two (32) layers 110, more than or equal to sixty-four (64) layers 110, more than or equal to one hundred and twenty-eight (128) layers 110, or more than or equal to two hundred and fifty-six (256) layers 110.

[0038] The conductive structure 106 of the layer 110 of the stacked structure 104 may be formed of and contain a conductive material. By means of a non-limiting example, each of the conductive structures 106 may be formed of and contain a metallic material comprising one or more of the following: at least one metal, at least one alloy, and at least one conductive metallic material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the conductive structure 106 is formed of and contains W. Each of the conductive structures 106 may be substantially homogeneous, or one or more of the conductive structures 106 may be substantially heterogeneous. In some embodiments, each of the conductive structures 106 is formed to be substantially homogeneous.

[0039] Optionally, one or more lining materials (e.g., insulating lining materials, conductive lining materials) may also be formed around the conductive structure 106. The lining materials may be formed from, for example, one or more of, and include one or more of, the following: metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the lining material includes at least one conductive material used as a seed material for forming the conductive structure 106. In some embodiments, the lining material includes titanium nitride. In other embodiments, the lining material further includes aluminum oxide. As a non-limiting example, aluminum oxide may be formed directly adjacent to the insulating structure 108, titanium nitride may be formed directly adjacent to aluminum oxide, and tungsten may be formed directly adjacent to titanium nitride. For clarity and ease of understanding of the description, Figure 1A and 1B The lining material is not shown, but it should be understood that the lining material may be placed around the conductive structure 106.

[0040] The insulating structure 108 of the layer 110 of the stacked structure 104 may be formed of and contain an insulating material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxynitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2).x C z N y In some embodiments, each of the insulating structures 108 is made of, for example, SiO2. x The insulating structure 108 is formed and comprises a dielectric oxide material such as SiO2. Each of the insulating structures 108 may be substantially homogeneous or substantially heterogeneous. In some embodiments, each of the insulating structures 108 is substantially homogeneous.

[0041] like Figure 1A and 1B As shown, the stacked structure 104 can be subdivided into access line layers 112, at least one select gate layer 114 (e.g., a lower select gate layer), and at least one additional select gate layer 116 (e.g., an upper select gate layer). The access line layer 112 can be vertically inserted between the select gate layer 114 and the additional select gate layer 116. At least some conductive structures 106 within the access line layer 112 can serve as local access line structures (e.g., local word line structures) of the microelectronic device structure 100. At least one conductive structure 106 within the select gate layer 114 can serve as at least one first select gate structure (e.g., at least one source-side select gate (SGS) structure) of the microelectronic device structure 100. At least one conductive structure 106 within the additional select gate layer 116 can serve as at least one second select gate structure (e.g., at least one drain-side select gate (SGD) structure) of the microelectronic device structure 100. In some embodiments, an additional selected horizontally adjacent conductive structure 106 within the gate layer 116 (e.g., along the X direction) is used as an additional selected gate structure (e.g., SGD structure) for the microelectronic device structure 100.

[0042] like Figure 1A and 1B As depicted, in some embodiments, the stack structure 104 includes four (4) access line layers 112 (e.g., first access line layer 112A, second access line layer 112B, third access line layer 112C, and fourth access line layer 112D), one select gate layer 114, and one additional select gate layer 116. However, the stack structure 104 may be configured to include a different number of access line layers 112 (e.g., more than four (4) access line layers 112), a different number of select gate layers 114 (e.g., more than one select gate layer 114, such as two or more select gate layers 114), and / or a different number of additional select gate layers 116 (e.g., more than one additional select gate layer 116, such as two or more additional select gate layers 116, three or more additional select gate layers 116, or four or more additional select gate layers 116).

[0043] refer to Figure 1B The first pillar structure 118 may extend vertically through the layers 110 of the stacked structure 104. Each of the first pillar structures 118 may be formed and comprise a stack of materials. By means of a non-limiting example, each of the first pillar structures 118 may be formed to comprise: a charge-blocking material, such as a first dielectric oxide material (e.g., SiO2). x For example, SiO2; AlO x (e.g., Al2O3); charge trapping materials, such as dielectric nitride materials (e.g., SiN). y (e.g., Si3N4); tunneling dielectric materials, such as second dielectric oxide materials (e.g., SiO2). x The channel material is a semiconductor material (e.g., silicon, such as polycrystalline silicon); and the dielectric filling material is a dielectric oxide, dielectric nitride, or air. A charge-blocking material may be formed on or above the conductive structure 106 and insulating structure 108 of the layer 110 of the stacked structure 104, which at least partially defines the horizontal boundary of the first pillar structure 118; a charge-trapping material may be horizontally surrounded by the charge-blocking material; a tunneling dielectric material may be horizontally surrounded by the charge-trapping material; a channel material may be horizontally surrounded by the tunneling dielectric material; and a dielectric filling material may be horizontally surrounded by the channel material.

[0044] The intersection of the first pillar structure 118 and the conductive structure 106 within the access line layer 112 of the stacked structure 104 may define a vertically extending string of memory cells 120 coupled in series with each other within the stacked structure 104. In some embodiments, the memory cells 120 formed at the intersection of the conductive structure 106 and the first pillar structure 118 within the access line layer 112 of the stacked structure 104 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 120 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subgroup of MONOS memory cells. In another embodiment, the memory cells 120 include so-called "floating gate" memory cells, which include a floating gate (e.g., a metal floating gate) as a charge storage structure. A floating gate may be horizontally positioned between the first pillar structure 118 of the different access line layers 112 of the stacked structure 104 and the central structure of the conductive structure 106. Vertically extending strings of memory cells 120 together form at least one memory array within the stacked structure 104.

[0045] Still referencing Figure 1BThe intersection of the first pillar structure 118 within the select gate level 114 of the stacked structure 104 and the conductive structure 106 may define a select transistor 122 coupled in series with the vertically extending memory cell string 120. A portion of the first pillar structure 118 within the vertical boundary of the select gate level 114 of the stacked structure 104 may contain a tunnel dielectric material (e.g., SiO2). x (e.g., SiO2), channel materials (e.g., silicon, such as polycrystalline silicon), and dielectric filling materials (e.g., SiO2). x For example, SiO2; SiN y The material may contain, for example, Si3N4; air, but may at least partially (e.g., substantially) exclude charge-blocking and charge-trapping materials present in an additional portion of the first pillar structure 118 within the vertical boundary of the access line layer 112 of the stacked structure 104. In some embodiments, the select transistor 122 comprises a metal-oxide-semiconductor (MOS) transistor. If the conductive structure 106 within the select gate layer 114 of the stacked structure 104 serves as the SGS structure of the microelectronic device structure 100, then the select transistor 122 may comprise a MOS-SGS transistor.

[0046] Additionally, the intersection of the first pillar structure 118 within the additional selective gate level 116 of the stacked structure 104 and the conductive structure 106 may define an additional selective transistor 124 coupled in series with the vertically extending memory cell string 120. A further portion of the first pillar structure 118 within the vertical boundary of the additional selective gate level 116 of the stacked structure 104 may contain a tunnel dielectric material (e.g., SiO2). x (e.g., SiO2), channel materials (e.g., silicon, such as polycrystalline silicon), and dielectric filling materials (e.g., SiO2). x For example, SiO2; SiN y The material may contain, for example, Si3N4; air, but may at least partially (e.g., substantially) exclude charge-blocking and charge-trapping materials within the additional portion of the first pillar structure 118 contained within the vertical boundary of the access line layer 112 of the stacked structure 104. In some embodiments, the additional selection transistor 124 comprises a MOS transistor. If the conductive structure 106 within the additional selection gate layer 116 of the stacked structure 104 serves as the SGD structure of the microelectronic device structure 100, the additional selection transistor 124 may comprise a MOS-SGD transistor.

[0047] Common Reference Figure 1A and 1B The local digital line layer 126 may contain multiple (e.g., more than one, many) local digital line structures 128. The local digital line structures 128 may vertically superimpose on the first column structure 118. Figure 1BLocal digital line structures 128 can extend horizontally along the X direction (e.g., a first horizontal direction). The local digital line hierarchy 126 may include rows of local digital line structures 128 extending along the X direction, and columns of local digital line structures 128 extending along a Y direction orthogonal to the X direction (e.g., a second horizontal direction). A group of local digital line structures 128 disposed within a single row of local digital line structures 128 can be substantially horizontally aligned with each other along the Y direction, horizontally separated from each other along the X direction, and horizontally extended in series along the X direction. As described in further detail below, these local digital line structures 128 disposed within the same row of local digital line structures 128 can be operatively associated with the same global digital line structures. Additionally, a group of local digital line structures 128 disposed within a single column of local digital line structures 128 can be substantially horizontally aligned with each other along the X direction, horizontally separated from each other along the Y direction, and extended parallel to each other along the X direction. By means of non-limiting examples, such as... Figure 1A As depicted, a single column of local digital line structures 128 may include a first local digital line structure 128A and a second local digital line structure 128B spaced apart from the first local digital line structure 128A. As described in further detail below, these local digital line structures 128 disposed within the same column of local digital line structures 128 may be operatively associated with different global digital line structures.

[0048] The local digital line structures 128 may each be formed of and contain a conductive material. By means of non-limiting examples, the local digital line structures 128 may each be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the local digital line structures 128 are each formed of W, Ru, Mo, and titanium nitride (TiN). y One or more of these components are formed and contain W, Ru, Mo, and titanium nitride (TiN). y One or more of the local digital line structures 128. Each of the local digital line structures 128 may be substantially homogeneous, or one or more of the local digital line structures 128 may be substantially heterogeneous. In some embodiments, each of the local digital line structures 128 is formed to be substantially homogeneous.

[0049] Still referencing Figure 1A and 1B The microelectronic device structure 100 further includes a first conductive contact structure 132, the first conductive contact structure being vertically positioned between at least some local digital line structures 128 and at least some first pillar structures 118. Figure 1BThe at least some local digital line structures and the at least some first pillar structures are electrically connected between each other. Each of the first conductive contact structures 132 may be formed of and contain a conductive material. By means of a non-limiting example, each of the first conductive contact structures 132 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, each of the first conductive contact structures 132 is formed of W, Ru, Mo, and TiN. y One or more of them are formed and contain W, Ru, Mo and TiN y One or more of them.

[0050] The global digital line hierarchy 134 may contain multiple (e.g., more than one, many) global digital line structures 136. Global digital line structures 136 may vertically superimpose on local digital line structures 128 and may extend horizontally along the X direction. Global digital line structures 136 may be horizontally separated from each other along the Y direction and may extend parallel to each other along the X direction. As a non-limiting example, such as Figure 1A As depicted, the global digital line hierarchy 134 may include a first global digital line structure 136A and a second global digital line structure 136B spaced apart from the first global digital line structure 136A. Different global digital line structures 136 may be operatively associated with different local digital line structures 128. Each of the global digital line structures 136 may be operatively associated with a single row of local digital line structures 128, wherein different global digital line structures 136 (e.g., the first global digital line structure 136A, the second global digital line structure 136B) may be operatively associated with different rows of local digital line structures 128. For example, the first global digital line structure 136A may be operatively associated with a first local digital line structure 128A and at least one additional local digital line structure 128 within the same row (e.g., the first row) of local digital line structures 128 as the first local digital line structure 128A; and the second global digital line structure 136B ( Figure 1A It can be used with the second local digital line structure 128B ( Figure 1AThe local digital line structure 128 is operatively associated with at least one additional local digital line structure 128 within the same row (e.g., the second row) as the second local digital line structure 128B. Additionally, each column of local digital line structures 128 may be operatively associated with a plurality of global digital line structures 136. For example, the first local digital line structure 128A and the second local digital line structure 128B within the same column (e.g., the first column) of local digital line structures 128 may be operatively associated with the first global digital line structure 136A and the second global digital line structure 136B, respectively. The global digital line structure 136 may be operatively associated with the local digital line structures 128 at least in part by means of additional features of the microelectronic device structure 100, which are operatively associated with one or more of the read / write electrode layers 138, source line layers 144, and layout layers 148, as described in further detail below. The horizontal dimension (e.g., length) of the global digital line structure 136 along the X direction may be greater than (e.g., longer than) the horizontal dimension (e.g., length) of the local digital line structure 128 that is operatively associated with it along the X direction.

[0051] The global digital line structures 136 may each be formed of and comprise a conductive material. By way of non-limiting examples, the global digital line structures 136 may each be formed of and comprise one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the global digital line structures 136 are each formed of W, Ru, Mo, and TiN. y One or more of them are formed and contain W, Ru, Mo and TiN y One or more of the global digital line structures 136 may be substantially homogeneous, or one or more of the global digital line structures 136 may be substantially heterogeneous. In some embodiments, each of the global digital line structures 136 is formed to be substantially homogeneous.

[0052] The global digital line structure 136 may be coupled to a logic circuit system (e.g., a page buffer circuit system) of the microelectronic device including the microelectronic device structure 100. The logic circuit system may, for example, be contained within a base structure vertically recessed into the microelectronic device structure 100. In some embodiments, the global digital line structure 136 is coupled to page buffer devices, each of which respectively includes an arrangement of data cache circuitry (e.g., dynamic data cache (DDC) circuitry, primary data cache (PDC) circuitry, secondary data cache (SDC) circuitry, temporary data cache (TDC) circuitry), sense amplifier (SA) circuitry, and digital line precharge circuitry. Optionally, an isolation device (e.g., an isolation transistor) may be inserted at a desired location along a conductive path extending from and between the global digital line structure 136 and the page buffer devices. In some embodiments, the isolation device includes a high-voltage isolation (HVISO) transistor configured to deliver a voltage greater than or equal to about 18V, for example, in the range of about 18V to about 25V. In an additional embodiment, the isolation device includes a low-voltage isolation (LVISO) transistor configured to substantially block applied voltages less than about 18V when in an off state (e.g., inactive, depleted, or deselected).

[0053] Still referencing Figure 1A and 1B The read / write electrode layer 138 may include read electrode structures 140 and write electrode structures 142. Read electrode structures 140 and 142 may be vertically inserted between local digital line structures 128 and global digital line structures 136, and may extend horizontally in the Y direction, orthogonal to the X direction in which the local digital line structures 128 and global digital line structures 136 extend horizontally. Each of the local digital line structures 128 may be operatively associated with one of the read electrode structures 140 and one of the write electrode structures 142, as described in further detail below. Additionally, each of the global digital line structures 136 may be operatively associated with a plurality (e.g., more than one) of read electrode structures 140 and a plurality (e.g., more than one) of write electrode structures 142, as also described in further detail below.

[0054] The read electrode structure 140 is spaced apart from the write electrode structure 142 along the X direction and may extend horizontally parallel to each other and parallel to the write electrode structure 142 along the Y direction. As described in further detail below, the read electrode structure 142 may be used as the gate structure of a switching transistor (e.g., a read transistor) of the microelectronic device structure 100. Each of the read electrode structures 140 may be operatively associated with a set of local digital line structures 128 within a separate column of local digital line structures 128. For example, as Figure 1A As shown, a first local digital line structure 128A and a second local digital line structure 128B within the same column of local digital line structures 128 can each be operatively associated with a single (e.g., only one) read electrode structure 140 of the read / write electrode hierarchy 138. Different groups of local digital line structures 128 within different columns of local digital line structures 128 can be operatively associated with different read electrode structures 140. Additionally, each of the read electrode structures 140 can be operatively associated with multiple (e.g., more than one) global digital line structures 136. For example, as... Figure 1A As shown, an individual read electrode structure 140 may be operatively associated with each of the first global digital line structure 136A and the second global digital line structure 136B. Furthermore, each of the global digital line structures 136 may be operatively associated with a plurality (e.g., more than one) of read electrode structures 140 of the read / write electrode hierarchy 138. For example, the first global digital line structure 136A and the second global digital line structure 136B may each be associated with more than one read electrode structure 140 (e.g., ...). Figure 1A The read electrode structure 140 shown is operatively associated with at least one additional read electrode structure 140 operatively associated with at least one additional column of local digital line structure 128.

[0055] Still referencing Figure 1AThe write electrode structure 142 may alternate horizontally with the read electrode structure 140 along the X direction. As described in further detail below, the write electrode structure 142 may serve as the gate structure of an additional switching transistor (e.g., a write transistor) of the microelectronic device structure 100. Each of the write electrode structures 142 may be operatively associated with a group of local digital line structures 128 within a single column of local digital line structures 128. Each column of local digital line structures 128 may be operatively associated with a single (e.g., only one) write electrode structure 142 and a single read electrode structure 140 horizontally adjacent to the single write electrode structure 142 (e.g., along the X direction). For example, a first local digital line structure 128A and a second local digital line structure 128B within the same column of local digital line structures 128 may each be operatively associated with a single write electrode structure 142 of the read / write electrode hierarchy 138. Different groups of local digital line structures 128 within different columns of local digital line structures 128 may be operatively associated with different write electrode structures 142. Additionally, each of the written electrode structures 142 can be operatively associated with multiple (e.g., more than one) global digital line structures 136. For example, as Figure 1A As shown, an individual write electrode structure 142 may be operatively associated with each of the first global digital line structure 136A and the second global digital line structure 136B. Furthermore, each of the global digital line structures 136 may be operatively associated with a plurality (e.g., more than one) of write electrode structures 142 of the read / write electrode hierarchy 138. For example, the first global digital line structure 136A and the second global digital line structure 136B may each be associated with more than one write electrode structure 142 (e.g., Figure 1A The write electrode structure 142 shown is operatively associated with at least one additional write electrode structure 142 operatively associated with at least one additional column of local digital line structure 128.

[0056] The read electrode structure 140 and the write electrode structure 142 may each be formed of and contain a conductive material. By way of non-limiting examples, the read electrode structure 140 and the write electrode structure 142 may each be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the read electrode structure 140 and the write electrode structure 142 are each formed of W, Ru, Mo, and TiN. y One or more of them are formed and contain W, Ru, Mo and TiN yOne or more of the read electrode structures 140 and the write electrode structures 142 may be substantially homogeneous, or one or more of the read electrode structures 140 and / or one or more of the write electrode structures 142 may be substantially heterogeneous. In some embodiments, each of the read electrode structures 140 and each of the write electrode structures 142 is formed to be substantially homogeneous.

[0057] Common reference Figure 1A and 1B Source line hierarchy 144 includes source line structures 146. Source line structures 146 are vertically inserted between local digital line structures 128 of local digital line hierarchy 126 and read electrode structures 140 of read / write electrode hierarchy 138. Source line structures 146 extend horizontally along a Y-direction orthogonal to the X-direction along which the local digital line structures 128 and global digital line structures 136 extend horizontally. As described further below, each of the local digital line structures 128 is operatively associated with one of the source line structures 146, and each of the read electrode structures 140 is operatively associated with one of the source line structures 146. Furthermore, as described further below, each of the global digital line structures 136 is operatively associated with multiple (e.g., more than one) source line structures 146.

[0058] like Figure 1A As shown, each of the source line structures 146 can be operatively associated with one of the read electrode structures 140 and a group of local digital line structures 128 within a single column of local digital line structures 128. For example, a first local digital line structure 128A and a second local digital line structure 128B within the same column of local digital line structures 128, and a single (e.g., only one) read electrode structure 140 operatively associated with them, can each be operatively associated with a single (e.g., only one) source line structure 146 of the source line hierarchy 144. Different groups of local digital line structures 128 within different columns of local digital line structures 128, and different read electrode structures 140 operatively associated with different columns of local digital line structures 128, can be operatively associated with different source line structures 146. Additionally, each of the source line structures 146 can be operatively associated with multiple (e.g., more than one) global digital line structures 136. For example, as Figure 1AAs shown, an individual source line structure 146 may be operatively associated with each of the first global digital line structure 136A and the second global digital line structure 136B. Furthermore, each of the global digital line structures 136 may be operatively associated with a plurality (e.g., more than one) source line structures 146 of the source line hierarchy 144. For example, the first global digital line structure 136A and the second global digital line structure 136B may each be associated with more than one source line structure 146 (e.g., Figure 1A The source line structure 146 shown is operatively associated with at least one additional source line structure 146 that is operatively associated with at least one additional column of local digital line structure 128.

[0059] The source line structures 146 may each be formed of and comprise a conductive material. By way of non-limiting examples, the source line structures 146 may each be formed of and comprise one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the source line structures 146 are each formed of W, Ru, Mo, and TiN. y One or more of them are formed and contain W, Ru, Mo and TiN y One or more of the source line structures 146. Each of the source line structures 146 may be substantially homogeneous, or one or more of the source line structures 146 may be substantially heterogeneous. In some embodiments, each of the source line structures 146 is formed to be substantially homogeneous.

[0060] refer to Figure 1A and 1B Layout layer 148 includes layout structures 150. Layout structures 150 can be vertically inserted between source line structures 146 of source line layer 144 and read electrode structures 140 of read / write electrode layer 138. Layout structures 150 can extend horizontally along the X direction. As described in further detail below, each of the layout structures 150 can be operatively associated with one of the local digital line structures 128, one of the source line structures 146, one of the read electrode structures 140, and one of the global digital line structures 136. Furthermore, as described in further detail below, each of the global digital line structures 136 can be operatively associated with multiple (e.g., more than one, many) layout structures 150.

[0061] like Figure 1AAs shown, each of the layout structures 150 can be operatively associated with one of the local digital line structures 128. For example, a first local digital line structure 128A can be operatively associated with one of the layout structures 150, and a second local digital line structure 128B can be operatively associated with another of the layout structures 150. The layout structure 150 can be coupled to the local digital line structures 128. As described in further detail below, the layout structure 150 can be used as the gate structure of a sense transistor inserted between and operatively associated with the source line structure 146 and the read electrode structure 140. Different groups of local digital line structures 128 within different columns of local digital line structures 128 and different read electrode structures 140 operatively associated with different columns of local digital line structures 128 can be operatively associated with different groups of layout structures 150. In addition, each of the layout structures 150 can be operatively associated with one of the global digital line structures 136. For example, such as Figure 1A As shown, the first global digital line structure 136A can be operatively associated with one of the layout structures 150 operatively associated with the first local digital line structure 128A; and the second global digital line structure 136B can be operatively associated with another of the layout structures 150 operatively associated with the second local digital line structure 128B. Furthermore, each of the global digital line structures 136 can be operatively associated with multiple (e.g., more than one) layout structures 150 of the layout hierarchy 148. For example, the first global digital line structure 136A can be operatively associated with different layout structures 150 operatively associated with different local digital line structures 128 within a single row of local digital line structures 128 extending along the X direction; and the second global digital line structure 136B can be operatively associated with other different layout structures 150 operatively associated with other different local digital line structures 128 within another single row of local digital line structures 128 extending along the X direction.

[0062] The arrangement structure 150 may each be formed of and comprise a conductive material. By way of non-limiting examples, the arrangement structure 150 may each be formed of and comprise one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the arrangement structure 150 may each be formed of W, Ru, Mo, and TiN. y One or more of them are formed and contain W, Ru, Mo and TiN yOne or more of the arrangements. Each of the arrangements 150 may be substantially homogeneous, or one or more of the arrangements 150 may be substantially heterogeneous. In some embodiments, each of the arrangements 150 is formed to be substantially homogeneous.

[0063] Still referencing Figure 1A and 1B The microelectronic device structure 100 further includes a second pillar structure 152 operatively associated with the local digital line structure 128, the source line structure 146, the layout structure 150, the readout electrode structure 140, and the global digital line structure 136. The second pillar structure 152 may extend vertically from one of the global digital line structures 136 (e.g., the first global digital line structure 136A, the second global digital line structure 136B), through each of the readout electrode structures 140 and the layout structure 150, and reach at least one of the source line structures 146 (e.g., extending thereto, extending into it, extending beyond it).

[0064] The second pillar structure 152 may be formed and comprise at least of a semiconductor material (e.g., silicon, such as polycrystalline silicon; oxide semiconductor material). One or more vertical regions of the semiconductor material of the second pillar structure 152 may be doped, or the semiconductor material of the second pillar structure 152 may be substantially undoped. If doped, the semiconductor material of the second pillar structure 152 may be doped with one or more conductivity-enhancing materials (e.g., one or more N-type dopants, such as phosphorus, arsenic, antimony, and bismuth; one or more P-type dopants, such as boron, aluminum, and gallium) to facilitate the reading of the desired vertical transistor at the intersection of the electrode structure 140 and the layout structure 150, as described in further detail below. In some embodiments, each of the second pillar structures 152 is formed and comprises a stack of materials. For example, each of the second pillar structures 152 may include at least a semiconductor material, and a tunneling dielectric material (e.g., a dielectric oxide material, such as SiO2) that horizontally surrounds and covers at least a portion of the second pillar structure 152 at the intersection of the second pillar structure 152 with one of the read electrode structures 140 and one of the layout structures 150. x Additionally, each of the second pillar structures 152 may optionally include one or more conductive materials vertically inserted between its semiconductor material and at least one (e.g., each) global digital line structure 136 and source line structure 146 operatively associated with it.

[0065] Still referencing Figure 1A and 1BThe intersection of the second pillar structure 152 and the read electrode structure 140 may define a read transistor 158 (e.g., a first switching transistor) of the microelectronic device structure 100. The read transistor 158 may include a vertical transistor comprising a channel region vertically offset from the source / drain region. In some embodiments, the read transistor 158 includes a MOS transistor. The channel region of the read transistor 158 may be located within the vertical boundary of the read electrode structure 140; and the source / drain region of the read transistor 158 may be vertically adjacent to the channel region and vertically offset from the read electrode structure 140. The tunnel dielectric material of the second pillar structure 152 may be horizontally inserted between the semiconductor material of the second pillar structure 152 and the read electrode structure 140 within the vertical boundary of the read electrode structure 140, and may serve as the gate dielectric structure of the read transistor 158.

[0066] Additionally, the intersection of the second pillar structure 152 and the layout structure 150 may define a sensing transistor 160 of the microelectronic device structure 100. The sensing transistor 160 may include a vertical transistor comprising a channel region vertically offset from the source / drain regions. For each second pillar structure 152, the sensing transistor 160 defined thereby may be arranged in series with a read transistor 158 defined thereby. As a non-limiting example, for each individual sensing transistor 160 defined by an individual second pillar structure 152, the drain region of the sensing transistor 160 may be coupled to the source region of the individual read transistor 158 vertically overlying the sensing transistor 160 and defined by the second pillar structure 152. The sensing transistor 160 defined by the second pillar structure 152 may be physically and electrically inserted between the read transistor 158 defined by the second pillar structure 152 and each of the source line structure 146 and the local digital line structure 128 operatively associated with the second pillar structure 152. In some embodiments, the sensing transistor 160 includes a MOS transistor. In some such embodiments, the sensing transistor 160 includes a PMOS transistor, such that the conductive structure 106 of the stacked structure 104 (e.g., used as a local access line structure) can be driven from low to high. The channel region of the sensing transistor 160 may be located within the vertical boundary of the layout structure 150; and the source / drain regions of the sensing transistor 160 may be vertically adjacent to the channel region and vertically offset from the layout structure 150. The tunnel dielectric material of the second pillar structure 152 may be horizontally inserted between the semiconductor material of the second pillar structure 152 and the layout structure 150 within the vertical boundary of the layout structure 150, and may serve as the gate dielectric structure of the sensing transistor 160.

[0067] Still referencing Figure 1A and 1BThe microelectronic device structure 100 further includes a third pillar structure 154 operatively associated with the local digital line structure 128, the write electrode structure 142, and the global digital line structure 136. The third pillar structure 154 may extend vertically from one of the global digital line structures 136 (e.g., the first global digital line structure 136A, the second global digital line structure 136B), through one of the write electrode structures 142, and at least reach one of the local digital line structures 128 (e.g., the first local digital line structure 128A, the second local digital line structure 128B) (e.g., extending thereto, extending therein).

[0068] The third pillar structure 154 may be formed and comprise at least of a semiconductor material (e.g., silicon, such as polycrystalline silicon; oxide semiconductor material). One or more vertical regions of the semiconductor material of the third pillar structure 154 may be doped, or the semiconductor material of the third pillar structure 154 may be substantially undoped. If doped, the semiconductor material of the third pillar structure 154 may be doped with one or more conductivity-enhancing materials (e.g., one or more N-type dopants, such as phosphorus, arsenic, antimony, and bismuth; one or more P-type dopants, such as boron, aluminum, and gallium) to facilitate the writing of desired vertical transistors at the intersections of the electrode structures 142, as described in further detail below. In some embodiments, each of the third pillar structures 154 is formed and comprises a stack of materials. For example, each of the third pillar structures 154 may include at least a semiconductor material, and a tunneling dielectric material (e.g., a dielectric oxide material, such as SiO2) that horizontally surrounds and covers at least a portion of the third pillar structure 154 at the intersection of the third pillar structure 154 and one of the write electrode structures 142. x Additionally, each of the third pillar structures 154 may optionally include one or more conductive materials vertically inserted between its semiconductor material and at least one (e.g., each) global digital line structure 136 and local digital line structure 128 operatively associated with it.

[0069] The intersection of the third pillar structure 154 and the write electrode structure 142 may define a write transistor 162 (e.g., a second switching transistor) of the microelectronic device structure 100. In some embodiments, the write transistor 162 includes a MOS transistor. The channel region of the write transistor 162 may be located within the vertical boundary of the write electrode structure 142; and the source / drain regions of the write transistor 162 may be vertically adjacent to the channel region and vertically offset from the write electrode structure 142. The tunnel dielectric material of the third pillar structure 154 may be horizontally inserted between the semiconductor material of the third pillar structure 154 and the write electrode structure 142 within the vertical boundary of the write electrode structure 142, and may serve as the gate dielectric structure of the write transistor 162.

[0070] Still referencing Figure 1A and 1B The microelectronic device structure 100 further includes a second conductive contact structure 156 operatively associated with the local digital line structure 128 and the layout structure 150. The second conductive contact structure 156 may extend vertically from one of the layout structures 150 and reach at least one of the local digital line structures 128 (e.g., the first local digital line structure 128A, the second local digital line structure 128B) (e.g., extending thereto, extending therein). Each second conductive contact structure 156 may facilitate electrical communication between the local digital line structure 128 and the layout structure 150 operatively associated with it (and therefore, the sensing transistor 160, the readout transistor 158, and the global digital line structure 136).

[0071] The second conductive contact structures 156 may each be formed of and comprise a conductive material. By way of non-limiting examples, the second conductive contact structures 156 may each be formed of and comprise one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the second conductive contact structures 156 are each formed of W, Ru, Mo, and TiN. y One or more of them are formed and contain W, Ru, Mo and TiN y One or more of the second conductive contact structures 156 may be substantially homogeneous, or one or more of the second conductive contact structures 156 may be substantially heterogeneous.

[0072] Common reference Figures 1A to 1C The source line structure 146, sensing transistor 160, read transistor 158, and write transistor 142 form a portion of a read / write circuit inserted between the local digital line structure 128 and the global digital line structure 136. The sensing transistor 160 is coupled to the local digital line structure 128, electrically connected to the source line structure 146, and also electrically connected to the global digital line structure 136 via the read transistor 158. The write transistor 142 is electrically connected to both the local digital line structure 128 and the global digital line structure 136.

[0073] During a read operation of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) including the microelectronic device structure 100, the local digital line structure 128 and the operatively associated global digital line structure 136 can be precharged and floated by means of the operatively associated write transistor 162. Thereafter, the operatively associated read electrode structure 140 can be activated. If the read cell current (I...) cell If the current (If) flows, the potential level of the local digital line structure 128 decreases, the operatively associated sensing transistor 160 is turned off, and the potential level of the global digital line structure 136 remains at the pre-charge level. Conversely, if the read cell current (If) flows, the potential level of the local digital line structure 128 decreases, the operatively associated sensing transistor 160 is turned off, and the potential level of the global digital line structure 136 remains at the pre-charge level. cell If the current does not flow, the potential level of the local digital line structure 128 remains at the pre-charge level, the operatively associated sensing transistor 160 is turned on, and the potential level of the global digital line structure 136 decreases. The potential level of the global digital line structure 136 can be detected by a sensing amplifier of a page buffer device operatively associated with the global digital line structure 136. Since each local digital line structure 128 is relatively shorter (e.g., along the X direction) than the global digital line structure 136 with which it is operatively associated, the sensing function can be implemented in a shorter time period compared to the sensing function promoted by conventional microelectronic device structure configurations. In addition, since the parasitic capacitance associated with the local digital line structure 128 is smaller than the parasitic capacitance associated with the global digital line structure 136, the read performance (e.g., sensing speed) can be maintained or improved compared to the conventional read performance promoted by conventional microelectronic device structures, even if the read cell current (I) is not flowing. cell The same applies to relatively small ones.

[0074] In an additional embodiment, the microelectronic device structure 100 may be configured to have the same characteristics as the previously referenced... Figures 1A to 1C The described configurations differ. The microelectronic device structure 100 may, for example, be formed to exhibit a shielded digital line configuration, wherein (e.g., along the Y direction) horizontally adjacent local digital line structures and global digital line structures are operatively associated with different read electrodes and different write electrodes. The shielded digital line configuration may, for example, mitigate unwanted parasitic capacitances between horizontally adjacent digital line structures (e.g., horizontally adjacent local digital line structures, horizontally adjacent global digital line structures) during read operations. By means of non-limiting examples, Figure 2A This is a simplified, partial schematic perspective view of a microelectronic device structure 200 of a microelectronic device (e.g., a memory device, such as a NAND flash memory device) according to additional embodiments of the present disclosure. Figure 2B yes Figure 2AThe diagram shows a schematic representation of the circuit system of a segment of the microelectronic device structure 200. In conjunction with the description provided below, it will be readily apparent to those skilled in the art that the structures and devices described herein can be incorporated into relatively large structures, devices, and systems.

[0075] Through Figure 2A and 2B Features that are functionally similar to those previously described (e.g., materials, structures, devices) are referred to by similar reference numerals incremented by 100. To avoid repetition, they will not be described in detail herein. Figure 2A and 2B All features shown herein. Conversely, unless otherwise described below, in Figure 2A and 2B One or more of them, from the previous reference Figures 1A to 1C The reference numerals of one or more described features incremented by 100 to denote features that are substantially similar to the previously described features. As a non-limiting example, unless otherwise described below, in Figure 2A and 2B In the figures, the features indicated by reference numerals 236A and 236B will be understood to be substantially similar to those previously referenced herein. Figures 1A to 1C The first global digital line structure 136A and the second global digital line structure 136B are described. As another non-limiting example, unless otherwise described below, [the following is a list of examples]. Figure 2A and 2B In the figures, the features indicated by reference numerals 228A and 228B will be understood to be substantially similar to those previously referenced herein. Figures 1A to 1C The first local digital line structure 128A and the second local digital line structure 128B are described.

[0076] Furthermore, unless otherwise described below, it should be understood that features indicated by alphanumeric reference numerals (e.g., reference numerals containing a combination of alphanumeric characters) are considered part of a relatively large group of functionally similar features commonly identified by reference numerals that contain only the numerical portion of the alphanumeric reference numerals. As a non-limiting example, unless otherwise described below, in Figure 2A and 2B In the figure, the feature indicated by the alphanumeric reference numeral 260A is considered as one sensing transistor 260 (e.g., the first sensing transistor) in a relatively large group of sensing transistors 260, wherein such sensing transistors 260 are functionally similar to those previously referenced herein. Figures 1A to 1C The described sensing transistor 160. As another non-limiting example, unless otherwise described below, in Figure 2A and 2BIn the figure, the feature indicated by alphanumeric reference numeral 260B is considered as another sensing transistor 260 (e.g., a second sensing transistor) in a relatively large group of sensing transistors 260, such sensing transistors being functionally similar to those previously referenced herein. Figures 1A to 1C The described sensing transistor 160.

[0077] In addition, unless otherwise described below, previous references Figures 1A to 1C The features of the microelectronic device structure 100 described herein may also be included in substantially the same manner (e.g., to show substantially similar configurations and positioning) as referenced herein. Figures 2A to 2B The microelectronic device structure described is within 200. For clarity and ease of understanding of the diagrams and related descriptions, it is not explicitly shown. Figures 2A to 2B All components (e.g., features, structures, devices) of the microelectronic device structure 200 depicted in one of the figures are... Figure 2A and 2B It is depicted in another figure in the book.

[0078] like Figure 2AAs shown, the microelectronic device structure 200 can be formed to exhibit a shielded digital line configuration, wherein local digital line structures 228 (e.g., first local digital line structure 228A, second local digital line structure 228B) that are horizontally adjacent to each other along the Y direction are operatively associated with each other’s different read electrodes 240 and each other’s different write electrodes 242. Global digital line structures 236 (e.g., first global digital line structure 236A, second global digital line structure 236B) that are operatively associated with the local digital line structures 228 and additional features of the microelectronic device structure 200 (described in further detail below) are also operatively associated with the respective read electrodes and the respective write electrodes. The microelectronic device structure 200 may include: several pairs of read electrodes 240 (e.g., first read electrode 240A, second read electrode 240B) extending horizontally adjacent to each other along the X direction and parallel to each other along the Y direction; and several pairs of write electrodes 242 (e.g., first write electrode 242A, second write electrode 242B) extending horizontally adjacent to each other along the X direction and parallel to each other along the Y direction. The pairs of read electrodes 240 are horizontally offset from the pairs of write electrodes 242 along the X direction (e.g., they may alternate horizontally with the pairs of write electrodes). For a single pair of read electrodes 240, one of the read electrodes 240 (e.g., the first read electrode 240A) may be operatively associated with a local digital line structure 228 (e.g., the first local digital line structure 228A), and the other of the read electrodes 240 (e.g., the second read electrode 240B) may be operatively associated with an additional local digital line structure 228 (e.g., the second local digital line structure 228B) horizontally adjacent to the local digital line structure 228 (e.g., the first local digital line structure 228A). Additionally, for a single pair of write electrodes 242 horizontally adjacent to the pair of read electrodes 240, one of the write electrodes 242 (e.g., the first write electrode 242A) may be operatively associated with a local digital line structure 228 (e.g., the first local digital line structure 228A), and the other of the read electrodes 240 (e.g., the second write electrode 242B) may be operatively associated with an additional local digital line structure 228 (e.g., the second local digital line structure 228B).

[0079] In some embodiments, the so-called "odd" local digital line structure 228 and the so-called "odd" global digital line structure 236 are operatively associated with different read electrodes 240 and different write electrodes 242 of the so-called "even" local digital line structures 228 and the so-called "even" global digital line structures 236 that are horizontally adjacent to the "odd" local digital line structures 228 and the "odd" global digital line structures 236 in the same (e.g., along the Y direction) direction. As a non-limiting example, a first local digital line structure 228A may be considered an "odd" local digital line structure 228, and a first global digital line structure 236A operatively associated with the first local digital line structure 228A may be considered an "odd" global digital line structure 236; and a second local digital line structure 228B may be considered an "even" local digital line structure 228, and a second global digital line structure 236B operatively associated with the second local digital line structure 228B may be considered an "even" global digital line structure 236. Figure 2A As shown, both the first local digital line structure 228A and the first global digital line structure 236A are operatively associated with the first read electrode 240A and the first write electrode 242A; and both the second local digital line structure 228B and the second global digital line structure 236B are operatively associated with the second read electrode 240B horizontally adjacent to the first read electrode 240A and the second write electrode 242B horizontally adjacent to the first write electrode 242A. Furthermore, additional features of the microelectronic device structure 200 operatively associated with the first local digital line structure 228A and the first global digital line structure 236A may be operatively associated with the first read electrode 240A and the first write electrode 242A (e.g., as previously referenced herein). Figures 1A to 1C (as described in one or more of the above); and additional features of the microelectronic device structure 200 operatively associated with the second local digital line structure 228B and the second global digital line structure 236B may be operatively associated with the second read electrode 240B and the second write electrode 242B (e.g., as previously referenced herein). Figures 1A to 1C (as described in one or more of the above). By means of non-limiting examples, the first source line structure 246A, the first read transistor 258A, the first sense transistor 260A, and the first write transistor 262A may be operatively associated with the first read electrode 240A and the first write electrode 242A (e.g., as previously referenced herein). Figures 1A to 1C (as described in one or more of the above); and the second source line structure 246B, the second read transistor 258B, the second sense transistor 260B, and the second write transistor 262B may be operatively associated with the second read electrode 240B and the second write electrode 242B (e.g., as previously referenced herein). Figures 1A to 1C (The way in which one or more are described).

[0080] refer to Figure 2B The microelectronic device structure 200 may be configured to include multiple (e.g., more than one, many) additional select gate layers 216 (e.g., upper select gate layers), such as a first additional select gate layer 216A and a second additional select gate layer 216B vertically overlying the first additional select gate layer 216A. The multiple additional select gate layers 216 may partially define (e.g., as previously referenced herein) Figures 1A to 1C (as described in one or more of the above) A plurality of additional selection transistors 224 are operatively associated with individual vertically extending memory cell strings 220 of the microelectronic device structure 200. For example, for individual vertically extending memory cell strings 120, a first additional selection transistor 224A and a second additional selection transistor 224B may be coupled in series with the vertically extending memory cell string 120. During a read operation of the microelectronic device including the microelectronic device structure 200, the states (e.g., on, off; active, inactive; enhanced, depleted; selected, deselected) of a first additional selection transistor 224A and a second additional selection transistor 224B operably associated with the same local digital line structure 228 (e.g., first local digital line structure 228A) and coupled in series, are controllable relative to the states (e.g., on, off; active, inactive; enhanced, depleted; selected, deselected) of another vertically extending memory cell string 220 operably associated with the same local digital line structure 228 (e.g., second local digital line structure 228B). For example, a first additional selection transistor 224A and a second additional selection transistor 224B, which are operatively associated with the first local digital line structure 228A and connected in series to individual vertically extending memory cell strings 220, may be provided in an off state (e.g., inactive state, depleted state, deselected state) and an on state (e.g., active state, enhanced state, selected state), respectively. Conversely, a first additional selection transistor 224A and a second additional selection transistor 224B, which are operatively associated with the second local digital line structure 228B and connected in series to another individual vertically extending memory cell string 220, may be provided in an on state and an off state, respectively; or vice versa.

[0081] Therefore, a microelectronic device according to embodiments of the present disclosure includes a local digital line structure, a global digital line structure, a source line structure, a sensing transistor, a readout transistor, and a write transistor. The local digital line structure is coupled to a memory cell string. The global digital line structure overlays the local digital line structure. The source line structure is inserted between the local digital line structure and the global digital line structure. The sensing transistor is inserted between the source line structure and the global digital line structure and coupled to both the local digital line structure and the source line structure. The readout transistor is inserted between the sensing transistor and the global digital line structure and coupled to both. The write transistor is inserted between the global digital line structure and the local digital line structure and coupled to both.

[0082] Furthermore, a microelectronic device according to an additional embodiment of this disclosure includes a stacked structure, a local digital line hierarchy, a global digital line hierarchy, a source line hierarchy, a read / write electrode hierarchy, a layout hierarchy, a first pillar structure, and a second pillar structure. The stacked structure includes conductive structures and insulating structures vertically intersecting the conductive structures. The local digital line hierarchy vertically overlies the stacked structure and includes local digital line structures coupled to a string of memory cells extending vertically through the stacked structure. The global digital line hierarchy vertically overlies the local digital line hierarchy and includes global digital line structures. The source line hierarchy is vertically inserted between the local digital line hierarchy and the global digital line hierarchy and includes source line structures. The read / write electrode hierarchy is vertically inserted between the source line hierarchy and the global digital line hierarchy and includes read electrode structures and write electrode structures. The layout hierarchy is vertically inserted between the source line hierarchy and the read / write electrode hierarchy and includes layout structures coupled to the local digital line structures. The first pillar structure comprises a semiconductor material. The first pillar structure extends vertically from the global digital line structure, through the read electrode structure and the layout structure, and at least reaches the source line structure. The second pillar structure includes additional semiconductor material. The second pillar structure extends vertically from the global digital line structure, through the write electrode structure, and at least reaches the local digital line structure.

[0083] Furthermore, the memory device according to embodiments of this disclosure includes a source plate, a stacked structure, local digital lines, memory cell strings, global digital lines, sensing transistors, read transistors, and write transistors. The stacked structure is overlaid on the source plate and includes: an access line region including local access line structures; a select gate region underlying the access line region and including a source-side select gate (SGS) structure; and an additional select gate region overlaid on the access line region and including a drain-side select gate (SGD) structure. The local digital lines are overlaid on the stacked structure. The memory cell strings extend through the stacked structure and are electrically connected to the source plate and the local digital lines. The global digital lines are overlaid on the local digital lines and are electrically connected to a page buffer circuit system. The horizontal dimension of the global digital lines is larger than the horizontal dimension of the local digital lines. The sensing transistor is overlaid on the local digital lines and is electrically connected to the local digital lines. The read transistor is overlaid on the sensing transistor and is electrically connected to the sensing transistor and the global digital lines. The write transistor is overlaid on the local digital line and is electrically connected to both the local digital line and the global digital line.

[0084] The microelectronic device structures (e.g., microelectronic device structure 100, microelectronic device structure 200) and microelectronic devices according to embodiments of the present disclosure can be used in embodiments of the electronic systems of the present disclosure. For example, Figure 3 This is a schematic block diagram of an illustrative electronic system 300 according to embodiments of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, or a tablet computer (e.g., an iPad) that supports Wi-Fi or cellular functionality. or SURFACE Tablet computers, e-books, navigation devices, etc. Electronic system 300 includes at least one memory device 302. Memory device 302 may include, for example, one or more microelectronic device structures (e.g., microelectronic device structure 100, microelectronic device structure 200) and microelectronic devices previously described herein. Electronic system 300 may further include at least one electronic signal processor device 304 (generally referred to as a “microprocessor”). Electronic signal processor device 304 may optionally include one or more microelectronic device structures (e.g., microelectronic device structure 100, microelectronic device structure 200) and microelectronic devices previously described herein. Although memory device 302 and electronic signal processor device 304 are depicted as... Figure 3The electronic system 300 may contain two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device with the functionality of memory device 302 and electronic signal processor device 304 may be included in the electronic system 300. In such embodiments, the memory / processor device may include one or more of the microelectronic device architectures (e.g., microelectronic device architecture 100, microelectronic device architecture 200) and microelectronic devices previously described herein. The electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g., visual or audio output) to a user, such as one or more of a monitor, display, printer, audio output jack, and speaker. In some embodiments, the input device 306 and the output device 308 may include a single touchscreen device available for inputting information into the electronic system 300 and outputting visual information to a user. The input device 306 and the output device 308 can communicate electrically with one or more of the memory device 302 and the electronic signal processor device 304.

[0085] Therefore, an electronic system according to embodiments of the present disclosure includes: an input device; an output device; a processor device operably connected to the input device and the output device; and a memory device operably connected to the processor device. The memory device includes a memory cell string, a source plate, local digital lines, global digital lines, a source line, a first vertical transistor, a second vertical transistor, and a third vertical transistor. The memory cell string extends vertically through a stacked structure comprising a conductive material alternating vertically with an insulating material. The source plate lies vertically beneath the stacked structure and is electrically connected to the memory cell string. The local digital lines vertically overlap the stacked structure and are electrically connected to the memory cell string. The global digital lines vertically overlap the local digital lines and have a greater horizontal length than the local digital lines. The source line is vertically positioned between the local digital lines and the global digital lines. The first vertical transistor is vertically positioned between the source line and the global digital line. The first vertical transistor is electrically connected to the local digital lines and the source line. The second vertical transistor is vertically positioned between the first vertical transistor and the global digital line and is electrically connected to both the first vertical transistor and the global digital line. The third vertical transistor is vertically positioned between the global digital line and the local digital line and is electrically connected to both the global digital line and the local digital line.

[0086] Compared to conventional structures, devices, and methods, the structures and devices of this disclosure advantageously facilitate one or more of the following: improved performance of microelectronic devices, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and increased packaging density. Compared to conventional structures and devices, the structures and devices of this disclosure also improve scalability, efficiency, and simplicity.

[0087] Additional non-limiting example embodiments of this disclosure are described below.

[0088] Example 1: A microelectronic device comprising: a local digital line structure coupled to a memory cell string; a global digital line structure overlying the local digital line structure; a source line structure inserted between the local digital line structure and the global digital line structure; a sensing transistor inserted between the source line structure and the global digital line structure, the sensing transistor being coupled to the local digital line structure and the source line structure; a read transistor inserted between the sensing transistor and the global digital line structure and coupled to both the sensing transistor and the global digital line structure; and a write transistor inserted between the global digital line structure and the local digital line structure and coupled to both the global digital line structure and the local digital line structure.

[0089] Example 2: The microelectronic device according to Example 1, wherein the local digital line structure includes: a row of the local digital line structures extending along a first horizontal direction, each of the row of local digital line structures including a group of local digital line structures substantially aligned with each other along a second horizontal direction orthogonal to the first horizontal direction; and a column of the local digital line structures extending along the second horizontal direction, each of the column of local digital line structures including an additional group of local digital line structures substantially aligned with each other along the first horizontal direction.

[0090] Example 3: In the microelectronic device according to Example 2, each of the additional set of local digital line structures of one of the arrayed local digital line structures is operatively associated with a global digital line structure of each other local digital line structure in the additional set of local digital line structures that is different from the arrayed local digital line structures.

[0091] Example 4: A microelectronic device according to Example 3, wherein: each of a set of read transistors operatively associated with an additional set of local digital line structures of one of the arrayed local digital line structures shares a gate electrode with each other read transistor in the set of read transistors; and each of a set of write transistors operatively associated with an additional set of local digital line structures of one of the arrayed local digital line structures shares an additional gate electrode with each other write transistor in the set of write transistors.

[0092] Example 5: A microelectronic device according to Example 3, wherein: at least one read transistor of a set of read transistors operatively associated with an additional set of local digital line structures of one of the arrayed local digital line structures is operatively associated with a gate electrode different from at least one other read transistor of the set of read transistors; and at least one write transistor of a set of write transistors operatively associated with an additional set of local digital line structures of one of the arrayed local digital line structures is operatively associated with an additional gate electrode different from at least one other write transistor of the set of write transistors.

[0093] Example 6: The microelectronic device according to Example 5, wherein: at least one read transistor is adjacent to the at least one other read transistor along the second horizontal direction; and at least one write transistor is adjacent to the at least one other write transistor along the second horizontal direction.

[0094] Example 7: A microelectronic device according to any one of Examples 3 to 6, wherein each local digital line structure in the group of local digital line structures of one of the rows is operatively associated with a global digital line structure that is identical to each other local digital line structure in the group of local digital line structures of one of the rows.

[0095] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the local digital line structure and the global digital line structure each extend along a first horizontal direction, and the horizontal dimension of the local digital line structure along the first horizontal direction is smaller than the horizontal dimension of the global digital line structure along the first horizontal direction.

[0096] Example 9: A microelectronic device according to any one of Examples 1 to 8, wherein: the sensing transistor includes a first vertical transistor vertically inserted between the source line structure and the global digital line structure; the read transistor includes a second vertical transistor vertically inserted between the sensing transistor and the global digital line structure; and the write transistor includes a third vertical transistor vertically inserted between the global digital line structure and the local digital line structure.

[0097] Example 10: The microelectronic device according to Example 9, wherein: the gate structure of the sensing transistor is vertically overlaid on and coupled to the local digital line structure; the source region of the sensing transistor is vertically overlaid on and coupled to the source line structure; and the drain region of the sensing transistor is vertically overlaid on and coupled to the source region of the readout transistor.

[0098] Example 11: A microelectronic device according to any one of Examples 1 to 10, wherein the sensing transistor includes a PMOS transistor.

[0099] Example 12: A microelectronic device according to any one of Examples 1 to 11, wherein the read transistor is located at substantially the same vertical position as the write transistor.

[0100] Example 13: A microelectronic device comprising: a stacked structure including a conductive structure and an insulating structure vertically intersecting the conductive structure; a local digital line hierarchy vertically overlying the stacked structure and including local digital line structures coupled to a string of memory cells extending vertically through the stacked structure; a global digital line hierarchy vertically overlying the local digital line hierarchy and including a global digital line structure; a source line hierarchy vertically inserted between the local digital line hierarchy and the global digital line hierarchy and including a source line structure; and a read / write electrode hierarchy vertically inserted between the source line hierarchy and the global digital line hierarchy. The system comprises: a line layer and a read electrode structure and a write electrode structure; a layout layer vertically inserted between the source line layer and the read / write electrode layer and including a layout structure coupled to the local digital line structure; a first pillar structure comprising semiconductor material, the first pillar structure extending vertically from the global digital line structure, passing through the read electrode structure and the layout structure, and reaching at least the source line structure; and a second pillar structure comprising additional semiconductor material, the second pillar structure extending vertically from the global digital line structure, passing through the write electrode structure, and reaching at least the local digital line structure.

[0101] Example 14: The microelectronic device according to Example 13 further includes: a first vertical transistor located at the intersection of the first pillar structure and the source line structure; a second vertical transistor located at the intersection of the first pillar structure and the read electrode structure; and a third vertical transistor located at the intersection of the second pillar structure and the write electrode structure.

[0102] Example 15: The microelectronic device according to Example 14 further includes a conductive contact structure extending vertically from the layout structure to the local digital line structure.

[0103] Example 16: A microelectronic device according to any one of Examples 13 to 15, wherein: the local digital line structure, the global digital line structure and the layout structure each extend horizontally along a first direction; and the source line structure, the read electrode structure and the write electrode structure each extend horizontally along a second direction orthogonal to the first direction.

[0104] Example 17: A microelectronic device according to any one of Examples 13 to 16, wherein at least one of the local digital line structures has a length along a first horizontal direction that is shorter than the length along the first horizontal direction of at least one of the global digital line structures.

[0105] Example 18: A microelectronic device according to any of Examples 13 to 17, wherein: the read / write electrode layer includes a pair of read electrode structures horizontally adjacent to a pair of write electrode structures along a first direction; and at least one of the local digital line structures is operatively associated with a read electrode structure in the pair of read electrode structures and a write electrode structure in the pair of write electrode structures that is horizontally adjacent to at least one of the local digital line structures along a second direction orthogonal to the first direction.

[0106] Example 19: A microelectronic device according to any of Examples 13 to 18, further comprising a source hierarchy vertically resting on the stacked structure and including a source structure coupled to the memory cell string.

[0107] Example 20: A memory device comprising: a source plate; a stacked structure covering the source plate and including: an access line region including a local access line structure; a select gate region underlying the access line region and including a source-side select gate (SGS) structure; and an additional select gate region covering the access line region and including a drain-side select gate (SGD) structure; local digital lines covering the stacked structure; a memory cell string extending through the stacked structure and electrically connected to the source plate and the local digital lines; a global digital line covering the local digital lines and electrically connected to a page buffer circuit system, the horizontal dimension of the global digital line being larger than the horizontal dimension of the local digital lines; a sensing transistor covering the local digital lines and electrically connected to the local digital lines; a read transistor covering the sensing transistor and electrically connected to the sensing transistor and the global digital lines; and a write transistor covering the local digital lines and electrically connected to the local digital lines and the global digital lines.

[0108] Example 21: The memory device according to Example 20, wherein each of the global digital lines is operatively associated with more than one of the local digital lines.

[0109] Example 22: A memory device according to one of Examples 20 and 21, further comprising a source line overlying the local digital line and electrically connected to the sensing transistor.

[0110] Example 23: A memory device according to any one of Examples 20 to 22, wherein the sensing transistor, the read transistor and the write transistor each comprise a vertical metal-oxide-semiconductor (MOS) transistor.

[0111] Example 24: A memory device according to any one of Examples 20 to 23, wherein: at least one of the read transistors operatively associated with a column of local digital lines is electrically connected to a gate electrode different from at least one of the other read transistors operatively associated with the column of local digital lines; and at least one of the write transistors operatively associated with the column of local digital lines is electrically connected to an additional gate electrode different from at least one of the other write transistors operatively associated with the column of local digital lines.

[0112] Example 25: A memory device according to any one of Examples 20 to 24, wherein each local digital line in a column of local digital lines is electrically connected to a global digital line in the global digital lines that is different from each other local digital line in the column of local digital lines.

[0113] Example 26: An electronic system comprising: an input device; an output device; a processor device operably connected to the input device and the output device; and a memory device operably connected to the processor device and comprising: a string of memory cells extending vertically through a stacked structure, the stacked structure comprising a conductive material alternating vertically with an insulating material; a source plate vertically resting on the stacked structure and electrically connected to the string of memory cells; a local digital line vertically covering the stacked structure and electrically connected to the string of memory cells; and a global digital line vertically covering the local digital line and having It has a horizontal length greater than the local digital line; a source line that is vertically positioned between the local digital line and the global digital line; a first vertical transistor that is vertically positioned between the source line and the global digital line, the first vertical transistor being electrically connected to both the local digital line and the source line; a second vertical transistor that is vertically positioned between the first vertical transistor and the global digital line and is electrically connected to both the first vertical transistor and the global digital line; and a third vertical transistor that is vertically positioned between the global digital line and the local digital line and is electrically connected to both the global digital line and the local digital line.

[0114] Example 27: The electronic system according to Example 26, wherein the memory device includes a 3D NAND flash memory device.

[0115] While various modifications and alternatives are permissible with respect to this disclosure, specific embodiments have been shown by way of example in the accompanying drawings and described in detail herein. However, this disclosure is not limited to the particular forms disclosed. In fact, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of this disclosure.

Claims

1. A microelectronic device comprising: Local digital line structures coupled to memory cell strings; A global digital line structure that overlays the local digital line structure; A source line structure inserted between the local digital line structure and the global digital line structure; A sensing transistor is inserted between the source line structure and the global digital line structure, and the sensing transistor is coupled to the local digital line structure and the source line structure; A readout transistor inserted between the sensing transistor and the global digital line structure and coupled to both the sensing transistor and the global digital line structure; as well as A write transistor inserted between the global digital line structure and the local digital line structure and coupled to both the global digital line structure and the local digital line structure.

2. The microelectronic device according to claim 1, wherein the local digital line structure comprises: The rows of local digital line structures extending along a first horizontal direction, each of the rows of local digital line structures comprising a set of local digital line structures generally aligned with each other along a second horizontal direction orthogonal to the first horizontal direction. as well as The array of local digital line structures extending along the second horizontal direction, each of the array of local digital line structures including an additional set of local digital line structures generally aligned with each other along the first horizontal direction.

3. The microelectronic device of claim 2, wherein each of the additional set of local digital line structures of one of the arrayed local digital line structures is operatively associated with a global digital line structure of the global digital line structure that is different from each of the other local digital line structures in the additional set of local digital line structures of one of the arrayed local digital line structures.

4. The microelectronic device according to claim 3, wherein: Each read transistor in a set of read transistors operably associated with an additional set of local digital line structures of one of the arrayed local digital line structures shares a gate electrode with each other read transistor in that set of read transistors; and Each write transistor in a set of write transistors operatively associated with an additional set of local digital line structures of one of the arrayed local digital line structures shares an additional gate electrode with each other write transistor in the same set of write transistors.

5. The microelectronic device according to claim 3, wherein: At least one read transistor in a set of read transistors operatively associated with an additional set of local digital line structures operatively associated with one of the arrayed local digital line structures is operatively associated with a gate electrode different from at least one other read transistor in the same set of read transistors; and At least one write transistor in a set of write transistors operatively associated with an additional set of local digital line structures operatively associated with one of the arrayed local digital line structures is operatively associated with an additional gate electrode different from at least one other write transistor in the set of write transistors.

6. The microelectronic device according to claim 5, wherein: At least one read transistor is adjacent to the at least one other read transistor along the second horizontal direction; and At least one write transistor is adjacent to the at least one other write transistor along the second horizontal direction.

7. The microelectronic device of claim 3, wherein each of the group of local digital line structures of one of the arranged local digital line structures is operatively associated with a global digital line structure that is identical to each other local digital line structure of the group of local digital line structures of one of the arranged local digital line structures.

8. The microelectronic device according to any one of claims 1 to 7, wherein the local digital line structure and the global digital line structure each extend along a first horizontal direction, and the horizontal dimension of the local digital line structure along the first horizontal direction is smaller than the horizontal dimension of the global digital line structure along the first horizontal direction.

9. The microelectronic device according to any one of claims 1 to 7, wherein: The sensing transistor includes a first vertical transistor that is vertically inserted between the source line structure and the global digital line structure; The readout transistor includes a second vertical transistor vertically inserted between the sensing transistor and the global digital line structure; and The write transistor includes a third vertical transistor that is vertically inserted between the global digital line structure and the local digital line structure.

10. The microelectronic device according to claim 9, wherein: The gate structure of the sensing transistor is vertically superimposed on and coupled to the local digital line structure; The source region of the sensing transistor is vertically superimposed on and coupled to the source line structure; and The drain region of the sensing transistor lies vertically beneath and is coupled to the source region of the read transistor.

11. The microelectronic device according to any one of claims 1 to 7, wherein the sensing transistor comprises a PMOS transistor.

12. The microelectronic device according to any one of claims 1 to 7, wherein the read transistor is located at substantially the same vertical position as the write transistor.

13. A microelectronic device comprising: A stacked structure comprising a conductive structure and an insulating structure vertically intersecting the conductive structure; A local digital line hierarchy, which vertically overlies the stacked structure and includes a local digital line structure coupled to a string of memory cells that extends vertically through the stacked structure; A global digital line hierarchy that vertically overlies the local digital line hierarchy and includes the global digital line structure; A source line hierarchy, which is vertically inserted between the local digital line hierarchy and the global digital line hierarchy and includes a source line structure; A read / write electrode layer, which is vertically inserted between the source line layer and the global digital line layer, includes a read electrode structure and a write electrode structure; A layout layer that is vertically inserted between the source line layer and the read / write electrode layer and includes a layout structure coupled to the local digital line structure; A first pillar structure comprising semiconductor material extends vertically from the global digital line structure, through the read electrode structure and the layout structure, and at least reaches the source line structure; as well as The second pillar structure includes additional semiconductor material and extends vertically from the global digital line structure, through the write electrode structure, and at least to the local digital line structure.

14. The microelectronic device of claim 13, further comprising: A first vertical transistor located at the intersection of the first pillar structure and the source line structure; A second vertical transistor located at the intersection of the first pillar structure and the read electrode structure; as well as The third vertical transistor is located at the intersection of the second pillar structure and the write electrode structure.

15. The microelectronic device of claim 14, further comprising a conductive contact structure extending vertically from the layout structure to the local digital line structure.

16. The microelectronic device according to any one of claims 13 to 15, wherein: The local digital line structure, the global digital line structure, and the deployment structure each extend horizontally along a first direction; and The source line structure, the read electrode structure, and the write electrode structure each extend horizontally along a second direction orthogonal to the first direction.

17. The microelectronic device according to any one of claims 13 to 15, wherein at least one of the local digital line structures has a length along a first horizontal direction that is shorter than the length along the first horizontal direction of at least one of the global digital line structures.

18. The microelectronic device according to any one of claims 13 to 15, wherein: The read / write electrode layer includes a pair of read electrode structures horizontally adjacent to a pair of write electrode structures along a first direction; and At least one of the local digital line structures is operatively associated with a read electrode structure in a pair of read electrode structures and a write electrode structure in a pair of write electrode structures that are horizontally adjacent to at least one of the local digital line structures along a second direction orthogonal to the first direction.

19. The microelectronic device according to any one of claims 13 to 15, further comprising a source hierarchy vertically resting on the stacked structure and including a source structure coupled to the memory cell string.

20. A memory device comprising: Source plate; A stacked structure, which covers the source plate and includes: Access line region, which includes local access line structure; Select gate region, which lies beneath the access line region and includes a source-side select gate (SGS) structure; and An additional select gate region, which overlays the access line region and includes a drain-side select gate (SGD) structure; Local digital lines, which are overlaid on the stacked structure; A string of memory cells extends through the stacked structure and is electrically connected to the source plate and the local digital line; A global digital line, which covers the local digital line and is electrically connected to the page buffer circuit system, wherein the horizontal dimension of the global digital line is larger than the horizontal dimension of the local digital line; A sensing transistor, which is overlaid on and electrically connected to the local digital line; A readout transistor, which overlays the sensing transistor and is electrically connected to the sensing transistor and the global digital line; and A write transistor is overlaid on the local digital line and electrically connected to both the local digital line and the global digital line.

21. The memory device of claim 20, wherein each of the global digital lines is operatively associated with more than one of the local digital lines.

22. The memory device of claim 20, further comprising a source line covering the local digital line and electrically connected to the sensing transistor.

23. The memory device according to any one of claims 20 to 22, wherein the sensing transistor, the read transistor, and the write transistor each comprise a vertical metal-oxide-semiconductor (MOS) transistor.

24. The memory device according to any one of claims 20 to 22, wherein: At least one of the read transistors operatively associated with a column of said local digital lines is electrically connected to the gate electrode of a read transistor that is different from at least one of the other read transistors operatively associated with said column of said local digital lines; and At least one of the write transistors operatively associated with the column of local digital lines is electrically connected to an additional gate electrode different from at least one of the other write transistors operatively associated with the column of local digital lines.

25. The memory device of claim 24, wherein each local digital line in the column of local digital lines is electrically connected to a global digital line in the global digital lines that is different from each other local digital line in the column of local digital lines.

26. An electronic system comprising: Input device; Output device; A processor device operatively connected to the input device and the output device; as well as A memory device operatively connected to the processor device and comprising: A string of memory cells extends vertically through a stacked structure comprising conductive material alternating vertically with insulating material; The source plate lies vertically beneath the stacked structure and is electrically connected in series with the memory cell; Local digital lines, which vertically cover the stacked structure and are electrically connected in series with the memory cells; A global digital line that vertically overlaps the local digital line and has a greater horizontal length than the local digital line; The source line is vertically positioned between the local digital line and the global digital line; A first vertical transistor is vertically positioned between the source line and the global digital line, and the first vertical transistor is electrically connected to the local digital line and the source line; A second vertical transistor is vertically positioned between the first vertical transistor and the global digital line and is electrically connected to both the first vertical transistor and the global digital line; and A third vertical transistor is vertically positioned between the global digital line and the local digital line and is electrically connected to both the global digital line and the local digital line.

27. The electronic system of claim 26, wherein the memory device comprises a 3D NAND flash memory device.

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