Display substrate and its preparation method, display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a substrate, a first electrode layer disposed on one side of the substrate, the first electrode layer comprising a first electrode pattern; a first planar layer disposed on the side of the first electrode layer away from the substrate, the first planar layer comprising a through hole penetrating through the first planar layer to expose the first electrode pattern; and a second electrode layer, a second planar layer and a third electrode layer stacked on the side of the first planar layer away from the substrate, wherein the second electrode layer is disposed close to the substrate, the orthographic projection of the second electrode layer on the substrate covers the orthographic projection of the through hole on the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer, and the second planar layer fills in the through hole to planarize the through hole. The technical scheme of the present disclosure can improve the pixel aperture ratio of the display area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Currently, liquid crystal displays (LCDs) remain the mainstream display technology. The display panel in an LCD typically includes an array substrate, a cell substrate, and liquid crystal filling the space between the array substrate and the cell substrate. However, as the pixel density of display panels increases, the size of individual pixel units is becoming smaller and smaller, and achieving increasingly lower pixel aperture ratios is a problem that urgently needs to be solved in this field. Summary of the Invention

[0003] This disclosure provides a display substrate and its fabrication method, as well as a display device, to improve pixel aperture ratio.

[0004] This disclosure provides a display substrate, the display substrate comprising:

[0005] A substrate, and a first electrode layer disposed on one side of the substrate, the first electrode layer including a first electrode pattern;

[0006] A first planarization layer is disposed on the side of the first electrode layer opposite to the substrate. A through-hole is disposed on the first planarization layer, and the through-hole penetrates the first planarization layer to expose the first electrode pattern.

[0007] A second electrode layer, a second planarization layer, and a third electrode layer are stacked on the side of the first planarization layer opposite to the substrate. The second electrode layer is disposed close to the substrate. The orthogonal projection of the second electrode layer on the substrate covers the orthogonal projection of the via on the substrate. The second electrode layer connects the first electrode pattern and the third electrode layer. The second planarization layer fills the via to planarize the via.

[0008] In one alternative implementation, the orthographic projection of the via on the substrate falls entirely within the orthographic projection of the second electrode layer on the substrate.

[0009] In one alternative implementation, the orthographic projection of the second electrode layer onto the substrate falls entirely within the orthographic projection of the third electrode layer onto the substrate.

[0010] In one alternative implementation, the orthographic projection of the second planarization layer onto the substrate falls entirely within the orthographic projection of the third electrode layer onto the substrate.

[0011] In one alternative implementation, the via and the second electrode layer are rectangular, circular, or elliptical in shape.

[0012] In one optional implementation, the display substrate includes a display area and a non-display area, wherein the display area includes an opening area and a non-opening area;

[0013] The display substrate further includes: a first thin-film transistor disposed between the substrate and the first electrode layer, the first thin-film transistor being located in the display area, the first thin-film transistor including a first active layer, a first gate insulating layer and a first gate layer stacked together, the first active layer including a drain contact region;

[0014] The first electrode layer further includes a second electrode pattern integrally formed with the first electrode pattern, the second electrode pattern being connected to the drain contact region, and the first electrode pattern being located in the non-opening region.

[0015] In one alternative implementation, the first active layer is disposed close to the substrate, and a first interlayer dielectric layer, a first source, and a first passivation layer are stacked on the side of the first gate facing away from the substrate. The first electrode layer is disposed on the side of the first passivation layer facing away from the substrate, and the second electrode pattern is connected to the drain contact area through vias disposed on the first passivation layer, the first interlayer dielectric layer, and the first gate insulating layer.

[0016] In one alternative implementation, the material of the first electrode layer is a transparent conductive material.

[0017] In one alternative implementation, the drain contact region is located in the non-opening region, and the material of the first electrode layer is metal.

[0018] In one alternative implementation, the drain contact region is located in the non-opening region, and the orthogonal projections of the first gate insulating layer, the first interlayer dielectric layer, and the first passivation layer on the substrate do not overlap with the opening region.

[0019] In one optional implementation, the first active layer is disposed close to the substrate, and a first interlayer dielectric layer and a first source / drain electrode layer are stacked on the side of the first gate away from the substrate. The first source / drain electrode layer includes a first source and a first drain disposed on the same layer. The first drain and the drain contact area are connected through vias disposed on the first interlayer dielectric layer and the first gate insulating layer. The first electrode layer is disposed on the side of the first drain away from the substrate, and the second electrode pattern is in contact with the first drain.

[0020] In one alternative implementation, the drain contact area is located in the non-opening region, and the material of the first drain is metal.

[0021] In one optional implementation, the display substrate includes a display area and a non-display area, wherein the display area includes an opening area and a non-opening area;

[0022] The display substrate further includes: a first thin-film transistor disposed on the side of the substrate near the first electrode layer, the first thin-film transistor being located in the display area, the first thin-film transistor including a first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer and a first source layer stacked together, the first active layer being disposed near the substrate, the first active layer including a drain contact region, the drain contact region being located in the opening region;

[0023] The orthographic projections of the first gate insulating layer and the first interlayer dielectric layer onto the substrate do not overlap with the opening region; the drain contact region is the first electrode pattern.

[0024] In one alternative implementation, the material of the first active layer includes a metal oxide.

[0025] In one alternative implementation, the display area further includes data lines and scan lines, wherein the first source extends along a first direction to form the data lines, and the first gate extends along a second direction intersecting the first direction to form the scan lines, wherein the orthogonal projections of the data lines and the scan lines on the substrate respectively cover the orthogonal projection of the channel region of the first active layer on the substrate.

[0026] In one alternative implementation, the material of the first active layer comprises polycrystalline silicon, and the orthographic projection of the data line onto the substrate overlaps the orthographic projection of the first active layer onto the substrate.

[0027] In one alternative implementation, a shielding layer and a second interlayer dielectric layer are further stacked between the first active layer and the substrate. The shielding layer is disposed close to the substrate, and the orthographic projection of the shielding layer on the substrate covers the orthographic projection of the channel region of the first active layer on the substrate.

[0028] In one alternative implementation, the display area further includes data lines and scan lines, and the orthographic projection of the shielding layer on the substrate covers the orthographic projection of the data lines and the scan lines on the substrate.

[0029] In one alternative implementation, the shielding layer is connected to a fixed potential input.

[0030] In one alternative implementation, the shielding layer is connected to the first source electrode via vias disposed on the second interlayer dielectric layer, the first gate insulating layer, and the first interlayer dielectric layer.

[0031] In one alternative implementation, the material of the shielding layer includes at least one of the following: molybdenum, aluminum, and silver.

[0032] In one alternative implementation, the display substrate further includes a second thin-film transistor located in the non-display area, wherein the active layer material of the second thin-film transistor comprises polycrystalline silicon.

[0033] In one optional implementation, the channel region of the first active layer includes a first channel region, a first resistance region, and a second channel region arranged sequentially along a first direction. The first gate includes a first sub-gate and a second sub-gate disposed separately. The orthogonal projection of the first sub-gate on the substrate covers the orthogonal projection of the first channel region on the substrate, and the orthogonal projection of the second sub-gate on the substrate covers the orthogonal projection of the second channel region on the substrate.

[0034] In one alternative implementation, a second passivation layer and a fourth electrode layer are stacked on the side of the first electrode layer facing away from the substrate. The fourth electrode layer is transparent and connected to a first fixed potential input terminal. The second passivation layer is disposed close to the substrate. The orthographic projections of the first electrode layer and the fourth electrode layer on the substrate overlap.

[0035] The first planarization layer is disposed on the side of the fourth electrode layer away from the substrate, the via penetrates the second passivation layer, and the via does not overlap with the orthographic projection of the fourth electrode layer on the substrate.

[0036] In one alternative implementation, the display substrate includes an opening region, and a color resist layer is further disposed on the side of the first electrode layer facing away from the substrate, the orthogonal projection of the color resist layer on the substrate covering the opening region.

[0037] The first planarization layer is disposed on the side of the color resist layer away from the substrate, and the orthographic projection of the via on the substrate does not overlap with the orthographic projection of the color resist layer on the substrate.

[0038] In one alternative implementation, a third passivation layer and a common electrode layer are stacked on the side of the third electrode layer facing away from the substrate. The third passivation layer is disposed close to the substrate. The common electrode layer includes a plurality of strip electrodes and is made of metal.

[0039] In one alternative implementation, an isolation pillar is further provided on the side of the first planarization layer facing away from the substrate, and the isolation pillar is formed synchronously with the second planarization layer.

[0040] This disclosure provides a display device including a display substrate as described in any embodiment.

[0041] This disclosure provides a method for preparing a display substrate, the method comprising:

[0042] Provide substrate;

[0043] A first electrode layer is formed on one side of the substrate, the first electrode layer including a first electrode pattern;

[0044] A first planarization layer is sequentially formed on the side of the first electrode layer away from the substrate. A through-hole is provided on the first planarization layer, and the through-hole penetrates the first planarization layer to expose the first electrode pattern.

[0045] A second electrode layer, a second planarization layer, and a third electrode layer are sequentially formed on the side of the first planarization layer away from the substrate, wherein the orthographic projection of the second electrode layer on the substrate covers the orthographic projection of the via on the substrate, the second electrode layer is used to connect the first electrode pattern and the third electrode layer, and the second planarization layer is used to planarize the via.

[0046] Compared with the prior art, this disclosure includes the following advantages:

[0047] This disclosure provides a display substrate and its fabrication method, as well as a display device. The display substrate includes a substrate, a first electrode layer disposed on one side of the substrate, the first electrode layer including a first electrode pattern, a first planarization layer disposed on the side of the first electrode layer facing away from the substrate, the first planarization layer having a through-hole penetrating the first planarization layer to expose the first electrode pattern, and a second electrode layer, a second planarization layer, and a third electrode layer stacked on the side of the first planarization layer facing away from the substrate, wherein the second electrode layer is disposed close to the substrate, the orthographic projection of the second electrode layer on the substrate covers the orthographic projection of the through-hole on the substrate, the second electrode layer connects the first electrode pattern and the third electrode layer, and the second planarization layer fills the through-hole to planarize the through-hole. On one hand, by filling the through-hole on the first planarization layer with the second planarization layer disposed within the through-hole, the deep hole structure on the first planarization layer is eliminated, eliminating light leakage caused by the deep hole structure, thus eliminating the need for a large light-shielding layer to block light leakage, thereby improving the pixel aperture ratio of the display area. On the other hand, since the third electrode layer is set on a flat surface, when the third electrode layer is used as a pixel electrode layer, the distance between the pixel electrode layer and the common electrode layer can be kept consistent, so that the electric field is uniform, the liquid crystal deflection is normal, and light leakage caused by abnormal liquid crystal deflection is avoided. Therefore, there is no need to set a large light-shielding layer to block light leakage, thus improving the pixel aperture ratio of the display area.

[0048] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0050] Figure 1 A cross-sectional structural schematic diagram of a display substrate provided in an embodiment of this disclosure is shown;

[0051] Figure 2 A cross-sectional structural schematic diagram of a display substrate provided in an embodiment of this disclosure is shown;

[0052] Figure 3 A cross-sectional structural schematic diagram of a display substrate provided in an embodiment of this disclosure is shown;

[0053] Figure 4 A schematic diagram of a planar structure of a display substrate provided in an embodiment of this disclosure is shown;

[0054] Figure 5 A schematic diagram of the planar structure of a first thin-film transistor provided in an embodiment of this disclosure is shown;

[0055] Figure 6 A cross-sectional structural schematic diagram of a first thin-film transistor provided in an embodiment of this disclosure is shown;

[0056] Figure 7 A schematic diagram of the planar structure of the shielding layer provided in an embodiment of this disclosure is shown;

[0057] Figure 8 A cross-sectional structural diagram of a display substrate with the second electrode layer fabricated according to an embodiment of this disclosure is shown.

[0058] Figure 9 A cross-sectional structural diagram of a display substrate with a second planar material layer fabricated according to an embodiment of this disclosure is shown.

[0059] Figure 10 A cross-sectional structural diagram of a display substrate with a second planarization layer fabricated according to an embodiment of the present disclosure is shown.

[0060] Figure 11 A cross-sectional structural diagram of a display substrate with the third electrode layer fabricated according to an embodiment of the present disclosure is shown;

[0061] Figure 12 A cross-sectional structural diagram of a display substrate with a third passivation layer fabricated according to an embodiment of this disclosure is shown.

[0062] Figure 13 A cross-sectional structural diagram of a display substrate with a completed common electrode layer provided in an embodiment of this disclosure is shown;

[0063] Figure 14 This illustration shows a planar structure diagram of a display substrate with a first active layer fabricated according to an embodiment of the present disclosure;

[0064] Figure 15 A schematic diagram of the planar structure of a display substrate with the first gate fabrication completed, provided in an embodiment of this disclosure, is shown.

[0065] Figure 16 This illustration shows a schematic diagram of the planar structure of a display substrate with the first interlayer dielectric layer fabricated, provided in an embodiment of this disclosure.

[0066] Figure 17 A schematic diagram of the planar structure of a display substrate with completed data line fabrication provided in an embodiment of this disclosure is shown;

[0067] Figure 18 A schematic diagram of the planar structure of a display substrate with the first electrode layer fabricated according to an embodiment of this disclosure is shown;

[0068] Figure 19 A schematic diagram of the planar structure of a display substrate with a completed color resist layer fabrication provided in an embodiment of this disclosure is shown;

[0069] Figure 20 A schematic diagram of the planar structure of a display substrate with a first planarization layer fabricated according to an embodiment of the present disclosure is shown.

[0070] Figure 21 A schematic diagram of the planar structure of a display substrate with the third electrode layer fabricated according to an embodiment of this disclosure is shown;

[0071] Figure 22 A schematic diagram of the planar structure of a display substrate with a completed common electrode layer provided in an embodiment of this disclosure is shown. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0073] One embodiment of this disclosure provides a display substrate, with reference to... Figures 1 to 3 The display substrate includes: a substrate 11; a first electrode layer 12 disposed on one side of the substrate 11, the first electrode layer 12 including a first electrode pattern 121; and a first planarization layer 13 disposed on the side of the first electrode layer 12 away from the substrate 11, the first planarization layer 13 having a through hole that penetrates the first planarization layer 13 to expose the first electrode pattern 121.

[0074] A second electrode layer 14, a second planarization layer 15, and a third electrode layer 16 are stacked on the side of the first planarization layer 13 away from the substrate 11. The second electrode layer 14 is disposed close to the substrate 11. The orthogonal projection of the second electrode layer 14 on the substrate 11 covers the orthogonal projection of the via on the substrate 11. The second electrode layer 14 connects the first electrode pattern 121 and the third electrode layer 16. The second planarization layer 15 fills the via to planarize the via.

[0075] On the one hand, by filling the through holes on the first flat layer 13 with the second flat layer 15 set inside the through holes, the deep hole structure on the first flat layer 13 is eliminated, and the light leakage caused by the deep hole structure is eliminated. Therefore, there is no need to set a large light-shielding layer to block the light leakage, thus improving the pixel aperture ratio of the display area.

[0076] On the other hand, since the third electrode layer 16 is disposed on a flat surface, when the third electrode layer 16 is used as a pixel electrode layer, the distance between the pixel electrode layer and the common electrode layer can be kept consistent, so that the electric field is uniform, the liquid crystal deflection is normal, and light leakage caused by abnormal liquid crystal deflection is avoided. Therefore, there is no need to set a large light-shielding layer to block light leakage, thus improving the pixel aperture ratio of the display area.

[0077] In addition, by setting the second electrode layer 14 and the third electrode layer 16 respectively, the problem of high contact resistance when only the second electrode layer 14 is set can be solved. The problem of high contact resistance can be solved by adding a third electrode layer 16 on the side of the second planarization layer 15 away from the substrate 11.

[0078] In one optional implementation, the materials of the first electrode layer 12, the second electrode layer 14, and the third electrode layer 16 can be, for example, transparent conductive materials or metallic materials, etc., and this embodiment is not limited in this regard. When the materials of the first electrode layer 12, the second electrode layer 14, and the third electrode layer 16 are all transparent conductive materials, the transmittance of the display area can be further improved. When the materials of the first electrode layer 12 and the second electrode layer 14 are the same, they can be deposited simultaneously and formed using a single patterning process, thereby saving a mask process.

[0079] The transparent conductive material may include at least one of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and graphene oxide.

[0080] In one alternative implementation, the orthographic projection of the via on the first planarization layer 13 onto the substrate 11 falls entirely within the orthographic projection of the second electrode layer 14 onto the substrate 11.

[0081] In one alternative implementation, the orthographic projection of the second electrode layer 14 onto the substrate 11 falls entirely within the orthographic projection of the third electrode layer 16 onto the substrate 11.

[0082] In one alternative implementation, the orthographic projection of the second planarization layer 15 onto the substrate 11 falls entirely within the orthographic projection of the third electrode layer 16 onto the substrate 11.

[0083] In one alternative implementation, the vias on the first planarization layer 13 and the second electrode layer 14 in a plane parallel to the substrate 11 are rectangular, circular, or elliptical in shape, and this embodiment does not limit this.

[0084] In one alternative implementation, refer to Figure 1 and Figure 2 The display substrate includes a display area and a non-display area. The display area includes an open area and a non-open area. The display substrate may also include a first thin-film transistor 17 disposed between a substrate 11 and a first electrode layer 12. The first thin-film transistor 17 is located in the display area and includes a first active layer 171, a first gate insulating layer 172, and a first gate 173 stacked together. The first active layer 171 includes a drain contact area 21. The first electrode layer 12 may also include a second electrode pattern 122 integrally formed with the first electrode pattern 121. The second electrode pattern 122 is connected to the drain contact area 21, and the first electrode pattern 121 is located in the non-open area.

[0085] In this implementation, the first thin-film transistor 17 can be a top-gate structure (e.g., Figures 1 to 2(As shown), it can also be a bottom grid structure, but this embodiment does not limit it.

[0086] The first gate 173 can be a single-gate structure (e.g., Figure 1 As shown), dual-gate structure (as shown) Figure 2 (as shown) or multi-gate structures, etc., but this embodiment does not limit this to.

[0087] The material of the first active layer 171 may include amorphous silicon, polycrystalline silicon, or metal oxide, etc., and this embodiment does not limit it.

[0088] The drain contact region 21 can be formed by conductiveing ​​the material of the first active layer 171. Conductivity can be achieved through processes such as ion doping and plasma treatment.

[0089] To achieve the connection between the second electrode pattern 122 and the drain contact region 21, in one optional implementation, refer to... Figure 1 The first active layer 171 is disposed close to the substrate 11. A first interlayer dielectric layer 18, a first source 19 and a first passivation layer 110 are stacked on the side of the first gate 173 away from the substrate 11. The first electrode layer 12 is disposed on the side of the first passivation layer 110 away from the substrate 11. The second electrode pattern 122 and the drain contact region 21 are connected by vias disposed on the first passivation layer 110, the first interlayer dielectric layer 18 and the first gate insulating layer 172.

[0090] In this implementation, the material of the first electrode layer 12 can be a transparent conductive material, which can improve the transmittance of the display area. When the material of the first electrode layer 12 can be a transparent conductive material, the material of the first active layer 171 can include a metal oxide, which can reduce the contact resistance between the second electrode pattern 122 and the drain contact area 21.

[0091] In this implementation, the material of the first electrode layer 12 can also be a metallic material, and the second electrode pattern 122 and the drain contact region 21 connected to the second electrode pattern 122 can be located in a non-aperture region, further improving the pixel aperture ratio. When the material of the first electrode layer 12 can be a metallic material, the contact resistance between the second electrode pattern 122 and the drain contact region 21 can be reduced.

[0092] In this implementation, refer to Figure 1 The second electrode pattern 122 in the first electrode layer 12 is reused as the drain of the first thin-film transistor and is connected to the drain contact region 21 through a via. By staggering the source and drain of the first thin-film transistor, the spacing between them can be reduced, which helps to improve the resolution of the display substrate.

[0093] To further improve the transmittance of the opening region, the orthogonal projections of the first gate insulating layer 172, the first interlayer dielectric layer 18, and the first passivation layer 110 on the substrate 11 can be non-overlapping with the opening region. By removing the first gate insulating layer 172, the first interlayer dielectric layer 18, and the first passivation layer 110 in the opening region, the film thickness of the opening region can be reduced, the number of film interfaces can be decreased, thereby improving the light transmittance of the opening region.

[0094] To achieve the connection between the second electrode pattern 122 and the drain contact region 21, in another optional implementation, refer to... Figure 2 The first active layer 171 is disposed close to the substrate 11. A first interlayer dielectric layer 18 and a first source / drain electrode layer are stacked on the side of the first gate 173 away from the substrate 11. The first source / drain electrode layer includes a first source 19 and a first drain 111 disposed on the same layer. The first drain 111 and the drain contact region 21 are connected through vias disposed on the first interlayer dielectric layer 18 and the first gate insulating layer 172. The first electrode layer 12 is disposed on the side of the first drain 111 away from the substrate 11. The second electrode pattern 122 is in contact with the first drain 111.

[0095] In this implementation, the first drain 111 is made of metal. The metallic material of the first drain 111 reduces the contact resistance between the first drain 111 and the drain contact region 21. To avoid occupying the open area, the drain contact region 21 and the first drain 111 connected to the drain contact region 21 can be located within a non-open area.

[0096] In this implementation, the first electrode layer 12 acts as a transition layer. The material of the first electrode layer 12 can be a transparent conductive material, which can improve the aperture ratio and transmittance.

[0097] When the first active layer 171 is disposed close to the substrate 11, the first thin film transistor 17 is a top gate structure. Compared with the traditional bottom gate structure, since the first gate 173 does not need to block the backlight, its size can be reduced, thereby reducing the parasitic capacitance formed between the first gate 173 and other film layers and reducing power consumption.

[0098] To further improve the transmittance of the opening region, the orthographic projections of the first gate insulating layer 172 and the first interlayer dielectric layer 18 on the substrate 11 can be non-overlapping with the opening region. By removing the first gate insulating layer 172 and the first interlayer dielectric layer 18 in the opening region, the film thickness of the opening region can be reduced, the number of film interfaces can be decreased, thereby improving the light transmittance of the opening region.

[0099] In one alternative implementation, refer to Figure 3The display substrate includes a display area and a non-display area. The display area includes an opening area and a non-opening area. The display substrate also includes a first thin-film transistor 17 disposed on the side of the substrate 11 near the first electrode layer 12. The first thin-film transistor 17 is located in the display area. The first thin-film transistor 17 includes a first active layer 171, a first gate insulating layer 172, a first gate 173, a first interlayer dielectric layer 18, and a first source 19 stacked together. The first active layer 171 is disposed near the substrate 11. The first active layer 171 includes a drain contact area 21 located in the opening area. The drain contact area 21 is a first electrode pattern 121.

[0100] To improve the transmittance of the opening region, the orthographic projections of the first gate insulating layer 172 and the first interlayer dielectric layer 18 on the substrate 11 can be non-overlapping with the opening region.

[0101] Since the drain contact region is located within the opening region, it can overlap with the first electrode layer located within the opening region without the need for a transition electrode or drain, thus improving the aperture ratio and transmittance of the display area. Furthermore, since the material of the first active layer 171 is a transparent metal oxide, even if the drain contact region 21 of the first active layer 171 is located in the opening region, it will not affect the aperture ratio and transmittance of the display area.

[0102] In one alternative implementation, the display area also includes data lines 41 and scan lines 42, as shown in the figure. Figure 4 The first source electrode 19 extends along a first direction to form a data line 41, and the first gate electrode 173 extends along a second direction intersecting the first direction to form a scan line 42. The orthogonal projections of the data line 41 and the scan line 42 onto the substrate 11 respectively cover the orthogonal projection of the channel region of the first active layer 171 onto the substrate 11. The second direction can be, for example, perpendicular to the first direction, such as... Figure 4 As shown.

[0103] When the material of the first active layer 171 includes polysilicon, the orthographic projection of the data line 41 on the substrate 11 covers the orthographic projection of the first active layer 171 on the substrate 11. Since the first active layer 171 made of polysilicon is opaque, placing the first active layer 171 in the non-aperture region corresponding to the data line 41 can improve the pixel aperture ratio.

[0104] When the first thin-film transistor 17 is a top-gate structure, in order to avoid the backlight irradiating the first active layer 171 and affecting the electrical characteristics of the first thin-film transistor 17, in one optional implementation, refer to Figures 1 to 3A shielding layer 112 and a second interlayer dielectric layer 113 are also stacked between the first active layer 171 and the substrate 11. The shielding layer 112 is disposed close to the substrate 11, and the orthogonal projection of the shielding layer 112 on the substrate 11 covers the orthogonal projection of the channel region of the first active layer 171 on the substrate 11.

[0105] To further improve the transmittance of the opening region, the orthogonal projection of the second interlayer dielectric layer 113 onto the substrate 11 can be non-overlapping with the opening region.

[0106] In one alternative implementation, the orthographic projection of the shielding layer 112 onto the substrate 11 can cover the orthographic projections of the data line 41 and the scan line 42 onto the substrate 11. That is, the shielding layer 126 has a mesh structure. The mesh structure of the shielding layer can increase the area of ​​the shielding layer without affecting the aperture ratio, thereby reflecting more backlight and improving the backlight transmittance.

[0107] In one alternative implementation, the shielding layer 112 is connected to a fixed potential input. This implementation can prevent display anomalies caused by threshold voltage drift of the first thin-film transistor 17, thereby improving display uniformity.

[0108] In one alternative implementation, such as Figure 3 As shown, the shielding layer 112 and the first source 19 are connected by vias disposed on the second interlayer dielectric layer 113, the first gate insulating layer 172 and the first interlayer dielectric layer 18.

[0109] To further improve backlight utilization, the shielding layer 126 can be made of a highly reflective metallic material, which may include at least one of the following: molybdenum, aluminum, silver, and tin. Using a highly reflective shielding layer allows backlight incident on it to be reflected back, and the reflected backlight can be reused, thereby improving backlight transmittance.

[0110] The material of the shielding layer can be, for example, Al / top TIN, Al / top Mo, Al alloy / top TIN, or Al alloy / top Mo. These materials have good high-temperature stability, and their reflectivity remains stable before and after high-temperature annealing.

[0111] In one alternative implementation, the material of the first active layer 171 includes metal oxide, and the display substrate further includes a second thin-film transistor 114 located in the non-display area. The active layer material of the second thin-film transistor 114 includes polysilicon.

[0112] The second thin-film transistor 114 can be formed using a low-temperature polysilicon (LTPS) process to improve the circuit driving capability of the non-display area. The first thin-film transistor 17 can be formed using an indium gallium zinc oxide (IGZO) process, which can reduce leakage current and improve voltage holding rate, thereby enhancing the display effect of the display area.

[0113] In one alternative implementation, refer to Figure 5 and Figure 6 The channel region 22 of the first active layer 171 may include a first channel region 61, a first resistance region 62 and a second channel region 63 arranged sequentially along a first direction. The first gate 173 includes a first sub-gate 64 and a second sub-gate 65 disposed separately. The orthogonal projection of the first sub-gate 64 on the substrate 11 covers the orthogonal projection of the first channel region 61 on the substrate 11, and the orthogonal projection of the second sub-gate 65 on the substrate 11 covers the orthogonal projection of the second channel region 63 on the substrate 11.

[0114] It should be noted that, in order to clearly identify the first active layer 171, Figure 5 The first sub-gate 64 and the second sub-gate 65 are not fully shown.

[0115] Reference Figure 5 and Figure 6 The first channel region 61, the first resistance region 62, and the second channel region 63 are arranged sequentially along the first direction to form an I-type channel. The first channel region 61 and the second channel region 63 can be equivalent to two thin-film transistor switches connected in series, and the first resistance region 62 can be equivalent to a resistor connected in series between the two thin-film transistor switches. The first resistance region 62 can be formed by processes such as ion doping and plasma treatment of the material of the first active layer 171.

[0116] In this embodiment, by setting a first resistance region 62 between the first channel region 61 and the second channel region 63, it is equivalent to connecting a resistor in series between the two thin-film transistor switches. The setting of the resistor can suppress the generation of leakage current, thereby reducing the leakage current of the thin-film transistor and improving the stability of the threshold voltage.

[0117] The first sub-gate 64 is used to receive a signal that controls the first channel region 61 to be turned on or off. The second sub-gate 65 is used to receive a signal that controls the second channel region 63 to be turned on or off. In an optional implementation, the signals received by the first sub-gate 64 and the second sub-gate 65 may be the same, and this embodiment does not limit this.

[0118] In this implementation, because the first thin-film transistor has a dual-gate structure, it exhibits high electrical stability and good voltage retention, thus improving the display effect and reliability of the display substrate. Furthermore, since the channel of the first thin-film transistor is an I-type channel, it occupies a smaller area in the pixel unit of the display substrate, thereby increasing the aperture ratio of the display substrate, especially for display substrates with high pixel density. This display substrate can be applied to virtual reality (VR) display technology, augmented reality (AR) display technology, and other similar applications.

[0119] Reference Figure 5 and Figure 6 The source contact region 20 in the first active layer 171 may include a first conductor region 66 and a second resistance region 67, with the second resistance region 67 located near the first channel region 61. The drain contact region 21 may include a second conductor region 69 and a third resistance region 68, with the third resistance region 68 located near the second channel region 63. By providing the second resistance region 67 and the third resistance region 68, leakage current can be further reduced.

[0120] Reference Figure 2 A second passivation layer 115 and a fourth electrode layer 116 are stacked on the side of the first electrode layer 12 away from the substrate 11. The fourth electrode layer 116 is transparent and connected to the first fixed potential input terminal. The second passivation layer 115 is disposed close to the substrate 11. The orthographic projections of the first electrode layer 12 and the fourth electrode layer 116 on the substrate 11 overlap. A first planarization layer 13 is disposed on the side of the fourth electrode layer 116 away from the substrate 11. A via penetrates the second passivation layer 115. The via does not overlap with the orthographic projection of the fourth electrode layer 116 on the substrate 11.

[0121] The first electrode layer 12 and the fourth electrode layer 116 can extend into the opening region, such as... Figure 2 As shown. Both the first electrode layer 12 and the fourth electrode layer 116 can be made of transparent conductive materials, which can improve the transmittance of the opening region.

[0122] Since the orthographic projections of the first electrode layer 12 and the fourth electrode layer 116 on the substrate 11 overlap, a storage capacitor can be formed, increasing the pixel storage capacitance and ensuring sufficient storage capacitance within a small pixel space. This improves the voltage retention rate and ensures normal display. The voltage on the fourth electrode layer 116 can, for example, be a common voltage.

[0123] Reference Figure 2An insulating layer 121 is also provided on the side of the fourth electrode layer 116 facing away from the substrate 11, and the data line 41 is provided on the side of the insulating layer 121 facing away from the substrate 11. A first planarization layer 13 is provided on the side of the data line 41 facing away from the substrate 11, and a through-hole penetrates the insulating layer 121. The through-hole and the orthographic projection of the data line 41 on the substrate 11 do not overlap.

[0124] By placing the fourth electrode layer 116 between the data line 41 and the first electrode layer 12, coupling capacitance caused by the close proximity of the data line 41 and the first electrode layer 12 can be avoided. Since the fourth electrode layer 116 is connected to a fixed potential, even if the signal on the data line 41 changes at a high frequency, the influence of the signal on the data line 41 on the first electrode layer 12 can be shielded, thereby shielding the influence of the data line 41 on the pixel voltage on the pixel electrode layer, thus enabling normal pixel display.

[0125] Reference Figure 1 The display substrate includes an opening area. A color resist layer 117 is also disposed on the side of the first electrode layer 12 away from the substrate 11. The orthographic projection of the color resist layer 117 on the substrate 11 covers the opening area. A first planarization layer 13 is disposed on the side of the color resist layer 117 away from the substrate 11. The orthographic projection of the via on the substrate 11 does not overlap with the orthographic projection of the color resist layer 117 on the substrate 11.

[0126] In a specific implementation, the first electrode layer 12 and the color resist layer 117 can be sequentially patterned on the side of the first passivation layer 110 away from the substrate 11, and then the first planarization layer 13 can be formed on the side of the color resist layer 117 and the first electrode layer 12 away from the substrate 11.

[0127] The color resist layer 117 may include a red color resist layer, a green color resist layer and a blue color resist layer, with each color resist layer disposed in a different sub-pixel unit to achieve color display.

[0128] In this implementation, by placing the color resist layer on the display substrate, which is located close to the backlight in the display device, crosstalk between adjacent sub-pixel units can be reduced, thus minimizing the impact on the display effect.

[0129] In one alternative implementation, refer to Figures 1 to 3 A third passivation layer 118 and a common electrode layer 119 are stacked on the side of the third electrode layer 16 facing away from the substrate 11, with the third passivation layer 118 disposed close to the substrate 11. The material of the common electrode layer 118 can be a transparent conductive material or a metallic material, and this embodiment does not limit this.

[0130] The common electrode layer 118 may include multiple strip electrodes, which can form a horizontal electric field with the pixel electrode layer 19. The width and spacing of the strip electrodes can be designed according to actual needs, and this embodiment does not limit this. To reduce light crosstalk between adjacent pixels, the material of the common electrode layer 118 can be metal.

[0131] In one alternative implementation, refer to Figure 1 An isolation pillar 120 is also provided on the side of the first planarization layer 13 facing away from the substrate 11. The isolation pillar 120 is formed simultaneously with the second planarization layer 15. The isolation pillar 120 and the second planarization layer 15 are made of the same material and are formed by the same process, which simplifies the process steps and reduces costs.

[0132] Another embodiment of this disclosure also provides a display device, which may include the display substrate described in any embodiment.

[0133] It should be noted that the display device in this embodiment can be any product or component with 2D or 3D display function, such as a display panel, electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator.

[0134] Another embodiment of this disclosure also provides a method for preparing a display substrate, the method comprising:

[0135] Step 11: Provide a substrate;

[0136] Step 12: Form a first electrode layer on one side of the substrate, the first electrode layer including a first electrode pattern;

[0137] Step 13: A first planarization layer is sequentially formed on the side of the first electrode layer away from the substrate. A through-hole is provided on the first planarization layer, and the through-hole penetrates the first planarization layer to expose the first electrode pattern.

[0138] Step 14: A second electrode layer, a second planarization layer and a third electrode layer are sequentially formed on the side of the first planarization layer away from the substrate. The orthogonal projection of the second electrode layer on the substrate covers the orthogonal projection of the via on the bottom. The second electrode layer is used to connect the first electrode pattern and the third electrode layer. The second planarization layer is used to planarize the via.

[0139] The display substrate described in any of the above embodiments can be prepared using the preparation method provided in this embodiment.

[0140] In one optional implementation, the method for fabricating the display substrate provided in this embodiment may include the following steps:

[0141] Step 21: First, the first thin-film transistor 17 and the second thin-film transistor 114 are fabricated on the substrate 11. Then, a first electrode layer 12, a first planarization layer 13, and a second electrode layer 14 are sequentially formed on the side of the first passivation layer 110 away from the substrate 11. The first planarization layer 13 has a via, and the second electrode layer 14 covers the via, forming a structure as shown in the figure. Figure 8 The display substrate shown;

[0142] Step 22: Fabricate a second planar material layer, filling the through-holes in the first planar layer 13 to form a structure as shown in the figure. Figure 9 The display substrate shown;

[0143] Step 23: Pattern the second planarization material layer by controlling the exposure energy in different areas to form the isolation pillars 120 and the second planarization layer 15, respectively, forming a pattern as shown in the figure. Figure 10 The display substrate shown; wherein, the second planarization layer 15 is used to fill the through holes on the first planarization layer 13, and the materials of the second planarization layer 15 and the first planarization layer 13 may be the same or different;

[0144] Step 24: Deposit and pattern ITO to form the third electrode layer, resulting in... Figure 11 The display substrate shown;

[0145] Step 25: Deposit to form the third passivation layer 118, forming as shown in the figure. Figure 12 The display substrate shown;

[0146] Step 26: Patterning to form the common electrode layer 119, forming as shown in the figure. Figure 1 The display substrate shown.

[0147] In one optional implementation, the method for fabricating the display substrate provided in this embodiment may include the following steps:

[0148] Step 31: Fabricate a masking layer to block the channel region of the first thin-film transistor and prevent backlight from affecting its characteristics. (Refer to...) Figure 13 A schematic diagram of the planar structure of a display substrate after the masking layer has been fabricated is shown.

[0149] Step 32: Fabricate the buffer layer and the first active layer made of metal oxide material. The drain contact area is located in the aperture region. Since the metal oxide is transparent, it will not affect the pixel aperture ratio. (Refer to...) Figure 14 A schematic diagram of the planar structure of a display substrate after the fabrication of the first active layer is shown.

[0150] Step 33: Fabricate the first gate insulating layer and the first gate. The first gate is located within the shielding layer region, ensuring that the channel region in the first active layer is shielded by the shielding layer. (Refer to...) Figure 15A schematic diagram of the planar structure of a display substrate after the first gate fabrication is completed is shown.

[0151] Step 34: Fabricate the first interlayer dielectric layer, and drill holes at the positions corresponding to the source contact region of the first active layer, such as... Figure 16 The 161 in the diagram is used to allow subsequent film layers to overlap with the first active layer. (Refer to...) Figure 16 A schematic diagram of the planar structure of a display substrate after the fabrication of the first interlayer dielectric layer is shown.

[0152] Step 35: Fabricate the data cable. The data cable is connected to the source contact area via a via disposed on the first interlayer dielectric layer. (Refer to...) Figure 17 A schematic diagram of the planar structure of the display substrate after the data cable fabrication is completed is shown.

[0153] Step 36: Fabricate the first passivation layer and the first electrode layer. Drill holes in the first passivation layer at positions corresponding to the drain contact region of the first active layer, such as... Figure 18 In section 181, the first electrode layer and the drain contact region are connected through a via disposed on the first passivation layer. (See reference...) Figure 18 A schematic diagram of the planar structure of a display substrate after the fabrication of the first electrode layer is shown.

[0154] Step 37: Fabricate a color resist layer. Placing the color resist layer on the display substrate can effectively reduce crosstalk between different colors of light; refer to... Figure 19 A schematic diagram of the planar structure of a display substrate with the completed color resist layer fabrication is shown.

[0155] Step 38: Create the first planarization layer and form through-holes, such as... Figure 20 201 in the middle, refer to Figure 20 A schematic diagram of the planar structure of a display substrate after the first planarization layer has been fabricated is shown.

[0156] Step 39: Sequentially form the second electrode layer, the second planarization layer, and the third electrode layer. The second and third electrode layers are formed separately. The second planarization layer fills the vias on the first planarization layer. This structure ensures both the electrical connection between the third electrode layer and the first electrode layer, and the overall flatness of the third electrode layer, ensuring a uniform electric field is formed between it and the common electrode layer. (Refer to...) Figure 21 A schematic diagram of the planar structure of a display substrate after the fabrication of the third electrode layer is shown.

[0157] Step 310: Fabricate the third passivation layer and the common electrode layer. The common electrode layer and the third electrode layer together form an electric field to drive the liquid crystal deflection. (Refer to...) Figure 22 A schematic diagram of the planar structure of a display substrate with the common electrode layer fabricated is shown. This allows for the fabrication of... Figure 1 The display substrate shown.

[0158] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0159] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0160] The above provides a detailed description of a display substrate, its preparation method, and the display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0161] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0162] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0163] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0164] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0165] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, characterized by, The display substrate includes: A substrate, and a first electrode layer disposed on one side of the substrate, the first electrode layer including a first electrode pattern; A first planarization layer is disposed on the side of the first electrode layer opposite to the substrate. A through-hole is disposed on the first planarization layer, and the through-hole penetrates the first planarization layer to expose the first electrode pattern. A second electrode layer, a second planarization layer, and a third electrode layer are stacked on the side of the first planarization layer opposite to the substrate. The second electrode layer is disposed close to the substrate. The orthogonal projection of the second electrode layer on the substrate covers the orthogonal projection of the via on the substrate. The second electrode layer connects the first electrode pattern and the third electrode layer. The second planarization layer fills the via to planarize the via. The display substrate includes a display area and a non-display area, and the display area includes an open area and a non-open area; The display substrate further includes: a first thin-film transistor disposed on the side of the substrate near the first electrode layer, the first thin-film transistor being located in the display area, the first thin-film transistor including a first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer and a first source layer stacked thereon, the first active layer being disposed near the substrate, the first active layer including a drain contact region located in the opening region; the orthographic projection of the first gate insulating layer and the first interlayer dielectric layer on the substrate does not overlap with the opening region; the drain contact region is the first electrode pattern; The channel region of the first active layer includes a first channel region, a first resistance region, and a second channel region arranged sequentially along a first direction. The first gate includes a first sub-gate and a second sub-gate disposed separately. The orthographic projection of the first sub-gate on the substrate covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second sub-gate on the substrate covers the orthographic projection of the second channel region on the substrate.

2. The display substrate according to claim 1, characterized in that, The orthogonal projection of the via on the substrate falls entirely within the orthogonal projection of the second electrode layer on the substrate.

3. The display substrate according to claim 1, characterized in that, The orthographic projection of the second electrode layer on the substrate falls completely within the orthographic projection of the third electrode layer on the substrate.

4. The display substrate according to claim 1, characterized in that, The orthographic projection of the second planarization layer on the substrate falls completely within the orthographic projection of the third electrode layer on the substrate.

5. The display substrate according to claim 1, characterized in that, The through-hole and the second electrode layer are rectangular, circular, or elliptical in shape.

6. The display substrate according to claim 1, characterized in that, The material of the first active layer includes metal oxides.

7. The display substrate according to claim 1, characterized in that, The display area further includes data lines and scan lines. The first source extends along a first direction to form the data lines, and the first gate extends along a second direction intersecting the first direction to form the scan lines. The orthogonal projections of the data lines and the scan lines on the substrate respectively cover the orthogonal projection of the channel region of the first active layer on the substrate.

8. The display substrate according to claim 7, characterized in that, The material of the first active layer includes polycrystalline silicon, and the orthogonal projection of the data line on the substrate covers the orthogonal projection of the first active layer on the substrate.

9. The display substrate according to claim 1, characterized in that, A shielding layer and a second interlayer dielectric layer are also stacked between the first active layer and the substrate. The shielding layer is disposed close to the substrate, and the orthogonal projection of the shielding layer on the substrate covers the orthogonal projection of the channel region of the first active layer on the substrate.

10. The display substrate according to claim 9, characterized in that, The display area also includes data lines and scan lines, and the orthogonal projection of the shielding layer on the substrate covers the orthogonal projection of the data lines and the scan lines on the substrate.

11. The display substrate according to claim 9, characterized in that, The shielding layer is connected to a fixed potential input terminal.

12. The display substrate according to claim 9, characterized in that, The shielding layer is connected to the first source electrode through vias disposed on the second interlayer dielectric layer, the first gate insulating layer, and the first interlayer dielectric layer.

13. The display substrate according to claim 9, characterized in that, The material of the shielding layer includes at least one of the following: molybdenum, aluminum, and silver.

14. The display substrate according to claim 1, characterized in that, The display substrate further includes a second thin-film transistor located in the non-display area, and the active layer material of the second thin-film transistor includes polycrystalline silicon.

15. The display substrate according to claim 1, characterized in that, A second passivation layer and a fourth electrode layer are stacked on the side of the first electrode layer away from the substrate. The fourth electrode layer is transparent and connected to a first fixed potential input terminal. The second passivation layer is disposed close to the substrate. The orthographic projections of the first electrode layer and the fourth electrode layer on the substrate overlap. The first planarization layer is disposed on the side of the fourth electrode layer away from the substrate, the via penetrates the second passivation layer, and the via does not overlap with the orthographic projection of the fourth electrode layer on the substrate.

16. The display substrate according to claim 1, characterized in that, The display substrate includes an opening area, and a color resist layer is further disposed on the side of the first electrode layer away from the substrate, the orthogonal projection of the color resist layer on the substrate covering the opening area; The first planarization layer is disposed on the side of the color resist layer away from the substrate, and the orthographic projection of the via on the substrate does not overlap with the orthographic projection of the color resist layer on the substrate.

17. The display substrate according to claim 1, characterized in that, A third passivation layer and a common electrode layer are stacked on the side of the third electrode layer away from the substrate. The third passivation layer is disposed close to the substrate. The common electrode layer includes a plurality of strip electrodes and is made of metal.

18. The display substrate according to claim 1, characterized in that, An isolation pillar is also provided on the side of the first planarization layer away from the substrate, and the isolation pillar is formed synchronously with the second planarization layer.

19. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 18.

20. A method for preparing a display substrate, characterized in that, The preparation method includes: Provide substrate; A first electrode layer is formed on one side of the substrate, the first electrode layer including a first electrode pattern; A first planarization layer is sequentially formed on the side of the first electrode layer away from the substrate. A through-hole is provided on the first planarization layer, and the through-hole penetrates the first planarization layer to expose the first electrode pattern. A second electrode layer, a second planarization layer, and a third electrode layer are sequentially formed on the side of the first planarization layer away from the substrate, wherein the orthographic projection of the second electrode layer on the substrate covers the orthographic projection of the via on the substrate, the second electrode layer is used to connect the first electrode pattern and the third electrode layer, and the second planarization layer is used to planarize the via. The display substrate includes a display area and a non-display area, the display area including an opening area and a non-opening area; the display substrate further includes: a first thin-film transistor disposed on the substrate near the first electrode layer, the first thin-film transistor being located in the display area, the first thin-film transistor including a first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer and a first source layer stacked thereon, the first active layer being disposed near the substrate, the first active layer including a drain contact area, the drain contact area being located in the opening area; the orthographic projection of the first gate insulating layer and the first interlayer dielectric layer on the substrate does not overlap with the opening area; the drain contact area is the first electrode pattern; The channel region of the first active layer includes a first channel region, a first resistance region, and a second channel region arranged sequentially along a first direction. The first gate includes a first sub-gate and a second sub-gate disposed separately. The orthographic projection of the first sub-gate on the substrate covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second sub-gate on the substrate covers the orthographic projection of the second channel region on the substrate.

Images