Semiconductor devices

Abstract

In a semiconductor device in which a vertical MOSFET with the same structure is formed in the main cell region (Rm) and the sensing cell region (Rs), the sensing cell region is defined as a quadrilateral region that surrounds the working area of ​​the semiconductor switching element formed as the sensing cell. The dimension in the same direction as one direction of the main cell region, specifically the longer direction of the gate wiring layer (8), is set as the lateral dimension, and the dimension in the direction perpendicular to the lateral dimension is set as the longitudinal dimension. The longitudinal dimension is greater than or equal to the lateral dimension.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-115972, filed on July 3, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a vertically shaped semiconductor switching element having the same structure in a main cell region and a sensing cell region, and a semiconductor device for detecting the current flowing through the main cell region based on the current flowing through the sensing cell region. Background Technology

[0004] Patent Document 1 discloses a semiconductor device that has a vertically shaped semiconductor switching element with the same structure in the main cell region and the sensing cell region, and detects the current flowing through the main cell region based on the current flowing through the sensing cell region.

[0005] This semiconductor device is configured such that a current sensing element is arranged in a sensing unit region between main elements having planar gate electrodes and formed in the main cell region. A high-resistance region is provided between the main elements and the sensing element to electrically isolate them. By making such a configuration, the path of charge carriers is adjusted, and the accuracy of the detected current flowing through the current sensing element is improved.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 10-261704

[0009] In a semiconductor device like Patent Document 1, which detects the current flowing through a main component based on the current flowing through a current sensing element, the design of the gate voltage dependence of the current sensing element is important in order to practically improve the detection accuracy of the current sensing element. Therefore, it is desirable to have a semiconductor device with a structure capable of designing a gate voltage dependence. Summary of the Invention

[0010] The purpose of this disclosure is to provide a semiconductor device with a structure capable of being designed to be gate voltage dependent.

[0011] According to one aspect of this disclosure, a semiconductor device has a vertically shaped semiconductor switching element with the same structure formed in a main cell region and a sensing cell region. The semiconductor switching element includes: a drift layer of a first conductivity type; a channel layer of a second conductivity type formed on the drift layer; a first impurity region of the first conductivity type formed on the surface portion of the channel layer within the channel layer, wherein the impurity concentration is higher than that of the drift layer; a gate insulating film covering the channel layer between the first impurity region and the drift layer; a gate electrode layer consisting of multiple strips arranged in a strip-like configuration along one longitudinal direction, formed on the surface of the gate insulating film to form a channel region over the channel layer; a second impurity region of the first or second conductivity type formed on the side opposite to the channel layer, separated by the drift layer, wherein the impurity concentration is higher than that of the drift layer; an upper electrode electrically connected to the first impurity region and the channel layer; and a lower electrode electrically connected to the second impurity region. Furthermore, the sensing unit region is defined as a quadrilateral region that surrounds the working area of ​​the semiconductor switching element formed as a sensing unit, and the dimension in the same direction as the aforementioned direction of the main unit region is set as the lateral dimension, and the dimension in the direction perpendicular to the lateral dimension is set as the longitudinal dimension, with the longitudinal dimension being greater than or equal to the lateral dimension.

[0012] In this way, the dimensions are designed such that the vertical dimension of the sensing unit region is greater than or equal to the horizontal dimension. The main current flowing through the main unit region is detected based on the ratio of the sensed current flowing through the sensing unit region to the main current flowing through the main unit region (hereinafter referred to as the sensing ratio). Therefore, if the change in the sensing ratio is large relative to the change in the gate voltage, the sensing ratio can be detected with high sensitivity and accuracy. Thus, when considering a circuit that detects the sensing ratio or sensed current of the semiconductor device driving the vertical semiconductor switching element through a feedback circuit, the degree of freedom in the circuit design for controlling the gate voltage through the gate driver circuit can be increased. As a result, gate voltage-dependent designs are possible.

[0013] Furthermore, according to another aspect of this disclosure, a semiconductor switching element comprises: a drift layer of a first conductivity type; a channel layer of a second conductivity type formed on the drift layer; a first impurity region of the first conductivity type formed on the surface portion of the channel layer within the channel layer, wherein the impurity concentration is higher than that of the drift layer; a gate insulating film covering the channel layer between the first impurity region and the drift layer; a gate electrode layer, having multiple electrodes arranged in a strip-like configuration along one longitudinal direction, formed on the surface of the gate insulating film to form a channel region for the channel layer; a second impurity region of the first or second conductivity type formed on the opposite side of the channel layer, separated by the drift layer, wherein the impurity concentration is higher than that of the drift layer; an upper electrode electrically connected to the first impurity region and the channel layer; and a lower electrode electrically connected to the second impurity region. In the drift layer of the sensing unit region, a resistive component layer is formed that makes the drift layer have a higher resistance compared to the drift layer of the main unit region.

[0014] Thus, a resistive component layer is incorporated into the drift layer within the sensing cell region. This structure reduces the sensing current flowing through the sensing cell region. Consequently, the gate voltage dependence of the sensing cell region can be made approximately identical to that of the main cell region. This allows for the design of gate voltage dependence.

[0015] In addition, the parenthesized reference numerals assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent elements described in the embodiments described later. Attached Figure Description

[0016] Figure 1 This is a layout diagram of the upper surface of the semiconductor device according to the first embodiment.

[0017] Figure 2 yes Figure 1 Section II-II.

[0018] Figure 3 yes Figure 1 Section III-III.

[0019] Figure 4 yes Figure 1 Section IV-IV.

[0020] Figure 5 This is a diagram illustrating the layout of the upper surface of the sensing unit area.

[0021] Figure 6 It is a block diagram representing the configuration of a semiconductor device driven by a gate driver circuit.

[0022] Figure 7 This is a graph showing the relationship between the sense ratio and the gate voltage.

[0023] Figure 8 This is a top surface layout diagram of the sensing unit region in a semiconductor device illustrating a modified example of the first embodiment.

[0024] Figure 9 This is a cross-sectional view of a modified example of the first embodiment in which the p-type layer of the channel is separated.

[0025] Figure 10 This is a layout diagram of the upper surface of the sensing unit region illustrating a modified example of the first embodiment.

[0026] Figure 11 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0027] Figure 12 This is a graph showing the relationship between the sense ratio and the gate voltage. Detailed Implementation

[0028] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in the following embodiments, the same or equivalent parts will be described using the same reference numerals.

[0029] (First Embodiment)

[0030] The first embodiment will be described. In this embodiment, a semiconductor device having an n-channel vertical MOSFET as a vertically oriented semiconductor switching element with the same structure in both the main cell region and the sensing cell region will be described. Hereinafter, based on Figures 1-4 The structure of the semiconductor device in this embodiment will be explained.

[0031] like Figure 1 As shown, the semiconductor device of this embodiment is configured to have a main cell region Rm and a sensing cell region Rs. The main cell region Rm is configured as a quadrilateral with a portion missing, and the sensing cell region Rs is disposed within the main cell region Rm, formed in a manner that it is surrounded by the main cell region Rm. Furthermore, Figure 1 In the figure, it only represents the vicinity of the sensing unit region Rs in the main unit region Rm, but the area of ​​the main unit region Rm is actually large enough compared to the sensing unit region Rs, for example, it is 100 million times larger.

[0032] In the main cell region Rm and the sensing cell region Rs, there are n-channel vertical MOSFETs with the same structure.

[0033] like Figure 2 As shown, semiconductor devices utilize n-type semiconductor materials such as silicon with a high impurity concentration. + It is formed by forming a semiconductor substrate 1. For example, the thickness of the semiconductor substrate 1 is set to 10 to 300 μm, and the n-type impurity concentration is set to 1 × 10⁻⁶. 12 ~1×10 18 cm －3 Left and right. In n + On the surface of the semiconductor substrate 1, an impurity concentration ratio of n is formed. + Type 1 semiconductor substrate with low n － Type 2 drift layer, in n － At the desired location of the drift layer 2, a channel p-type layer 3 with a relatively low impurity concentration is formed. － The thickness of the n-type drift layer 2 is set to 1–10 μm, and the concentration of the n-type impurities is set to 1 × 10⁻⁶. 12 ~1×10 18 cm －3 Approximately. Furthermore, the thickness of the p-type layer 3 in the channel was set to 0–2 μm, and the p-type impurity concentration was set to 1 × 10⁻⁶. 12 ~1×1018 cm －3 about.

[0034] Channel p-type layer 3 through n － The p-type drift layer 2 is formed by implanting p-type impurity ions, etc. In this embodiment, such as... Figure 4 As shown, the channel p-type layer 3 is constructed such that the main channel layer 3a formed in the main cell region Rm and the sensing channel layer 3b formed in the sensing cell region Rs are continuously connected.

[0035] In the surface portion of the p-type layer 3 of the channel, there exists a source region with an impurity concentration higher than that of the n-type layer. － The type drift layer 2 is equivalent to the n of the first impurity region. + Type 4 impurity region. + For example, the thickness of the n-type impurity region 4 is set to 0–2 μm, and the concentration of the n-type impurity is set to 1 × 10⁻⁶. 12 ~1×10 18 cm －3 about.

[0036] In addition, n is formed from the substrate surface side. + Type impurity region 4 and channel p-type layer 3 are connected until n is reached. － The trench 5 of the drift layer 2 is formed. A gate insulating film 6 is formed to cover the inner wall of the trench 5, and a shielding electrode 7 made of doped polysilicon and a gate electrode layer 8 are stacked in the trench 5 through the gate insulating film 6 to form a two-layer structure. The shielding electrode 7 is formed to reduce the gate-drain capacitance by fixing it to the source potential, thereby improving the electrical characteristics of the MOSFET. The gate electrode layer 8 performs the switching operation of the MOSFET, and a channel is formed in the p-type layer 3 on the side of the trench 5 when a gate voltage is applied.

[0037] An insulating film 9 is formed between the shielding electrode 7 and the gate electrode layer 8, insulating the shielding electrode 7 and the gate electrode layer 8. The trenches 5, the gate insulating film 6, the shielding electrode 7, the gate electrode layer 8, and the insulating film 9 constitute a trench gate structure. This trench gate structure is exemplified by... Figure 2 The vertical direction of the paper is the longer direction. Figure 1 The top and bottom directions on the paper, that is Figure 2 The paper is arranged with multiple grooves in the left-right direction, thus forming a strip-like layout. The spacing between the groove grid structures is arbitrary, for example, 1 to 2 μm.

[0038] Additionally, a trench gate structure is formed between the main cell region Rm and the sensing cell region Rs, but no n is formed. + Type 4 impurity region does not constitute a vertical MOSFET.

[0039] In addition, trench 5, as Figure 3 As shown, the main cell region Rm and the sensing cell region Rs are continuously connected. Furthermore, the shielding electrode 7 and the gate electrode layer 8 embedded in the trench 5 are also continuously connected in a manner that reaches both the main cell region Rm and the sensing cell region Rs.

[0040] Furthermore, although not illustrated in the figure, at one end of the trench 5 in the longer direction, the shielding electrode 7 extends to the outside of the main cell region Rm relative to the gate electrode layer 8, that is, the side of the main cell region Rm away from the sensing cell region Rs. This portion is exposed from the surface of the channel p-type layer 3 as a shielding liner, thereby achieving electrical connection with the upper electrode 10, which is set to the source potential and described later.

[0041] Similarly, at the other end of the trench 5 in its longer direction, the gate electrode layer 8 extends to the outside of the main cell region Rm, i.e., the side of the main cell region Rm furthest from the sensing region, relative to the shielding electrode 7. Furthermore, this portion is exposed from the surface of the channel p-type layer 3 as a gate pad, achieving electrical connection with a gate electrode (not shown).

[0042] Furthermore, an interlayer insulating film 13, composed of an oxide film or the like, is formed to cover the gate electrode layer 8. An upper electrode 10, corresponding to the source electrode, and a gate electrode (not shown) are formed on this interlayer insulating film 13. The upper electrode 10 passes through a portion where the interlayer insulating film 13 is not formed, such as a contact hole, and connects to n. + The impurity region 4 and the p-type channel layer 3 are electrically connected. The gate electrode also passes through the portion where the interlayer insulating film 13 is not formed, such as the contact hole, and is electrically connected to the gate electrode layer 8 via the gate pad.

[0043] The upper electrode 10 is divided into a main electrode 10a formed in the main cell region Rm and a sensing electrode 10b formed in the sensing cell region Rs, which are separated by a predetermined distance. The main electrode 10a is formed over approximately the entire area of ​​the main cell region Rm and is configured as a quadrilateral with a portion missing. The sensing electrode 10b is a quadrilateral and is arranged to be surrounded by the main electrode 10a. From one side of the sensing electrode 10b corresponding to the portion missing in the main cell region Rm, a lead wire 10c is led out to the outside of the main cell region Rm.

[0044] Furthermore, in n + The semiconductor substrate 1 of type n － A lower electrode 12, corresponding to the drain electrode, is formed on the opposite side of the drift layer 2. This structure constitutes the basic configuration of a vertical MOSFET. Furthermore, as... Figure 2As shown, a vertical MOSFET is formed by assembling multiple units to form the main unit region Rm and the sensing unit region Rs.

[0045] As described above, a semiconductor device with a vertical MOSFET is constructed. In such a semiconductor device, when a gate voltage is applied to the gate electrode layer 8 of the vertical MOSFET provided in the main cell region Rm and the sensing cell region Rs, a channel is formed on the surface of the p-type channel layer 3 that is connected to the trench 5. As a result, electrons injected from the upper electrode 10 flow from the n... + Type impurity region 4 reaches n after passing through the channel formed in the p-type layer 3. － The drift layer 2 allows current to flow between the upper electrode 10 and the lower electrode 12.

[0046] Furthermore, vertically oriented MOSFETs with identical cell structures are formed in both the main cell region Rm and the sensing cell region Rs, and the cell areas, or in other words, the number of cells, of the vertically oriented MOSFETs in the main cell region Rm and the sensing cell region Rs are set to a predetermined ratio. Therefore, a sensing current, after the main current flowing through the main cell region Rm is reduced by a predetermined ratio, can flow through the sensing cell region Rs. Thus, by outputting the sensing current flowing through the sensing cell region Rs to the outside, the sensing current flowing through the main cell region Rm can be detected.

[0047] In such semiconductor devices, such as Figure 1 Viewed from the top, the direction in the sensing cell region Rs that is parallel to the longer direction of the trench gate structure is defined as the lateral direction, and the direction perpendicular to the longer direction is defined as the longitudinal direction, thus defining the dimensional relationship between the longitudinal and lateral dimensions. The sensing cell region Rs is the quadrilateral portion that forms the working region in a vertical MOSFET formed as a sensing cell. That is, the sensing cell region Rs is formed by creating n along the trench gate structure that constitutes the source region. + Type impurity region 4 is the region through which current flows when a gate voltage is applied to the gate electrode layer 8, thus enabling MOS operation. Specifically, as... Figure 5 As shown, the sensing unit region Rs is represented as a plurality of n that will contact the sensing electrode 10b. + The area uniformly surrounded by type impurity region 4.

[0048] Furthermore, the vertical dimension of the sensing unit region Rs is greater than or equal to the horizontal dimension; in other words, the ratio of the vertical dimension to the horizontal dimension of the sensing unit region Rs is 1 or greater. More preferably, the dimension of the portion of the sensing unit region Rs that becomes the current path after removing the width of the trench gate structure from the vertical dimension (hereinafter referred to as the current path dimension) is greater than or equal to the horizontal dimension.

[0049] The main current flowing through the main cell region Rm is detected based on the sensing ratio. Specifically, as... Figure 6 As shown, a gate voltage is applied to a semiconductor device 101 having a main cell region Rm and a sensing cell region Rs by a gate driver circuit 100, and the sensing ratio or sensing current at this time is fed back to the gate driver circuit 100. The gate driver circuit 100 includes a feedback circuit, which detects the sensing ratio or sensing current and controls the desired main current by adjusting the gate voltage output by the gate driver circuit 100.

[0050] Figure 7 The dependence of the sensing ratio on the gate voltage (Vgs) is shown (hereinafter referred to as Vgs dependence). In the figure, in addition to the characteristic (1) in which the longitudinal dimension of the sensing cell region Rs is greater than or equal to the lateral dimension as in this embodiment, the characteristic (2) in which the lateral dimension is greater than the longitudinal dimension is also shown.

[0051] As shown in the figure, the sensing ratio is Vgs dependent. However, when the lateral dimension of the sensing cell region Rs is larger than the longitudinal dimension, the change in the sensing ratio relative to the gate voltage of the element is small. Although the sensing ratio decreases as the gate voltage increases, the sensing ratio remains relatively constant regardless of the gate voltage. In contrast, when the longitudinal dimension of the sensing cell region Rs is larger than the lateral dimension as in this embodiment, the change in the sensing ratio relative to the gate voltage of the element is larger, and the sensing ratio decreases as the gate voltage increases. Furthermore, the higher the gate voltage, the greater the rate of decrease in the sensing ratio. On the other hand, in the current sensing detection method with an external resistor used in conjunction with the gate driver circuit 100, since the sensing cell itself is gate voltage dependent, the gate voltage dependence of the entire system including the resistor is suppressed, and the sensing ratio can be detected with high sensitivity.

[0052] As described above, the sensing ratio or sensing current is fed back to the gate driver circuit 100, but the feedback is the sensing ratio when the gate voltage is set to a predetermined value, and the gate voltage output by the gate driver circuit 100 is adjusted. In this case, if the change in the sensing ratio relative to the change in the gate voltage is large, the sensing ratio can be detected with high sensitivity and accuracy. Therefore, considering a circuit that detects the sensing ratio or sensing current of the semiconductor device driving the vertical MOSFET via a feedback circuit, the degree of freedom in the circuit design for controlling the gate voltage via the gate driver circuit 100 can be increased. This allows for Vgs-dependent designs.

[0053] (A variation of the first embodiment)

[0054] In the first embodiment described above, the longitudinal dimension of the sensing unit region Rs is greater than or equal to the transverse dimension, but such a structure can be achieved through various constructions.

[0055] For example, it can be like Figure 8 As shown, regarding the sensing cell region Rs, compared to the main cell region Rm, the spacing of the trench gate structure, in other words, the spacing of the gate electrode layers 8, is made longer, resulting in a structure where there is no trench gate structure anywhere. In this case, it is easier to make the current path size in the sensing cell region Rs greater than the lateral dimension.

[0056] Furthermore, in the first embodiment, the channel p-type layers 3 formed in the main cell region Rm and the sensing cell region Rs are continuously connected, but it is also possible to... Figure 9 As shown, it is constructed with the main unit region Rm and the sensing unit region Rs separated.

[0057] In addition, the working area of ​​the sensing unit region Rs can also be divided into multiple parts, for example, Figure 10 The structure is configured such that two working regions are arranged perpendicular to the longer direction of the trench gate structure, as shown. Specifically, multiple groups of trench gate structures arranged in strips are formed, such that the spacing between adjacent trench gate structures in each group is greater than the spacing between trench gate structures arranged in the same group. In this case, the channel p-type layers 3 of adjacent groups can also be separated within the sensing unit region Rs. In this way, the longitudinal dimension of the multiple working regions separated into sensing unit regions Rs is greater than or equal to the transverse dimension.

[0058] (Second Implementation)

[0059] The second embodiment will be described. Compared to the first embodiment, this embodiment allows for the design of gate voltage dependence through a different structure. Everything else is the same as the first embodiment, so only the parts that are different from the first embodiment will be described.

[0060] like Figure 11 As shown, in this embodiment, in the sensing unit region Rs, below the trench gate structure, there is a structure for n － A portion of the drift layer 2 is configured as a high-resistivity resistive component layer 2a. The resistive component layer 2a is, for example, configured by adjusting the n... － The drift layer 2 is formed by ion implantation of p-type impurities. By having this resistive component layer 2a, in the sensing cell region Rs, compared to the main cell region Rm, n － The resistance of the n-type drift layer 2 increases. For example, the resistivity component layer 2a has a thickness of 0–5 μm and an n-type impurity concentration of 1 × 10⁻⁶. 12 ~1×10 18 cm －3about.

[0061] like Figure 2 As shown, the main cell region Rm and the sensing cell region Rs are vertically oriented MOSFETs with the same structure, but the current paths of the main current and the sensing current during operation are different. That is, if we compare the formation areas of the main cell region Rm and the sensing cell region Rs, the formation area of ​​the sensing cell region Rs is sufficiently small compared to the formation area of ​​the main cell region Rm. Therefore, in the sensing cell region Rs, the proportion of current flowing from the outside to the inside of the region is larger than that in the main cell region Rm, and current tends to flow into the sensing cell region Rs. Under this influence, the Vgs dependence in the sensing cell region Rs and the main cell region Rm becomes inconsistent.

[0062] Therefore, if a resistive component layer 2a is provided as in this embodiment, the sensing current flowing through the sensing unit region Rs can be reduced. Thus, the Vgs dependence of the sensing unit region Rs and the main unit region Rm can be made approximately the same. Specifically, as... Figure 12 As shown, the Vgs dependence of the sensing ratio can be eliminated, and it can be adjusted so that the sensing ratio remains approximately constant even when the gate voltage changes. Therefore, Vgs-dependent designs are possible.

[0063] (Other implementation methods)

[0064] This disclosure is based on the embodiments described above, but is not limited to these embodiments, and includes various modifications and variations within the same range. In addition, various combinations and forms, and further, combinations and forms containing only one element, or more or less thereof, also fall within the scope and spirit of this disclosure.

[0065] (1) For example, in the above embodiments, a high concentration of impurity region is formed on a semiconductor substrate 1, and n is made thereon. － This is an example of epitaxial growth of the p-type drift layer 2. This merely illustrates one case where a high-concentration impurity region is formed on the side opposite to the channel p-type layer 3, separated by the drift layer. Alternatively, the drift layer can be formed on a semiconductor substrate, and a high-concentration impurity region can be formed on its back side by ion implantation or similar methods. Furthermore, the impurity region including the semiconductor substrate 1 described herein corresponds to the second impurity region.

[0066] (2) Furthermore, in the above embodiment, the main unit region Rm is set as a quadrilateral such that it surrounds three sides of the sensing unit region Rs, but this is only one example. For example, the main unit region Rm may also be set as a shape that is not quadrilateral. In addition, the main unit region Rm may also be set as a structure that surrounds three sides and a portion of the remaining side of the sensing unit region Rs. Furthermore, it may also be set as a structure that does not surround the sensing unit region Rs through the main unit region Rm, for example, a structure in which one corner of the quadrilateral main unit region Rm is cut off and the sensing unit region Rs is arranged in that part.

[0067] (3) Furthermore, in the above embodiment, a vertical MOSFET with a trench gate having a two-layer structure was described as an example, but a two-layer structure is not necessary, and a single-gate structure is also possible. Alternatively, a planar vertical MOSFET may not be used. Regardless of the structure of the vertical MOSFET, it is acceptable as long as a gate electrode layer 8 is formed on the surface of the channel p-type layer 3 with the gate insulating film 6 in between, and the gate electrode layers 8 extend in one direction as the longer direction and are arranged in multiple rows in its vertical direction. Of course, the portion of the gate electrode layer 8 extending in one direction as the longer direction is sufficient; for example, adjacent gate electrode layers 8 may be connected to each other in a semi-circular shape at their two front ends.

[0068] (4) Furthermore, in the above embodiment, an n-channel vertical MOSFET with the first conductivity type set to n-type and the second conductivity type set to p-type was described as an example of a semiconductor switching element. However, this is only one example, and other semiconductor switching elements with different structures can also be made, such as a p-channel vertical MOSFET obtained by inverting the conductivity types of each component of an n-channel MOSFET. In addition, this disclosure can also be applied to vertical IGBTs with the same structure, in addition to vertical MOSFETs. In the case of vertical IGBTs, except that the conductivity type of the semiconductor substrate 1 is changed from n-type to p-type, it is the same as the vertical MOSFET described in the above embodiment.

Claims

1. A semiconductor device comprising a vertically shaped semiconductor switching element having the same structure in a main unit region and a sensing unit region, characterized in that, The above-mentioned semiconductor switching element has: Drift layer of the first conductivity type; A second conductivity type channel layer is formed on the aforementioned drift layer; The first impurity region of the first conductivity type is formed in the surface portion of the channel layer within the aforementioned channel layer, and the impurity concentration is higher than that of the aforementioned drift layer. A gate insulating film covers the channel layer between the first impurity region and the drift layer. A gate electrode layer, having multiple strips arranged in a strip-like configuration with one direction as the elongation direction, is formed on the surface of the gate insulating film, thereby forming a channel region for the channel layer. A second impurity region of the first or second conductivity type is formed on the opposite side of the channel layer, separated by the drift layer, and the impurity concentration is higher than that of the drift layer. The upper electrode is electrically connected to the first impurity region and the channel layer; and The lower electrode is electrically connected to the second impurity region mentioned above. The aforementioned sensing unit region is defined as a quadrilateral region that surrounds the working area of ​​the aforementioned semiconductor switching element formed as a sensing unit. The dimension in the same direction as the aforementioned direction of the main unit region is defined as the lateral dimension, and the dimension in the direction perpendicular to the lateral dimension is defined as the longitudinal dimension. The longitudinal dimension is greater than or equal to the lateral dimension. The spacing of the gate electrode layers arranged in a strip shape in the main cell region is longer than that in the sensing cell region. In the region where the aforementioned sensing unit region is provided, each of the aforementioned gate electrode layers extends continuously in the aforementioned main unit region and the aforementioned sensing unit region.

2. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned sensing unit region includes multiple working areas of the aforementioned semiconductor switching elements formed as sensing units. The aforementioned sensing unit region is defined as a quadrilateral region that surrounds the multiple working areas.

3. The semiconductor device as claimed in claim 2, characterized in that, As the aforementioned multiple work areas, two of the aforementioned work areas are arranged in the aforementioned vertical direction.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, It has a trench gate structure, which has the following structure: With the aforementioned direction as the longer direction, a trench is formed that extends from the first impurity region through the channel layer to the drift layer, and the gate electrode layer is formed in the trench, separated by the gate insulating film.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The current path dimension obtained by subtracting the width of the gate electrode layer from the longitudinal dimension of the sensing unit region is greater than or equal to the lateral dimension.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The aforementioned channel layer is a structure in which the main channel layer formed in the aforementioned main unit region and the sensing channel layer formed in the aforementioned sensing unit region are continuously connected.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, In the aforementioned sensing unit region, the trench gate structure is missing in various places, resulting in a longer spacing between the aforementioned gate electrode layers.

8. A semiconductor device comprising a vertically shaped semiconductor switching element having the same structure in a main unit region and a sensing unit region, characterized in that, The above-mentioned semiconductor switching element has: Drift layer of the first conductivity type; A second conductivity type channel layer is formed on the aforementioned drift layer; The first impurity region of the first conductivity type is formed in the surface portion of the channel layer within the aforementioned channel layer, and the impurity concentration is higher than that of the aforementioned drift layer. A gate insulating film covers the channel layer between the first impurity region and the drift layer. A gate electrode layer, having multiple strips arranged in a strip-like configuration with one direction as the longer direction, is formed on the surface of the gate insulating film, thereby forming a channel region for the channel layer. A second impurity region of the first or second conductivity type is formed on the opposite side of the channel layer, separated by the drift layer, and the impurity concentration is higher than that of the drift layer. The upper electrode is electrically connected to the first impurity region and the channel layer; and The lower electrode is electrically connected to the second impurity region mentioned above. In a portion of the drift layer in the aforementioned sensing unit region, a resistive component layer is formed that makes the drift layer have a higher resistance compared to the drift layer in the aforementioned main unit region.

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