High performance tunable filter using gallium arsenide

Abstract

A gallium arsenide (GaAs)-enabled tunable filter for use in, for example, a 6 GHz Wi-Fi RF front-end, is disclosed, featuring an integrated high-performance variable capacitor, a metal-insulator-metal (MIM) capacitor, and a 3D solenoid inductor. The tunable filter includes a super-sudden variable capacitor (120) (variable capacitor) with a high capacitance tuning ratio. The tunable filter also includes a GaAs substrate in which a GaAs via (160) (TGV) is formed. The variable capacitor, along with the MIM capacitor and the 3D inductor (142), is formed in an upper conductive structure (150) on the upper surface of the GaAs substrate. A lower conductive structure (170), including a lower conductor, is formed on the lower surface of the GaAs substrate. Electrical coupling between the lower and upper conductive structures is provided by the TGV. The tunable filter can be integrated with radio frequency front-end (RFFE) devices.

Description

[0001] Cross-reference to related applications This patent application claims the benefit of U.S. nonprovisional application No. 16 / 922471 entitled “HIGH PERFORMANCE TUNABLE FILTER”, filed July 7, 2020, which has been assigned to the assignee of this application and is expressly incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to antennas, and more specifically, but not exclusively, to high-performance tunable filters and techniques for their fabrication. Background Technology

[0003] Integrated circuit technology has made significant strides in improving computing power through the miniaturization of active components. Packaged devices can be found in many electronic devices, including processors, servers, and radio frequency (RF) integrated circuits. Packaging technology has become cost-effective in high-pin-count devices and / or high-volume components.

[0004] Tunable filters with variable capacitors (variable capacitors, which are voltage-controlled capacitors) are desirable for cellular and Wi-Fi communications in their RF front-end (RFFE) applications to cover multiple bands and frequencies. Variable capacitors with large Cmax / Cmin tuning ratios (TR), good isolation, linearity, Q factor, and high power handling capability are key performance indicators (KPIs) for the technology benchmark.

[0005] For high-performance variable capacitors with RF KPIs, few technical options exist for RFFE considerations. For example, silicon-on-insulator (SOI) and microelectromechanical systems (MEMS) variable capacitors on silicon substrates, as well as MEMS variable capacitors on glass substrates, have been developed. MEMS variable capacitors exhibit high tuning capability (e.g., TR > 8). Unfortunately, they require a high-voltage charge pump (e.g., > 20 V) for capacitor tuning.

[0006] High-Q 3D substrate through-hole (TSuV) inductors built on low-loss and high-thermal-conductivity substrates are also desirable for RF filters used in the TX path, allowing not only low insertion loss but also high power handling capabilities. Among the available 3D TSuV substrates, neither silicon nor glass can meet both the high-Q and high-power handling requirements. Sapphire or alumina can be used as substrates. However, their low TSuV etch rates using conventional photolithography (batch processing) mean that sequential laser scanning / drilling processes are used, resulting in low yields.

[0007] Therefore, there is a need for systems, apparatuses, and methods that overcome the shortcomings of conventional tunable filter packaging, including the methods, systems, and apparatuses provided herein. Summary of the Invention

[0008] The following is a simplified overview relating to one or more aspects and / or examples in connection with the apparatus and methods disclosed herein. Thus, this overview should not be considered an exhaustive summary relating to all anticipated aspects and / or examples, nor should it be considered to identify key or essential elements relating to all anticipated aspects and / or examples, or to depict the scope relating to any particular aspect and / or example. Accordingly, the following overview has the sole purpose of presenting, in a simplified form, certain concepts relating to one or more aspects and / or examples of the apparatus and methods disclosed herein, prior to the detailed description presented below.

[0009] An exemplary tunable filter is disclosed. The tunable filter may include a gallium arsenide (GaAs) substrate. The tunable filter may also include a variable capacitor (variable capacitor) disposed on the upper surface of the GaAs substrate. The tunable filter may also include an upper conductive structure disposed on the upper surface of the GaAs substrate. The upper conductive structure may include one or more upper conductors and one or more upper insulators, which are configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor. The tunable filter may also include one or more GaAs vias (TGVs) disposed through the GaAs substrate from the upper surface to the lower surface of the GaAs substrate. The tunable filter may also include a lower conductive structure disposed on the lower surface of the GaAs substrate. The lower conductive structure may include one or more lower conductors and one or more lower insulators, which are configured to form a lower redistribution layer (RDL). A variable capacitor, a MIM capacitor, and a 3D inductor are electrically coupled to form a radio frequency (RF) filter circuit.

[0010] An exemplary apparatus is disclosed. The apparatus may include a tunable filter and one or more radio frequency front-end (RFFE) devices configured to control the tunable filter when electrically coupled to it. The tunable filter may include a gallium arsenide (GaAs) substrate. The tunable filter may also include a variable capacitor (variable capacitor) disposed on an upper surface of the GaAs substrate. The tunable filter may also include an upper conductive structure disposed on the upper surface of the GaAs substrate. The upper conductive structure may include one or more upper conductors and one or more upper insulators configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor. The tunable filter may also include one or more GaAs vias (TGVs) disposed through the GaAs substrate from the upper surface to the lower surface of the GaAs substrate. The tunable filter may also include a lower conductive structure disposed on the lower surface of the GaAs substrate. The lower conductive structure may include one or more lower conductors and one or more lower insulators, which are configured to form a lower redistribution layer (RDL). A variable capacitor, a MIM capacitor, and a 3D inductor are electrically coupled to form a radio frequency (RF) filter circuit.

[0011] A method for fabricating a tunable filter is disclosed. The method may include forming a variable capacitor (variable capacitor) on the upper surface of a GaAs substrate. The method may also include forming an upper conductive structure on the upper surface of the GaAs substrate. The upper conductive structure may include one or more upper conductors and one or more upper insulators, configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor. The method may also include forming one or more GaAs vias (TGVs) that extend through the GaAs substrate from the upper surface to the lower surface of the GaAs substrate. The method may further include forming a lower conductive structure on the lower surface of the GaAs substrate. The lower conductive structure may include one or more lower conductors and one or more lower insulators, configured to form a lower redistribution layer (RDL). The variable capacitor, MIM capacitor, and 3D inductor are electrically coupled to form a radio frequency (RF) filter circuit.

[0012] Based on the accompanying drawings and detailed description, other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0013] A more complete understanding of aspects of this disclosure and its many accompanying advantages will become readily available when considered in conjunction with the following detailed description taken in conjunction with the accompanying drawings, which are presented for illustrative purposes only and not as a limitation thereof.

[0014] Figure 1 An example tunable filter according to one or more aspects of this disclosure is illustrated.

[0015] Figures 2A-2B The illustration shows an example integration of one or more tunable filters with an RF front-end device according to one or more aspects of this disclosure.

[0016] Figures 3A-3G , Figures 4A-4F and Figures 5A-5F An example stage of manufacturing a tunable filter according to one or more aspects of this disclosure is illustrated.

[0017] Figures 6-9 A flowchart illustrating an example method for manufacturing a tunable filter according to one or more aspects of this disclosure is shown.

[0018] Figure 10 Various electronic devices that can utilize one or more aspects of this disclosure are illustrated.

[0019] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. As is customary, features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of the depicted features may be arbitrarily enlarged or reduced for clarity. As is customary, some figures in the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular apparatus or method. Furthermore, the same reference numerals denote the same features throughout the specification and drawings. Detailed Implementation

[0020] Aspects of this disclosure are illustrated in the following description of specific embodiments and in the accompanying drawings. Alternative aspects or embodiments may be designed without departing from the scope of the teachings herein. Furthermore, well-known elements of the illustrative embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in this disclosure.

[0021] In some of the exemplary embodiments described, instances are identified in which portions of the various component structures and operations may be derived from known conventional techniques and then arranged according to one or more exemplary embodiments. In such cases, the internal details of known conventional component structures and / or operational portions may be omitted to help avoid potential confusion with the concepts shown in the illustrative embodiments disclosed herein.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that when the terms “comprising,” “including,” “constituting,” and / or “having” are used herein, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Based on the various aspects disclosed herein, a novel tunable filter is proposed to address the problems associated with conventional tunable filters. This filter incorporates a high-performance gallium arsenide (GaAs) super-abrupt junction capacitor, a metal-insulator-metal (MIM) capacitor, and a 3D solenoid inductor through-gaAs substrate via (TGV). The proposed tunable filter can be used at very high frequencies (e.g., 6 GHz) in applications such as RFFE. The proposed tunable filter allows for the integration of high-Q (HQ) and high-tunability (HTR) tunable resonator / filter devices with a wide range of CMOS / silicon drivers and controllers, as well as RFFE devices such as CMOS charge pumps, low-noise amplifiers (LNAs), switches, etc.

[0024] Some of the unique features of the proposed tunable filter include: • GaAs-enabled tunable filters for, for example, 6GHz Wi-Fi RF front-ends, featuring integrated high-performance variable capacitors, MIM capacitors, and solenoid inductors; • GaAs supermutation junction container with high capacitance tuning ratio (e.g., HTR: Cmax / Cmin>4). • HQ 3D solenoid inductors built on low-loss thermally conductive GaAs substrates, utilizing mature high-volume GaAs through-hole (TGV) technology; • HQ and HTR resonators built on top of the TGV inductor with a super-abrupt junction capacitor; • CMOS charge pump (CHP), controller, LNA and switch chip with die-to-wafer (D2W) integration to tunable RF filter; • High-power processing of filters in the TX path, using GaAs substrates with good thermal conductivity; • Integration schemes with key RFFE devices: (i) an interposer-like approach, (ii) a “CIL”-like approach.

[0025] Figure 1An example tunable filter 100 according to one or more aspects of this disclosure is illustrated. The tunable filter 100 may include a GaAs substrate 110, an upper conductive structure 150 above the GaAs substrate 110, and a lower conductive structure 170 below the GaAs substrate 110. It should be noted that terms or phrases such as “lower,” “upper,” “left,” “right,” “below,” “above,” “horizontal,” “vertical,” etc., are used for convenience. Unless specifically indicated otherwise, such terms / phrases are not intended to indicate absolute orientation or direction. Furthermore, while GaAs is used for descriptive purposes, other group III-V compounds are contemplated for use.

[0026] In short, components (e.g., GaAs variable capacitor 120, MIM capacitor 130, 3D inductor 140, etc.) can be formed in the upper conductive structure 150, the lower conductive structure 170 serves as a redistribution layer and provides connectivity to external devices, and the GaAs substrate 110 can provide electrical coupling between the upper conductive structure 150 and the lower conductive structure 170.

[0027] A GaAs variable capacitor (variable capacitor) 120 can be formed in the upper conductive structure 150. The GaAs variable capacitor (variable capacitor) 120 is a capacitor whose capacitance can be controlled by the application of voltage. The illustrated GaAs variable capacitor 120 may include a GaAs buffer layer 122, a GaAs active layer 124, and a variable capacitor contact 126. The GaAs buffer layer 122 is disposed on the upper surface 112 of the GaAs substrate 110. That is, the GaAs buffer layer 122 can be in contact with the GaAs substrate 110. The GaAs buffer layer 122 may be n+ doped.

[0028] The n-doped GaAs active layer 124 can be disposed on the GaAs buffer layer 122. The GaAs active layer 124 can be hypermutated. Therefore, the GaAs variable capacitor 120 can also be referred to as a hypermutated (HA) GaAs variable capacitor. The GaAs active layer 124 can be mesa-shaped. Variable capacitor contacts 126 can be disposed on the GaAs active layer 124. In one aspect, the variable capacitor contacts 126 can be Schottky contacts.

[0029] Note that the GaAs active layer 124 does not completely cover the GaAs buffer layer 122. Ohmic contacts (the upper contacts of the upper conductive structure 150, explained further below) can be formed on the portions of the GaAs buffer layer 122 not covered by the GaAs active layer 124. The ohmic contacts can be used as cathode contacts, meaning that the transformer contact 126 can be used as an anode contact. As can be seen, the GaAs transformer 120 can be encapsulated by one or more upper insulators of the upper conductive structure 150 (also explained further below). Although one GaAs transformer 120 is illustrated, any number of GaAs transformers 120 can be formed.

[0030] GaAs substrate 110 may include one or more GaAs vias (TGVs) 160, which are formed in one or more vias 115 within the GaAs substrate 110. The conductive TGVs 160 may extend the entire height of the GaAs substrate 110, i.e., from the upper surface 112 to the lower surface 114. The TGVs 160 may be configured to electrically couple one or more of the GaAs variable capacitor 120, the MIM capacitor 130, and the 3D inductor 140 to a lower RDL 190 formed in the lower conductive structure 170.

[0031] Each TGV 160 may include a conductive post 162, which fills a corresponding via 115 and may extend from the upper surface 112 to the lower surface 114 within the via 115. The conductive post 162 may be formed of copper (Cu), silver (Ag), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), or a combination thereof. In one aspect, the conductive post 162 and the lower RDL 190 of the lower conductive structure 170 may be formed of the same material. In fact, they may be integrally formed.

[0032] Each TGV 160 may further include a conductive layer 164 vertically disposed on the wall 116 of the via 115, such that conductive pillars 162 are disposed on and inside the conductive layer 164 within the via 115. The conductive layer 164 may also be horizontally disposed between a corresponding conductive pillar 162 and one of the first upper conductors 152 of the upper conductive structure 150. Alternatively or otherwise, the conductive layer 164 may be horizontally disposed between the lower surface 114 of the GaAs substrate 110 and the lower RDL 190 formed in the lower conductive structure 170. The conductive layer 164 of the GaAs substrate may be formed by depositing a TiW seed layer, followed by depositing gold (Au), copper (Cu), or a combination thereof. The first conductive layer 164 of Au can typically be used in GaAs production lines. When the first conductive layer 164 is not provided, the conductive pillars 162 may be disposed on the wall 116 and on the first upper conductor 152.

[0033] Note that the TGV 160 (and specifically the conductive pillar 162) may also have a central cavity 165 filled with an insulating plug 161. The insulating plug 161 may extend from below the lower surface 114, but not completely to the upper surface 112 of the GaAs substrate 110. That is, the insulating plug 161 may extend from below the lower surface 114 to below the upper surface 112. In one aspect, the insulating plug 161 and the lower insulator 171 of the lower conductive structure 170 may be formed of the same material. In fact, they may be formed integrally.

[0034] A lower conductive structure 170, which may be disposed on the lower surface 114 of a GaAs substrate 110, may include one or more lower conductors 172 and one or more lower insulators 171, configured to form a lower redistribution layer (RDL) 190. That is, the lower RDL 190 may include one or more lower conductors 172. In one aspect, the one or more lower conductive layers and one or more lower insulating layers may be patterned to form a lower RDL 190 including one or more lower conductors 172.

[0035] The lower RDL 190 and thus one or more lower conductors 172 can be disposed on the lower surface 114 of the GaAs substrate 110. The lower conductors 172 can be formed of copper (Cu), silver (Ag), gold (Au), aluminum (Al), or a combination thereof. In fact, as described above, the lower RDL 190 and the conductive pillars 162 of the TGV 160 can be formed of the same material.

[0036] One or more insulators 171 may be disposed on the lower surface 114 of the GaAs substrate 110 and on the lower RDL 190 (i.e., on the lower conductor 172). The lower insulator 171 may be formed of any one or more of silicon dioxide (SiO2), organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), silicon-based polymer dielectric, or combinations thereof. Note that the insulating plug 161 of the TGV 160 may also be formed of the same material.

[0037] In one aspect, one or more external connectors 195 may be disposed on the lower surface of some of the lower conductors 172. More generally, external connectors 195 may be disposed on the lower RDL 190. External connectors 195 may be configured to electrically couple the lower RDL 190 to one or more components outside the tunable filter 100. In this way, external connectors 195 may provide an electrical coupling path between the external components and the components of the tunable filter 100 (GaAs capacitor 120, MIM capacitor 130, and / or 3D inductor 140). One or more external connectors 195 may be any one or more of wafer-level package (WLP) balls, copper (Cu) pillars, and solder bumps. In one aspect, the lower insulator 171 may be configured to encapsulate one or more external connectors 195, except for the portion of the lower surface of the lower RDL 190 on which one or more external connectors 195 are disposed.

[0038] An upper conductive structure 150, which may be disposed on the upper surface 112 of the GaAs substrate 110, may include one or more upper conductors and one or more upper insulators, both of which may be configured to form passive components such as multiple MIM capacitors 130 and multiple 3D inductors 140. As described above, a GaAs variable capacitor 120 may be formed within the upper conductive structure 150. The GaAs variable capacitor 120, the MIM capacitor 130, and the 3D inductor 140 may be electrically coupled to form a radio frequency (RF) filter circuit.

[0039] On one hand, multiple upper conductive layers can be patterned to form upper conductors. For example, such as Figure 1 As shown, the first upper conductive layer can be patterned to form one or more first upper conductors 152, the second upper conductive layer can be patterned to form one or more second upper conductors 154, the third upper conductive layer can be patterned to form one or more third upper conductors 156, and the fourth upper conductive layer can be patterned to form one or more fourth upper conductors 158. This is just an example, and the actual number of upper conductive layers is not limited to four.

[0040] The conductive material of each of the upper conductive layers (and thus the upper conductors) can vary. For example, each of the first to fourth upper conductors can be formed of copper (Cu), silver (Ag), gold (Au), aluminum (Al), or a combination thereof.

[0041] Similarly, multiple upper insulating layers can be patterned to form an upper insulator. Again, for example, such as... Figure 1As shown, the first upper insulating layer can be patterned to form one or more first upper insulators 153, the second upper insulating layer can be patterned to form one or more second upper insulators 155, the third upper insulating layer can be patterned to form one or more third upper insulators 157, and the fourth upper insulating layer can be patterned to form one or more fourth upper insulators 159.

[0042] This is an example, and the actual number of upper insulating layers does not have to be limited to 4. This is an illustration of the flexibility in the number of insulating layers. Figure 1 A zeroth upper insulating layer is also shown, which can be patterned to form one or more zeroth upper insulators 151 disposed on the upper surface 112 of the GaAs substrate 110. If applied, the zeroth upper insulator 151 can help mitigate leakage current. However, the disclosed tunable filter 100 will still function well even without the zeroth upper insulator 151. That is, the zeroth upper insulator 151 is optional.

[0043] The insulating material constituting each of the upper insulating layers (and thus constituting an upper insulator) can vary and may include a dielectric. For example, each of the first (or zeroth) to fourth upper insulators may be formed of silicon dioxide (SiO2), an organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polybenzoxazole (PBO), polytetrafluoroethylene (PTFE), a silicone-based polymer dielectric, or a combination thereof.

[0044] One or more of the first upper conductors 152 can be disposed on corresponding one or more TGVs in TGV 160. Note that the first upper conductors 152 can be used to provide electrical connectivity to TGV 160 for components within the upper conductive structure 150. For example, one of the first upper conductors 152 can be configured to electrically couple the GaAs buffer layer 122 of GaAs transformer 120 to one of the TGVs in TGV 160.

[0045] One or more of the second upper conductors 154 can be arranged on or above one or more corresponding first upper conductors 152. That is, some second upper conductors 154 can be in contact with their corresponding first upper conductors 152. However, for some other second upper conductors 154, a first upper insulator 153 can be formed between the first upper conductor 152 and the second upper conductor 154. In other words, one or more first upper insulators 153 can be arranged on their corresponding one or more first upper conductors 152. In one aspect, this can occur in the region of the upper conductive structure 150 forming the MIM capacitor 130. When present, the first upper insulator 153 can prevent electrical coupling between the first upper conductor 152 and the second upper conductor 154.

[0046] One or more third upper conductors 156 may be disposed on or above one or more corresponding second upper conductors 154. That is, some third upper conductors 156 may be in contact with their corresponding second upper conductors 154. For other third upper conductors 156, a second upper insulator 155 may be present between the second upper conductors 154 and the third upper conductors 156. That is, one or more second upper insulators 155 may be disposed on their corresponding one or more second upper conductors 154. Similarly, this may occur in the region of the upper conductive structure 150 forming the MIM capacitor 130. When present, the second upper insulator 155 can prevent electrical coupling between the second upper conductors 154 and the third upper conductors 156.

[0047] One or more fourth upper conductors 158 may be arranged on one or more third upper conductors 156. In one aspect, the fourth upper conductor 158 may serve as an upper RDL 180 to provide electrical coupling within the upper conductive structure 150. For example, the fourth upper conductor 158 may provide an electrical path to apply voltage to the GaAs transformer 120. Note that one of the fourth upper conductors 158 may be electrically coupled to the GaAs buffer layer 122 (the cathode of the GaAs transformer 120), and another of the fourth upper conductors 158 may be electrically coupled to the transformer contact 126 (the anode of the GaAs transformer 120).

[0048] One or more of the first upper insulators 153 may be disposed on the upper surface 112 of the GaAs substrate 110, or may be disposed on one or more zeroth upper insulators 151 (if present). One or more second upper insulators 155 are disposed on one or more first upper insulators 153 to at least partially passivate the GaAs capacitor 120. Also as described above, some of the first upper insulators 153 may be disposed between the first upper conductor 152 and the second upper conductor 154, and one or more second upper insulators 155 may be disposed between the second upper conductor 154 and the third upper conductor 156, for example, in the region forming the MIM capacitor 130.

[0049] One or more third upper insulators 157 can be formed by patterning a third upper insulating layer. The third upper insulator 157 can be disposed on or above a GaAs substrate to encapsulate the first upper conductor 152, the second upper conductor 154, and the third upper conductor 156. One or more fourth upper insulators 159 can be formed by patterning a fourth upper insulating layer. The fourth upper insulator 159 can be disposed on the fourth upper conductor 158 and the third upper insulator 157. In one aspect, the fourth insulating layer can completely cover the upper surface of the fourth upper conductor 158 electrically coupled to the MIM capacitor 130, and completely cover the fourth upper conductor 158 forming the 3D inductor 140.

[0050] In one aspect, one or more contact pads 185 may be disposed on one or more fourth upper conductors 158. The contact pads 185 may be exposed above the fourth insulating layer. More generally, external connectors 195 may be disposed on the lower RDL 190. The contact pads 185 may be configured to electrically couple the fourth upper conductor 158 to one or more components external to the tunable filter 100. In this way, the contact pads 185 may provide an electrical coupling path between the external components and components of the tunable filter 100 (GaAs transformer 120, MIM capacitor 130, and / or 3D inductor 140). One or more contact pads 185 may be formed of copper (Cu), silver (Ag), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), or combinations thereof.

[0051] The MIM capacitor 130 may include a lower plate 134, an upper plate 136, and a dielectric 135 disposed between the lower plate 134 and the upper plate 136. In one aspect, one of the second upper conductors 154 may serve as the lower plate 134, one of the second upper insulators 155 may serve as the dielectric 135, and one of the third upper conductors 156 may serve as the upper plate 136.

[0052] The MIM capacitor 130 can be electrically coupled to the GaAs transformer 120 and the 3D inductor 140. In this particular example, Figure 1 The diagram illustrates the lower plate 134 coupled to the GaAs transformer 120 and the upper plate coupled to the 3D inductor 140. However, the reverse is also possible. That is, typically, one of the lower plate 134 and the upper plate 136 can be electrically coupled to one of the GaAs transformer 120 and the 3D inductor 140, and the other of the lower plate 134 and the upper plate 136 can be electrically coupled to the other of the GaAs transformer 120 and the 3D inductor 140.

[0053] For electrical integrity, note that one of the first upper insulators 153 may be arranged above and below the lower electrode 134 such that the lower electrode 134 does not contact any of the first upper conductor 152. Although one MIM capacitor 130 is illustrated, any number of MIM capacitors 130 may be used.

[0054] The 3D inductor 140 may include one or more loops. In one aspect, each loop of the 3D inductor 140 may include multiple loop segments—an upper horizontal loop segment 142, a first vertical loop segment 144, a second vertical loop segment 146, and a lower horizontal loop segment 148—in Figure 1 Highlighted by a dashed box. The upper horizontal loop segment 142 may include one of the fourth upper conductors 158, the first vertical loop segment 144 may include one TGV 160, the second vertical loop segment 146 may include another TGV 160, and the lower horizontal loop segment 148 includes one of the lower conductors 172 constituting the lower RDL 190. In this example, the first vertical loop segment 144 and the second vertical loop segment 146 may also include their respective first upper conductor 152, second upper conductor 154, and third upper conductor 156.

[0055] Although one 3D inductor 140 is illustrated, any number of 3D inductors 140 can exist. Furthermore, although only one loop is illustrated, any number of loops can exist for a 3D inductor 140. Moreover, the number of loops in one 3D inductor 140 can be independent of the number of loops in another 3D inductor 140.

[0056] The tunable filter 100 can be integrated with one or more radio frequency front-end (RFFE) devices, such as... Figure 2A and Figure 2BAs shown in the figures. For simplicity, details of the tunable filter 100 are omitted from these figures. When electrically coupled to the tunable filter 100, the RFFE device can control the tunable filter 100. The RFFE device can be fabricated as a CMOS device and may include a charge pump / controller 210, a low-noise amplifier (LNA) 220, a switch 230, etc. When the RFFE device and the tunable filter 100 are integrated, the RFFE device can be electrically coupled to any of the GaAs transformer 120, MIM capacitor 130, and 3D inductor 140 via external connectors 195 and / or contact pads 185.

[0057] Figure 2A The illustration shows apparatus 200A, which depicts an example result of a method for integration using a similar mediator layer. In this method, individual RFFE devices (any one or more of the charge pump / controller 210, LNA 220, switch 230, etc.) can be electrically coupled to tunable filter 100 via one or more contact pads 185.

[0058] Figure 2B The illustration shows apparatus 200B, which depicts an example result of a similar intermediary layer method for integration. In this method, individual RFFE functions can be combined into a single RFFE device 240. That is, the functions of charge pump / controller 210, LNA 220, switch 230, etc., can be combined into a single RFFE device 240. The single RFFE device 240 can be integrated with one or more tunable filters 100. That is, the single RFFE device 240 itself can be configured to be electrically coupled to multiple tunable filters 100.

[0059] Figures 3A-5F The illustration depicts example stages of manufacturing a tunable filter according to one or more aspects of this disclosure. In summary, Figures 3A-3G The diagram illustrates the stages associated with the formation of the GaAs variable container 120. Figures 4A-4F The diagram illustrates the stages associated with forming passive components (MIM capacitor 130, 3D inductor 140), and Figures 5A-5F The diagram illustrates the stages associated with the formation of the TGV 160 and the lower conductive structure 170. The GaAs variable capacitor 120 is formed ( Figures 3A-3G ) and passive components 130, 140 ( Figures 4A-4F This can be referred to as the front-side process, and it forms TGV 160 and the lower conductive structure 170. Figures 5A-5F This can be referred to as the back-side process.

[0060] Figure 3AThe illustration shows a stage in which an n+-doped GaAs layer 322 can be deposited on the upper surface 112 of a GaAs substrate 110, and an n-doped GaAs layer 324 can be deposited on the n+-doped GaAs layer 322. The n+-doped GaAs layer 322 and / or the n-doped GaAs layer 324 can be epitaxial layers deposited via metal-organic chemical vapor deposition (MOCVD). The n-doped GaAs layer 324 can be hypermutated.

[0061] Figure 3A The illustration shows a stage in which an n+-doped GaAs layer 322 can be deposited on the upper surface 112 of a GaAs substrate 110, and an n-doped GaAs layer 324 can be deposited on the n+-doped GaAs layer 322. The n+-doped GaAs layer 322 and / or the n-doped GaAs layer 324 can be epitaxial layers grown by metal-organic chemical vapor deposition (MOCVD). The n-doped GaAs layer 324 can be hypermutated.

[0062] Figure 3B The diagram illustrates a stage in which the variable capacitor contact 126 can be formed on the n-doped GaAs layer 324. The variable capacitor contact 126 can be a Schottky contact.

[0063] Figure 3C The illustration shows a stage in which the n-doped GaAs layer 324 is etched into a mesa shape to form the GaAs active layer 124.

[0064] Figure 3D The illustration shows a stage in which the n+ doped GaAs layer 324 is etched to form a GaAs buffer layer 122. The GaAs buffer layer 122 can be patterned for use as a cathode contact.

[0065] Figure 3E The diagram illustrates a stage in which ohmic contacts can be formed on the GaAs substrate 110 and on the GaAs buffer layer 122. The ohmic contact can be one of the first upper conductors 152 of the upper conductive structure 150.

[0066] Figure 3F Similar to Figure 3E This is because it illustrates the stages at which ohmic contacts can be formed on GaAs substrate 110 and on GaAs buffer layer 122. The difference lies in... Figure 3F In this process, a zero-insulating layer 351 can be deposited on the GaAs substrate 110. On one hand, Figure 3E and Figure 3F It can be considered an alternative.

[0067] Figure 3GThe illustration depicts a stage in which the GaAs variable capacitor 120 can be passivated using one or more upper insulators (e.g., a first upper insulator 153 and a second upper insulator 155) of the upper conductive structure 150. Figure 3G The zeroth insulating layer 351 is shown. Therefore, Figure 3G Can be regarded as Figure 3F The subsequent stages. However, although not shown, the GaAs variable capacitor 120 can be used in the absence of the zeroth insulating layer 351. Figure 3E It is passivated in the subsequent stages.

[0068] Figure 4A The illustration shows a stage in which a first upper conductive layer can be deposited and patterned to form a first upper conductor 152 disposed on the upper surface 112 of the GaAs substrate 110. Figure 4A The illustration also shows that a first upper insulating layer 453 (e.g., a dielectric layer) can be deposited on top to horizontally fill the space between the first upper conductors 152.

[0069] Figure 4A The diagram shows that the zeroth insulating layer 351 can be patterned as a zeroth upper insulator 151, which is horizontally disposed on the GaAs substrate 110 between the first upper conductors 152, and a first upper insulating layer 453 (patterned to form the first upper insulator 153) can be disposed on the zeroth upper insulator 151. Alternatively, when the zeroth upper insulator 151 is absent, the first upper insulating layer 453 can be horizontally disposed on the GaAs substrate 110 between the first upper conductors 152 (not shown).

[0070] Figure 4B The illustration depicts a stage in which one or more first upper insulators 153 and one or more second upper conductors 154 may be formed. As can be seen, the first upper insulating layer 453 may be patterned to form the first upper insulator 153 on some of the first upper conductors 152. Furthermore, the second upper conductors 154 may be formed, for example, by depositing and patterning a second upper conductive layer. Some of the second upper conductors 154 may contact their corresponding first upper conductors 152, and other second upper conductors 154 may have first upper insulators 153 between them and their corresponding first upper conductors 152 (e.g., in the region forming the MIM capacitor 130). That is, the second upper conductors 154 may be arranged on or above their first upper conductors 152.

[0071] Figure 4CThe illustration shows a stage in which one or more second upper insulators 155 and one or more third upper conductors 156 can be formed. To form the second upper insulator 155, a second upper insulating layer can be deposited and patterned. The second upper insulator 155 can be disposed on or above a first upper insulator 153. Where the MIM capacitor 130 is formed, one of the second upper insulators 155 (configured to serve as dielectric 135) can be disposed on a second upper conductor 154 (serving as lower electrode 134).

[0072] To form the third upper conductor 156, a third upper conductive layer can be deposited and patterned. The third upper conductor 156 can be disposed on or above the second upper conductor 154. Where the MIM capacitor 130 is formed, one of the third upper conductors 156 (configured to serve as an upper plate 136) can be disposed on the second upper insulator 155 (serving as a dielectric 135).

[0073] Figure 4D The illustration shows a stage in which one or more third upper insulators 157 may be formed. To form the third upper insulator 157, a third upper insulating layer may be deposited and patterned. The third upper insulating layer may be an interlayer dielectric (ILD) such as polyimide. The third upper insulating layer may be patterned to expose the upper surface of the third upper conductor 156.

[0074] Figure 4E The illustration shows a stage in which one or more fourth upper conductors 158 may be formed. To form the fourth upper conductor 158, a fourth conductive layer may be deposited and patterned. For example, a very thick copper (Cu) layer may be deposited and patterned. The fourth upper conductor 158 may be disposed on the third upper conductor 156 to provide electrical coupling among components within the upper conductive structure 150. Therefore, the fourth upper conductor 158 can be considered to function as an upper RDL 180.

[0075] Figure 4F The illustration shows a stage in which tunable filter components (e.g., GaAs variable capacitor 120, MIM capacitor 130, 3D inductor 140, etc.) can be passivated. For example, a fourth upper insulating layer can be deposited and patterned to form one or more fourth upper insulators 159 to encapsulate the fourth upper conductor 158.

[0076] To provide connectivity to external components such as RFFE devices, the upper surfaces of some of the fourth upper conductors 158 may be left exposed, and one or more contact pads 185 may be formed on the exposed fourth upper conductors 158.

[0077] Figure 5A The illustration shows a stage in which the GaAs substrate 110 can be brought to the desired height. For example, a back-side grinding process can be performed on the back side of the GaAs substrate 110 (the side opposite to the upper surface 112).

[0078] Figure 5B The illustration shows a stage in which the GaAs substrate 110 can be etched to form a via (i.e., a hole) 115 within the GaAs substrate. For example, deep reactive ion etching (DRIE) can be performed. A first upper conductor 152 can be used as an etch stop. That is, the first upper conductor 152 of the upper conductive structure 150 can be exposed.

[0079] Figure 5C The illustration shows a stage in which conductive layer 164 may be formed on the wall 116 of via 115, on the exposed first upper conductor 152, and on portions of the lower surface 114 of GaAs substrate 110. For example, conductive layer 164 may be plated. As described above, conductive layer 164 may be optional.

[0080] Figure 5D The illustration shows a stage in which conductive pillars 162 and a lower RDL 190 (which includes a lower conductor 172) can be formed. For example, a thick metal layer (e.g., Cu) can be deposited and patterned. The metal layer can be deposited and patterned such that a central cavity 165 is formed within the conductive pillars 162. This completes the loop of the 3D inductor 140 when the lower conductor 172 is formed.

[0081] Figure 5E The illustration shows a stage in which the lower RDL 190 (lower conductor 172) can be passivated. For example, a lower insulating layer can be deposited and patterned to form one or more lower insulators 171 disposed on the lower surface 114 of the GaAs substrate 110 and on the lower RDL 190. The lower insulating layer can also be patterned to form an insulating plug 161 filling the central cavity 165.

[0082] Figure 5F The illustration shows a stage in which one or more external connections 195 may be formed. To provide external connectivity, some lower surfaces of the lower conductor 172 may be left exposed, and one or more external connections 195 may be formed on the exposed lower conductor 172.

[0083] Figure 6The illustration shows a flowchart of an example method 600 for fabricating a tunable filter (such as tunable filter 100). In block 610, a GaAs variable capacitor 120 may be formed on the upper surface of a GaAs substrate 110.

[0084] Figure 7 A flowchart illustrating an example process for implementing block 610 is shown. In block 710, an n+ doped GaAs layer 322 can be deposited on the upper surface 112 of the GaAs substrate 110, and an n-doped GaAs layer 324 can be deposited on the n+ doped GaAs layer 322. The n-doped GaAs layer 324 can be hyper-amplified. Block 710 can correspond to Figure 3A .

[0085] In block 720, a variable capacitor contact 126 can be formed on the n-doped GaAs layer 324. Block 720 can correspond to Figure 3B .

[0086] In box 730, the n-doped GaAs layer 324 can be etched into, for example, a mesa shape to form the GaAs active layer 124. Box 730 can correspond to Figure 3C .

[0087] In box 740, the n+ doped GaAs layer 322 can be patterned to form the GaAs buffer layer 122. Box 740 can correspond to Figure 3D .

[0088] In block 750, ohmic contacts can be formed on the GaAs substrate 110 and on the GaAs buffer layer 122. For example, one of the first upper conductors 152 of the upper conductive structure 150 can be formed as an ohmic contact. Block 750 can correspond to Figure 3E or Figure 3F .

[0089] In block 760, the GaAs transformer 120 can be passivated using one or more of the upper insulators of the upper conductive structure 150. For example, a first upper insulator 153 and a second upper insulator 155 can be used for passivation. Block 760 can correspond to Figure 3G .

[0090] Return to reference Figure 6 In block 620, the upper conductive structure 150 may be formed and disposed on the upper surface 112 of the GaAs substrate 110. The upper conductive structure 150 may include one or more upper conductors and one or more upper insulators, which are configured to form one or more passive components including a MIM capacitor 130 and a 3D inductor 140.

[0091] Figure 8 A flowchart illustrating an example process for implementing block 620 is shown. In block 805, a zeroth upper insulating layer can be deposited and patterned to form one or more zeroth upper insulators 151. Block 805 may correspond to Figure 3F Since the zeroth upper insulator 151 is optional, the frame 805 can also be optional.

[0092] In block 810, a first upper conductive layer can be deposited and patterned to form one or more first upper conductors 152 disposed on the upper surface 112 of the GaAs substrate 110. In block 820, a first upper insulating layer can be deposited and patterned to form one or more first upper insulators 153 disposed on one or more first upper conductors among the first upper conductors 152 and / or on the upper surface of the GaAs substrate. Blocks 810 and 820 may correspond to Figure 4A and Figure 4B .

[0093] In block 830, a second upper conductive layer can be deposited and patterned to form one or more second upper conductors 154 disposed on or above one or more first upper conductors 152. Block 830 may correspond to Figure 4B .

[0094] In block 840, a second upper insulating layer can be deposited and patterned to form one or more second upper insulators 155 disposed on or above one or more first upper insulators 153. In block 850, a third upper conductive layer can be deposited and patterned to form one or more third upper conductors 156 disposed on one or more second upper conductors 154. Note that after block 850, a MIM capacitor 130 (lower plate 134, upper plate 136, and dielectric 135) is formed. Blocks 840 and 850 may correspond to Figure 4C .

[0095] In frame 860, a third upper insulating layer can be deposited and patterned to form one or more third upper insulators 157, the third upper insulators 157 being configured to expose the upper surfaces of one or more third upper conductors 156. Frame 860 may correspond to... Figure 4D .

[0096] In frame 870, a fourth upper conductive layer can be deposited and patterned to form one or more fourth upper conductors 158 disposed on one or more third upper conductors 156. Frame 870 may correspond to... Figure 4E .

[0097] In frame 880, a fourth upper insulating layer can be deposited and patterned to form one or more fourth upper insulators 159, the fourth upper insulators 159 being configured to encapsulate a plurality of fourth upper conductors 158. In frame 890, one or more contact pads 185 can be formed on one or more of the fourth upper conductors 158. Frames 880 and 890 may correspond to... Figure 4F .

[0098] Return to reference Figure 6 In block 630, one or more TGV 160s may be formed through the GaAs substrate 110 from the upper surface 112 to the lower surface 114. In block 640, a lower conductive structure 170 is disposed on the lower surface 114 of the GaAs substrate 110. The lower conductive structure 170 may include one or more lower conductors 172 and one or more lower insulators 171, which are configured to form a lower RDL 190.

[0099] Figure 9 The diagram illustrates a flowchart of an example process for implementing blocks 630 and 640. In block 910, the back side of the GaAs substrate 110 can be milled to give the GaAs substrate 110 a desired height or thickness, for example, 50 μm-100 μm. Block 910 can correspond to... Figure 5A .

[0100] In frame 920, one or more vias 115 can be formed, for example, by DRIE etching of the GaAs substrate 110. The vias 115 can expose one or more first upper conductors 152 of the upper conductive structure 150. Frame 920 can correspond to... Figure 5B .

[0101] In frame 930, a conductive layer 164 can be formed by thinly depositing a conductive material (e.g., Au) onto the wall 116 of the via 115, the exposed first upper conductor 152, and a portion of the lower surface 114 of the GaAs substrate 110. Frame 930 can correspond to... Figure 5C .

[0102] In frame 940, a conductive layer 164 and the lower surface 114 of the GaAs substrate 110 can be thickly plated using a conductive material to form a conductive pillar 162 within each via 115 and to form a lower conductor 172 (lower RDL 190). Each conductive pillar 162 can be formed with a central cavity 165. Frame 940 can correspond to... Figure 5D .

[0103] In frame 950, a lower insulating layer can be deposited and patterned to form one or more lower insulators 171 disposed on the lower surface 114 of the GaAs substrate 110 and on the lower RDL 190. In doing so, an insulating plug 161 configured to fill the central cavity 165 of the conductive pillar 162 can be formed. Frame 950 may correspond to... Figure 5E .

[0104] In frame 960, one or more external connectors 195 may be formed on one or more lower conductors 172. Frame 960 may correspond to... Figure 5F .

[0105] It should be understood that the foregoing manufacturing processes and related discussions are provided only as a general illustration of some aspects of this disclosure and are not intended to limit this disclosure or the appended claims. Furthermore, many details of the manufacturing processes known to those skilled in the art may have been omitted or combined in the summary process section to aid in understanding the disclosed aspects without requiring a detailed reproduction of every detail and / or all possible process variations. Moreover, it should be understood that the illustrated configurations and descriptions are provided only to aid in interpreting the various aspects disclosed herein. For example, the number and location of MIM capacitors and / or inductors; the metallization structure may have more or fewer conductive and insulating layers; the orientation, size, whether multiple cavities are formed, whether it is enclosed or open; and other aspects may vary, driven by application-specific design features such as the number of antennas, antenna type, frequency range, power, etc. Therefore, the foregoing illustrative examples and associated drawings should not be construed as limiting the aspects disclosed herein and claimed.

[0106] Figure 10 The illustrations depict various electronic devices that can be integrated with any of the aforementioned on-glass antenna devices according to various aspects of this disclosure. For example, mobile phone device 1002, laptop computer device 1004, and fixed location terminal device 1006 can generally be considered as user equipment (UE) and may include a tunable filter 100 as described herein. Figure 10The devices 1002, 1004, and 1006 illustrated in the figure are merely exemplary. Other electronic devices may also include the tunable filter 100, including but not limited to the group of devices (e.g., electronic devices), which includes: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as watch-reading devices, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0107] The devices and functions disclosed above can be designed and configured as computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of these files can be provided to a manufacturing processor, who then manufactures the device based on these files. The resulting product may include a semiconductor wafer, which is then diced into semiconductor dies and packaged into an on-glass antenna device. The on-glass antenna device can then be employed in the device described herein.

[0108] The following provides an overview of examples of this disclosure: Example 1: A tunable filter includes: a gallium arsenide (GaAs) substrate; a variable capacitor (variable capacitor) disposed on an upper surface of the GaAs substrate; an upper conductive structure disposed on the upper surface of the GaAs substrate, the upper conductive structure including one or more upper conductors and one or more upper insulators, the one or more upper conductors and the one or more upper insulators being configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor; one or more GaAs vias (TGVs) disposed through the GaAs substrate from the upper surface to a lower surface of the GaAs substrate; and a lower conductive structure disposed on the lower surface of the GaAs substrate, the lower conductive structure including one or more lower conductors and one or more lower insulators, the one or more lower conductors and the one or more lower insulators being configured to form a lower redistribution layer (RDL), wherein the variable capacitor, the MIM capacitor, and the 3D inductor are electrically coupled to form a radio frequency (RF) filter circuit.

[0109] Example 2: The tunable filter according to Example 1, wherein the lower RDL is configured to electrically couple at least one TGV to at least one other TGV.

[0110] Example 3: The tunable filter according to Example 2 further includes: one or more external connectors configured to electrically couple the lower RDL to one or more components outside the tunable filter.

[0111] Example 4: The tunable filter according to Example 3, wherein the one or more external connectors are one or more of wafer-level package (WLP) balls, copper (Cu) pillars, and solder bumps.

[0112] Example 5: A tunable filter according to Examples 1 to 4, wherein one or more of the TGVs are configured to electrically couple one or more of the variable capacitor, the MIM capacitor, and the 3D inductor to the lower RDL.

[0113] Example 6: The tunable filter according to Example 5, wherein each TGV includes a conductive post arranged to fill a via of the GaAs substrate, the conductive post extending within the via from the upper surface of the GaAs substrate to the lower surface of the GaAs substrate.

[0114] Example 7: The tunable filter according to Example 6, wherein the conductive pillar is formed of any one or more of copper (Cu), silver (Ag), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), or combinations thereof.

[0115] Example 8: The tunable filter according to Examples 6 and 7, wherein the conductive pillars and the lower RDL are formed of the same one or more conductive materials.

[0116] Example 9: A tunable filter according to Examples 6 to 8, wherein each TGV further includes a conductive layer disposed vertically on the wall of the GaAs substrate, such that the conductive pillar is disposed within the via on the conductive layer and inside the conductive layer.

[0117] Example 10: The tunable filter according to Example 9, wherein the conductive layer of the TGV is horizontally disposed between the corresponding conductive pillar and the first upper conductor of the upper conductive structure, and / or wherein the conductive layers of the same or different TGVs are horizontally disposed between the lower surface of the GaAs substrate and the lower RDL.

[0118] Example 11: A tunable filter according to Examples 6 to 10, wherein each TGV further includes an insulating plug configured to fill a central cavity within the conductive pillar, the insulating plug extending from below the lower surface of the GaAs substrate to below the upper surface of the GaAs substrate.

[0119] Example 12: The tunable filter according to Example 11, wherein the insulating plug and the one or more insulators of the lower conductive structure are formed of the same one or more insulating materials.

[0120] Example 13: A tunable filter according to Examples 1 to 12, wherein the lower RDL of the lower conductive structure is disposed on the lower surface of the GaAs substrate, and wherein one or more insulators of the lower conductive structure are disposed on the lower surface of the GaAs substrate and on the lower RDL.

[0121] Example 14: The tunable filter according to Example 13, wherein the one or more lower insulators are formed of any one or more of the following: silicon dioxide (SiO2), organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or silicon-based polymer dielectric.

[0122] Example 15: The tunable filter according to Examples 13 to 14 further includes: one or more external connectors disposed on the lower surface of the lower RDL and configured to electrically couple the lower RDL to one or more components outside the tunable filter, wherein the one or more lower insulators are configured to enclose the one or more external connectors except for the portion of the lower surface of the lower RDL on which the one or more external connectors are disposed.

[0123] Example 16: A tunable filter according to Examples 1 to 15, wherein the variable container is a super-mutation (HA) variable container.

[0124] Example 17: The tunable filter according to Example 16, wherein the variable capacitor comprises: a GaAs buffer layer disposed on the upper surface of the GaAs substrate, the GaAs buffer layer being n+ doped; a GaAs active layer disposed on the GaAs buffer layer, the GaAs active layer being n-doped and super-abrupt; and a variable capacitor contact disposed on the GaAs active layer.

[0125] Example 18: A tunable filter according to Example 17, wherein the GaAs active layer is mesa-shaped.

[0126] Example 19: A tunable filter according to Examples 16 to 18, wherein the one or more upper insulating layers of the upper conductive structure at least partially encapsulate the variable capacitor.

[0127] Example 20: A tunable filter according to Examples 1 to 19, wherein the upper conductive structure comprises: one or more first upper conductors disposed on the one or more TGVs; one or more second upper conductors disposed on or above the one or more first upper conductors; one or more third upper conductors disposed on or above the one or more second upper conductors; one or more fourth upper conductors disposed on the one or more third upper conductors; one or more first upper insulators disposed on one or more of the first upper conductors; and one or more second upper insulators disposed on one or more of the first upper conductors and one or more of the first upper insulators.

[0128] Example 21: The tunable filter according to Example 20, wherein the first upper conductor, the second upper conductor, the third upper conductor and / or the fourth upper conductor are formed of any one or more of copper (Cu), silver (Ag), gold (Au), aluminum (Al) or combinations thereof.

[0129] Example 22: A tunable filter according to Examples 20 to 21, wherein one of the first upper conductors is configured to electrically couple the GaAs buffer layer of the variable capacitor to one of the TGVs.

[0130] Example 23: A tunable filter according to Example 22, wherein one of the fourth upper conductors is electrically coupled to the variable capacitor contact of the variable capacitor, and the other of the fourth upper conductors is electrically coupled to the GaAs buffer layer of the variable capacitor.

[0131] Example 24: A tunable filter according to Examples 20 to 23, wherein the MIM capacitor includes: a lower plate; an upper plate; and a dielectric disposed between the lower plate and the upper plate, wherein one of the second upper conductors serves as the lower plate, one of the second upper insulating layers serves as the dielectric, and one of the third upper conductors serves as the upper plate.

[0132] Example 25: A tunable filter according to Example 24, wherein one of the lower plate and the upper plate is electrically coupled to one of the variable capacitor and the 3D inductor, and the other of the lower plate and the upper plate is electrically coupled to the other of the variable capacitor and the 3D inductor.

[0133] Example 26: A tunable filter according to Examples 24 to 25, wherein the lower electrode does not contact any of the first upper conductors in the first upper conductor.

[0134] Example 27: A tunable filter according to Examples 20 to 26, wherein the 3D inductor includes one or more loops, each loop including: an upper horizontal loop segment; a first vertical loop segment and a second vertical loop segment; and a lower horizontal loop segment, wherein the upper horizontal loop segment includes one of the fourth upper conductors, the first vertical loop segment includes one of the TGVs, the second vertical loop segment includes another TGV, and the lower horizontal loop segment includes one of the lower conductors.

[0135] Example 28: A tunable filter according to Examples 20 to 27, wherein the upper conductive structure further comprises: a first insulating layer patterned to form one or more third upper insulators disposed on or above the GaAs substrate to encapsulate the first upper conductor, the second upper conductor, and the third upper conductor; and a second insulating layer patterned to form one or more fourth upper insulators disposed on the one or more fourth upper conductors and the one or more third upper insulators, wherein the second insulating layer completely covers the upper surface of the fourth upper conductor electrically coupled to the MIM capacitor and completely covers the upper surface of the fourth upper conductor forming the 3D inductor.

[0136] Example 29: The tunable filter according to Example 28, wherein the first upper insulator, the second upper insulator, the third upper insulator and / or the fourth upper insulator are formed of one or more of silicon dioxide (SiO2), organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO) or silicon-based polymer dielectric.

[0137] Example 30: The tunable filter according to Examples 28 to 29 further includes: one or more contact pads disposed on one or more of the fourth upper conductors and exposed over the fourth insulating layer, the one or more contact pads being configured to electrically couple one or more of the fourth upper conductors to one or more components outside the tunable filter.

[0138] Example 31: The tunable filter according to Examples 20 to 30, wherein the upper conductive structure further includes: one or more zeroth insulators disposed between the GaAs substrate and one or more first upper conductors and / or disposed between the GaAs substrate and the third insulating layer.

[0139] Example 32: A tunable filter according to Examples 1 to 31, wherein the tunable filter is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, Internet of Things (IoT) devices, laptop computers, servers, and devices in motor vehicles.

[0140] Example 33: An apparatus comprising: a tunable filter; and one or more radio frequency front-end (RFFE) devices configured to control the tunable filter when coupled to it, wherein the tunable filter includes: a gallium arsenide (GaAs) substrate; a variable capacitor (variable capacitor) disposed on an upper surface of the GaAs substrate; and an upper conductive structure disposed on the upper surface of the GaAs substrate, the upper conductive structure including one or more upper conductors and one or more upper insulators, the one or more upper conductors and the one or more upper insulators being configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor; One or more GaAs vias (TGVs) are arranged to pass through the GaAs substrate from the upper surface to the lower surface of the GaAs substrate; and a lower conductive structure is arranged on the lower surface of the GaAs substrate, the lower conductive structure including one or more lower conductors and one or more lower insulators, the one or more lower conductors and the one or more lower insulators being configured to form a lower redistribution layer (RDL), and wherein the one or more RFFE devices are electrically coupled to any one or more of the variable capacitor, the MIM capacitor and the 3D inductor via one or more external connectors and / or one or more contact pads of the tunable filter.

[0141] Example 34: The apparatus according to Example 33, wherein the one or more RFFE devices are CMOS devices.

[0142] Example 35: The apparatus according to Examples 33 to 34, wherein the one or more RFFE devices include one or more of the following: a charge pump / controller, a low-noise amplifier (LNA), and a switch.

[0143] Example 36: The apparatus according to Example 35, wherein the charge pump / controller, the low-noise amplifier (LNA), and the switch are each individually electrically coupled to the tunable filter via the one or more contact pads.

[0144] Example 37: The apparatus according to Examples 35 to 36, wherein the functions of the charge pump / controller, the low-noise amplifier (LNA), and the switch are combined in a single RFFE device.

[0145] Example 38: The apparatus according to Example 37, wherein a single RFFE device is configured to be electrically coupled to a plurality of tunable filters.

[0146] Example 39: A method of manufacturing a tunable filter, the method comprising: forming a variable capacitor (variable capacitor) on an upper surface of a GaAs substrate; forming an upper conductive structure disposed on the upper surface of the GaAs substrate, the upper conductive structure including one or more upper conductors and one or more upper insulators, the one or more upper conductors and the one or more upper insulators being configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor; forming one or more GaAs vias (TGVs) through the GaAs substrate from the upper surface to a lower surface of the GaAs substrate; and forming a lower conductive structure disposed on the lower surface of the GaAs substrate, the lower conductive structure including one or more lower conductors and one or more lower insulators, the one or more lower conductors and the one or more lower insulators being configured to form a lower redistribution layer (RDL), wherein the variable capacitor, the MIM capacitor, and the 3D inductor are electrically coupled to form a radio frequency (RF) filter circuit.

[0147] Example 40: The method according to Example 39, wherein forming the variable capacitor includes: depositing an n+ doped GaAs layer on the upper surface of the GaAs substrate, and depositing an n-doped GaAs layer on the n+ doped GaAs layer, the n-doped GaAs layer being super-abrupt; forming a variable capacitor contact on the n-doped GaAs layer; etching the n-doped GaAs layer into a mesa shape to form a GaAs active layer; patterning the n+ doped GaAs layer to form a GaAs buffer layer; forming an ohmic contact on the GaAs substrate and the GaAs buffer layer using one or more upper conductors of the upper conductor of the upper conductive structure; and passivating the variable capacitor using one or more upper insulators of the upper insulator of the upper conductive structure.

[0148] Example 41: The method according to Examples 39 to 40, wherein forming the upper conductive structure comprises: depositing and patterning a first upper conductive layer to form one or more first upper conductors disposed on the upper surface of the GaAs substrate; depositing and patterning a first upper insulating layer to form one or more first upper insulators disposed on one or more of the first upper conductors and / or on the upper surface of the GaAs substrate; depositing and patterning a second upper conductive layer to form one or more second upper conductors disposed on or above the one or more first upper conductors; depositing and patterning a second upper insulating layer to form one or more second upper conductors disposed on or above the one or more first upper insulators. One or more second upper insulators are deposited on top of the one or more first upper insulators; a third upper conductive layer is deposited and patterned to form one or more third upper conductors disposed on the one or more second upper conductors; a third upper insulating layer is deposited and patterned to form one or more third upper insulators configured to expose the upper surfaces of the one or more third upper conductors; a fourth upper conductive layer is deposited and patterned to form one or more fourth upper conductors disposed on the one or more third upper conductors; and a fourth upper insulating layer is deposited and patterned to form one or more fourth upper insulators configured to encapsulate the one or more fourth upper conductors.

[0149] Example 42: According to the method of Example 41, the MIM capacitor includes: a lower plate; an upper plate; and a dielectric disposed between the lower plate and the upper plate, wherein one of the second upper conductors serves as the lower plate, one of the second upper insulators serves as the dielectric, and one of the third upper conductors serves as the upper plate.

[0150] Example 43: According to the method of Examples 41 to 42, the 3D inductor includes one or more loops, each loop including: an upper horizontal loop segment; a first vertical loop segment and a second vertical loop segment; and a lower horizontal loop segment, wherein the upper horizontal loop segment includes one of the fourth upper conductors, the first vertical loop segment includes one of the TGVs, the second vertical loop segment includes another TGV, and the lower horizontal loop segment includes one of the lower conductors.

[0151] Example 44: The method according to Examples 41 to 43 further includes: forming one or more contact pads on one or more of the fourth upper conductors.

[0152] Example 45: The method according to Examples 39 to 44, wherein forming the one or more TGVs and forming the lower conductive structure comprises: grinding the back side of the GaAs substrate; etching the GaAs substrate to form one or more vias, the one or more vias exposing one or more first upper conductors of the first upper conductors of the upper conductive structure; depositing a conductive material over the walls of the one or more vias, the exposed one or more first upper conductors of the first upper conductors, and a portion of the lower surface of the GaAs substrate to form a conductive layer; depositing a conductive material over the conductive layer and the lower surface of the GaAs substrate to form a conductive pillar within each via and within the lower RDL, wherein each conductive pillar is formed to have a central cavity; depositing and patterning a lower insulating layer to form one or more lower insulators disposed on the lower surface of the GaAs substrate and on the lower RDL; and forming one or more insulating plugs configured to fill the central cavity of the conductive pillar, wherein each TGV includes one conductive pillar and the corresponding insulating plug.

[0153] Example 46: The method according to Example 45, wherein forming the one or more TGVs and forming the lower conductive structure further includes forming one or more external connectors on one or more lower conductors of the lower conductors.

[0154] As used herein, the terms “user equipment” (or “UE”), “user terminal”, “client equipment”, “communication equipment”, “wireless equipment”, “wireless communication equipment”, “handheld device”, “mobile device”, “mobile terminal”, “mobile station”, “phone”, “access terminal”, “subscriber equipment”, “subscriber terminal”, “subscriber station”, “terminal”, and their variations may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, motor vehicle equipment in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device that can receive wireless communication and / or navigation signals, such as via short-range wireless, infrared, wired, or other connections, whether at the device itself or at other devices, satellite signal reception, auxiliary data reception, and / or location-related processing. Furthermore, these terms are intended to encompass all devices, including wireless and wired communication devices, capable of communicating with the core network via a radio access network (RAN), through which the UE can connect to external networks such as the Internet, and to other UEs. Of course, other mechanisms for connecting the UE to the core network and / or the Internet are also possible, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11), and so on. The UE can be implemented by any of a variety of devices, including but not limited to printed circuit (PC) cards, compact flash memory devices, external or internal modems, wireless or wired telephones, smartphones, tablets, tracking devices, asset tags, and so on. The communication link through which the UE sends signals to the RAN is called an uplink channel (e.g., reverse flow channel, reverse control channel, access channel, etc.). The communication link through which the RAN sends signals to the UE is called a downlink or forward link channel (e.g., paging channel, control channel, broadcast channel, forward flow channel, etc.). As used in this article, the term Traffic Channel (TCH) can refer to either the uplink / reverse or downlink / forward traffic channel.

[0155] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network (PAN) technology designed and marketed by the Bluetooth Special Interest Group (SIG) to significantly reduce power consumption and cost while maintaining similar communication range. In 2010, with the adoption of Bluetooth Core Specification version 4.0 and the update to Bluetooth 5, BLE was incorporated into the major Bluetooth standard.

[0156] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as superior to other examples. Similarly, the term "example" does not mean that all examples include the features, advantages, or modes of operation discussed. Furthermore, specific features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0157] It should be noted that the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between elements, and may cover the presence of an intermediate element between two elements (the two elements are “connected” or “coupled” together via the intermediate element), unless the connection is explicitly disclosed as a direct connection.

[0158] This document does not limit the number and / or order of elements by using names such as "first," "second," etc. Rather, these names are used as a convenient way to distinguish two or more elements and / or instances of elements. Furthermore, unless otherwise stated, a collection of elements may include one or more elements.

[0159] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0160] Any statements or illustrations depicted in this application are not intended to offer any component, action, feature, benefit, advantage, or equivalent to the public, whether or not such component, action, feature, benefit, advantage, or equivalent is described in the claims.

[0161] As can be seen in the detailed description above, different features are combined together in the examples. This manner of disclosure should not be construed as an intention for the claimed examples to have more features than those expressly mentioned in the corresponding claims. Rather, this disclosure may include all features less than those of the individual examples disclosed. Therefore, the appended claims should be considered as included in the description, where each claim can serve as a separate example on its own. While each claim can serve as a separate example on its own, it should be noted that although dependent claims in a claim may refer to a specific combination having one or more claims, other examples may also cover or include combinations of the subject matter of said dependent claim with any other dependent claim, or any feature combined with other dependent and independent claims. Such combinations are presented herein unless it is expressly stated that a particular combination is not desired. Furthermore, it is intended that features of a claim may be included in any other independent claim, even if said claim is not directly dependent on that independent claim.

[0162] It should be further noted that the methods, systems, and apparatuses disclosed in the description or claims can be implemented by devices that include components for performing corresponding actions and / or functions of the disclosed methods.

[0163] Furthermore, in some examples, a single action can be subdivided into one or more sub-actions, or contain one or more sub-actions. Such sub-actions can be included in the disclosure of a single action and are part of the disclosure of the single action.

[0164] While the foregoing disclosure has shown illustrative examples of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the disclosure described herein need not be performed in any particular order. Furthermore, well-known elements will not be described in detail or may be omitted so as not to obscure the relevant details of the aspects disclosed herein and the examples. Moreover, although elements of this disclosure may be described or claimed in the singular, the plural form is contemplated unless expressly stated to be limited to the singular.

Claims

1. A tunable filter, comprising: Gallium arsenide (GaAs) substrate; A variable capacitor—a variable capacitor—is disposed on the upper surface of the GaAs substrate; An upper conductive structure is disposed on the upper surface of the GaAs substrate, the upper conductive structure comprising one or more upper conductors and one or more upper insulators, the one or more upper conductors and the one or more upper insulators being configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor; One or more GaAs vias (TGVs) are arranged to pass through the GaAs substrate from the upper surface to the lower surface of the GaAs substrate; as well as A lower conductive structure is disposed on the lower surface of the GaAs substrate, the lower conductive structure comprising one or more lower conductors and one or more lower insulators, the one or more lower conductors and the one or more lower insulators being configured to form a lower redistribution layer RDL. The variable capacitor, the MIM capacitor, and the 3D inductor are electrically coupled to form an RF filter circuit, and The variable container includes: A GaAs buffer layer is disposed on the upper surface of the GaAs substrate, and the GaAs buffer layer is n+ doped. A GaAs active layer is disposed on the GaAs buffer layer, wherein the GaAs active layer is n-doped and hyper-abrupt; and The variable container contact is arranged on the GaAs active layer.

2. The tunable filter of claim 1, wherein the lower RDL is configured to electrically couple at least one TGV to at least one other TGV.

3. The tunable filter according to claim 2 further includes: One or more external connectors are configured to electrically couple the lower RDL to one or more components outside the tunable filter.

4. The tunable filter according to claim 3, wherein the one or more external connectors are one or more of wafer-level packaged WLP balls, copper Cu pillars, and solder bumps.

5. The tunable filter of claim 1, wherein one or more of the TGVs are configured to electrically couple one or more of the variable capacitor, the MIM capacitor, and the 3D inductor to the lower RDL.

6. The tunable filter of claim 5, wherein each TGV includes a conductive post arranged to fill a via of the GaAs substrate, the conductive post extending within the via from the upper surface of the GaAs substrate to the lower surface of the GaAs substrate.

7. The tunable filter according to claim 6, wherein the conductive pillar is formed of any one or more of copper (Cu), silver (Ag), gold (Au), aluminum (Al), tungsten (W), nickel (Ni), or combinations thereof.

8. The tunable filter of claim 6, wherein the conductive pillar and the lower RDL are formed of the same one or more conductive materials.

9. The tunable filter of claim 6, wherein each TGV further comprises a conductive layer disposed vertically on the wall of the GaAs substrate, such that the conductive pillar is disposed within the via on the conductive layer and inside the conductive layer.

10. The tunable filter according to claim 9, The conductive layer of the TGV is horizontally arranged between the corresponding conductive pillar and the first upper conductor of the upper conductive structure, and / or The conductive layers of the same or different TGV are horizontally arranged between the lower surface of the GaAs substrate and the lower RDL.

11. The tunable filter of claim 6, wherein each TGV further comprises an insulating plug configured to fill a central cavity within the conductive pillar, the insulating plug extending from below the lower surface of the GaAs substrate to below the upper surface of the GaAs substrate.

12. The tunable filter of claim 11, wherein the insulating plug and the one or more lower insulators of the lower conductive structure are formed of the same one or more insulating materials.

13. The tunable filter according to claim 1, The lower RDL of the lower conductive structure is disposed on the lower surface of the GaAs substrate, and The lower conductive structure, wherein one or more lower insulators are disposed on the lower surface of the GaAs substrate and on the lower RDL.

14. The tunable filter of claim 13, wherein the one or more lower insulators are formed of any one or more of the following: silicon dioxide (SiO2), organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or silicon-based polymer dielectric.

15. The tunable filter of claim 1, wherein the GaAs active layer is mesa-shaped.

16. The tunable filter of claim 1, wherein the tunable filter is incorporated into an apparatus selected from the group consisting of: entertainment units, navigation devices, and communication devices.

17. A tunable filter, comprising: Gallium arsenide (GaAs) substrate; A variable capacitor—a variable capacitor—is disposed on the upper surface of the GaAs substrate; An upper conductive structure is disposed on the upper surface of the GaAs substrate, the upper conductive structure comprising one or more upper conductors and one or more upper insulators, the one or more upper conductors and the one or more upper insulators being configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor; One or more GaAs vias (TGVs) are arranged to pass through the GaAs substrate from the upper surface to the lower surface of the GaAs substrate; as well as A lower conductive structure is disposed on the lower surface of the GaAs substrate, the lower conductive structure comprising one or more lower conductors and one or more lower insulators, the one or more lower conductors and the one or more lower insulators being configured to form a lower redistribution layer RDL. The variable capacitor, the MIM capacitor, and the 3D inductor are electrically coupled to form an RF filter circuit, and The upper conductive structure includes: One or more first upper conductors are arranged on the one or more TGVs; One or more second upper conductors are arranged on or above the one or more first upper conductors; One or more third upper conductors are arranged on or above the one or more second upper conductors; One or more fourth upper conductors are arranged on the one or more third upper conductors; One or more first upper insulators are disposed on one or more of the first upper conductors; and One or more second upper insulators are disposed on one or more first upper conductors in the first upper conductors and on one or more first upper insulators in the first upper insulators.

18. The tunable filter of claim 17, wherein the first upper conductor, the second upper conductor, the third upper conductor and / or the fourth upper conductor are formed of any one or more of copper Cu, silver Ag, gold Au, aluminum Al or combinations thereof.

19. The tunable filter of claim 17, wherein one of the first upper conductors is configured to electrically couple the GaAs buffer layer of the variable capacitor to one of the TGVs.

20. The tunable filter of claim 19, wherein one of the fourth upper conductors is electrically coupled to a variable capacitor contact of the variable capacitor, and the other of the fourth upper conductors is electrically coupled to the GaAs buffer layer of the variable capacitor.

21. The tunable filter of claim 17, wherein the MIM capacitor comprises: Lower electrode plate; Upper electrode plate; as well as A dielectric material is disposed between the lower electrode and the upper electrode. One of the second upper conductors serves as the lower electrode, one of the second upper insulators serves as the dielectric, and one of the third upper conductors serves as the upper electrode.

22. The tunable filter of claim 21, wherein one of the lower plate and the upper plate is electrically coupled to one of the variable capacitor and the 3D inductor, and the other of the lower plate and the upper plate is electrically coupled to the other of the variable capacitor and the 3D inductor.

23. The tunable filter of claim 21, wherein the lower electrode does not contact any of the first upper conductors in the first upper conductor.

24. The tunable filter of claim 17, wherein the 3D inductor comprises one or more loops, each loop comprising: Upper horizontal loop segmentation; First vertical loop segmentation and second vertical loop segmentation; as well as The lower horizontal loop is segmented. The upper horizontal loop segment includes one of the fourth upper conductors, the first vertical loop segment includes one of the TGVs, the second vertical loop segment includes another TGV, and the lower horizontal loop segment includes one of the lower conductors.

25. The tunable filter of claim 17, wherein the upper conductive structure further comprises: One or more third upper insulators are disposed on or above the GaAs substrate to encapsulate the first upper conductor, the second upper conductor, and the third upper conductor; as well as One or more fourth upper insulators are disposed on the one or more fourth upper conductors and the one or more third upper insulators. The fourth upper insulator completely covers the upper surface of the fourth upper conductor electrically coupled to the MIM capacitor, and completely covers the upper surface of the fourth upper conductor forming the 3D inductor.

26. The tunable filter of claim 25, wherein the first upper insulator, the second upper insulator, the third upper insulator, and / or the fourth upper insulator are formed of one or more of silicon dioxide (SiO2), organic polymer dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polybenzoxazole (PBO), or silicon-based polymer dielectric.

27. A method for manufacturing a tunable filter, the method comprising: A variable capacitor—a variable capacitor—is formed on the upper surface of a GaAs substrate; An upper conductive structure is formed on the upper surface of the GaAs substrate, the upper conductive structure including one or more upper conductors and one or more upper insulators, the one or more upper conductors and one or more upper insulators being configured to form one or more passive components including a metal-insulator-metal (MIM) capacitor and a 3D inductor; One or more GaAs vias (TGVs) are formed, the one or more GaAs vias (TGVs) passing through the GaAs substrate from the upper surface of the GaAs substrate to the lower surface of the GaAs substrate; as well as A lower conductive structure is formed on the lower surface of the GaAs substrate, the lower conductive structure including one or more lower conductors and one or more lower insulators, the one or more lower conductors and the one or more lower insulators being configured to form a lower redistribution layer RDL. The variable capacitor, the MIM capacitor, and the 3D inductor are electrically coupled to form an RF filter circuit, and The variable container is formed by: An n+ doped GaAs layer is deposited on the upper surface of the GaAs substrate, and an n-doped GaAs layer is deposited on the n+ doped GaAs layer, wherein the n-doped GaAs layer is hyper-abrupt. A variable container contact is formed on the n-doped GaAs layer.

28. The method of claim 27, wherein forming the upper conductive structure comprises: A first upper conductive layer is deposited and patterned to form one or more first upper conductors disposed on the upper surface of the GaAs substrate; A first upper insulating layer is deposited and patterned to form one or more first upper insulators disposed on one or more first upper conductors in the first upper conductors and / or on the upper surface of the GaAs substrate; A second upper conductive layer is deposited and patterned to form one or more second upper conductors disposed on or above the one or more first upper conductors; A second upper insulating layer is deposited and patterned to form one or more second upper insulators disposed on or above the one or more first upper insulators; A third upper conductive layer is deposited and patterned to form one or more third upper conductors disposed on the one or more second upper conductors; A third upper insulating layer is deposited and patterned to form one or more third upper insulators, the one or more third upper insulators being configured to expose the upper surface of the one or more third upper conductors; A fourth upper conductive layer is deposited and patterned to form one or more fourth upper conductors disposed on the one or more third upper conductors; as well as A fourth upper insulating layer is deposited and patterned to form one or more fourth upper insulators, the one or more fourth upper insulators being configured to encapsulate the one or more fourth upper conductors.

29. The method of claim 28, wherein the MIM capacitor comprises: Lower electrode plate; Upper electrode plate; as well as A dielectric material is disposed between the lower electrode and the upper electrode. One of the second upper conductors serves as the lower electrode, one of the second upper insulators serves as the dielectric, and one of the third upper conductors serves as the upper electrode.

30. The method of claim 28, wherein the 3D inductor comprises one or more loops, each loop comprising: Upper horizontal loop segmentation; First vertical loop segmentation and second vertical loop segmentation; as well as The lower horizontal loop is segmented. The upper horizontal loop segment includes one of the fourth upper conductors, the first vertical loop segment includes one of the TGVs, the second vertical loop segment includes another TGV, and the lower horizontal loop segment includes one of the lower conductors constituting the lower RDL.

31. The method of claim 27, wherein forming the one or more TGVs and forming the lower conductive structure comprises: Grind the back side of the GaAs substrate; The GaAs substrate is etched to form one or more vias, the one or more vias exposing one or more first upper conductors of the upper conductive structure; A conductive layer is formed by depositing a conductive material over the walls of the one or more vias, the exposed one or more first upper conductors, and a portion of the lower surface of the GaAs substrate. The conductive layer and the lower surface of the GaAs substrate are coated with a conductive material to form conductive pillars in each via and in the lower RDL, wherein each conductive pillar is formed to have a central cavity; as well as A lower insulating layer is deposited and patterned to form one or more lower insulators disposed on the lower surface of the GaAs substrate and on the lower RDL, and one or more insulating plugs are formed, the one or more insulating plugs being configured to fill the central cavity of the conductive pillar. Each TGV includes one conductive pillar and a corresponding conductive layer.

32. The method of claim 31, wherein forming the one or more TGVs and forming the lower conductive structure further comprises: One or more external connectors are formed on the one or more lower conductors.

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