Impedance test structure and design method of impedance test structure

Abstract

The embodiment of the present application belongs to the technical field of printed circuit board design and manufacturing, and particularly relates to an impedance test structure and a design method of the impedance test structure, which are used to solve the problem of time-consuming and laborious manual test of the printed circuit board in the related art. The impedance test structure has a plurality of circuit layers arranged in layers, and each circuit layer is provided with an impedance line. The impedance line is located in a detection area of the circuit layer, and the impedance values of two impedance lines in adjacent circuit layers are not equal. When the impedance test structure is tested, an impedance tester is used to test the impedance of the detection area. Since different impedance values can obtain different detection signals, the detection signals and waveforms are distinguished to test whether the printed circuit board has layer dislocation phenomenon, so that the detection efficiency is improved and the manpower is saved.

Description

Technical Field

[0001] The present invention relates to the field of printed circuit board design and manufacturing technology, and in particular to an impedance test structure and a design method for the impedance test structure. Background Technology

[0002] With the development of printed circuit board (PCB) technology, multilayer PCBs are increasingly being used. In the fabrication of PCB structures, layer numbers are typically etched onto each circuit layer, which are then stacked sequentially and pressed together to form a multilayer PCB. In related technologies, manual verification of the layer numbers on each circuit layer is commonly used to test for layer misalignment. However, this manual testing method is time-consuming and labor-intensive. Summary of the Invention

[0003] This invention provides an impedance testing structure and a design method for the impedance testing structure, in order to solve the problem of time-consuming and labor-intensive manual testing of printed circuit boards in related technologies.

[0004] In a first aspect, embodiments of the present invention provide an impedance testing structure, comprising multiple stacked circuit layers, each circuit layer having an impedance line located within the detection area of ​​the circuit layer, wherein the impedance values ​​of two impedance lines in adjacent circuit layers are not equal.

[0005] In one possible implementation, the impedance value of each of the impedance lines is not equal to the impedance values ​​of the other impedance lines.

[0006] In one possible implementation, multiple signal vias are included, the signal vias passing through the circuit layer, and any impedance line is located between two adjacent signal vias, so that the impedance lines are connected in series.

[0007] In one possible implementation, a grounding hole is also included, wherein the grounding hole and the signal hole are at a predetermined distance.

[0008] In one possible implementation, a plurality of the signal holes are arranged in an array on the impedance test structure.

[0009] Secondly, embodiments of the present invention also provide a design method for an impedance test structure, comprising:

[0010] The length and width of the impedance test structure are designed, and the impedance test structure has multiple stacked circuit layers.

[0011] A signal aperture is designed within the impedance test structure, the signal aperture penetrating the circuit layer to form a detection area for impedance detection;

[0012] Impedance lines are designed within each of the circuit layers so that the impedance lines are located within the detection area, and the impedance values ​​of two impedance lines in adjacent circuit layers are not equal.

[0013] A grounding hole is designed within the impedance test structure.

[0014] In one possible implementation, the design of impedance lines within each of the circuit layers includes: the impedance value of each impedance line is not equal to the impedance values ​​of the other impedance lines.

[0015] In one possible implementation, each of the impedance lines is designed to have a different linewidth and line length, so that the impedance value of each impedance line is not equal to the impedance values ​​of the other impedance lines.

[0016] In one possible implementation, the impedance lines are designed to be located between two adjacent signal holes, such that the impedance lines are connected in series.

[0017] In one possible implementation, designing signal holes within the impedance test structure includes: designing a plurality of the signal holes arranged in an array within the impedance test structure.

[0018] This invention provides an impedance testing structure and its design method, comprising multiple stacked circuit layers, each with an impedance line located within a detection area of ​​the circuit layer. The impedance values ​​of two impedance lines in adjacent circuit layers are unequal. When testing the impedance testing structure, an impedance meter is used to detect the impedance in the detection area. Since different impedance values ​​yield different detection signals, distinguishing these signals allows for the testing of whether layer misalignment has occurred on the printed circuit board, improving testing efficiency and saving manpower. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the impedance testing structure provided in the embodiments of the present invention. Figure 1 ;

[0021] Figure 2 for Figure 1 AA cross-section of the impedance test structure in Figure 1 ;

[0022] Figure 3 For this Figure 1 AA cross-section of the impedance test structure in Figure 2 ;

[0023] Figure 4 A schematic diagram of the impedance testing structure provided in the embodiments of the present invention. Figure 2 ;

[0024] Figure 5 A flowchart illustrating the design method of the impedance test structure provided in an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] 10. Impedance test structure; 101. First circuit layer; 102. Second circuit layer; 103. Third circuit layer; 104. Fourth circuit layer; 105. Fifth circuit layer;

[0027] 11. Signal hole; 111. First signal hole; 112. Second signal hole; 113. Third signal hole; 114. Fourth signal hole; 115. Fifth signal hole;

[0028] 12. Grounding hole;

[0029] 13. Positioning holes;

[0030] 14. Impedance line; 141. First impedance line; 142. Second impedance line; 143. Third impedance line; 144. Fourth impedance line; 145. Fifth impedance line; 146. Sixth impedance line. Detailed Implementation

[0031] With the development of printed circuit board (PCB) technology, multilayer PCBs are increasingly being used. In the fabrication of PCB structures, layer numbers are typically etched onto each circuit layer, which are then stacked and pressed together to form a multilayer PCB. In related technologies, manual verification of the layer numbers on each circuit layer is commonly used to test for layer misalignment. However, this manual testing method is time-consuming and labor-intensive.

[0032] In view of this, embodiments of the present invention provide an impedance testing structure and a design method for the impedance testing structure. The impedance testing structure has multiple stacked circuit layers, each circuit layer having an impedance line located within the detection area of ​​the circuit layer. The impedance values ​​of two impedance lines in adjacent circuit layers are not equal. When testing the impedance testing structure, an impedance tester is used to detect the impedance of the detection area. Since different impedance values ​​yield different detection signals, distinguishing the detection signals allows for the testing of whether layer misalignment has occurred on the printed circuit board, improving testing efficiency and saving manpower.

[0033] The following describes several optional implementations of the present invention with reference to the accompanying drawings. Those skilled in the art should understand that the following implementations are merely illustrative and not exhaustive. Based on these implementations, those skilled in the art may replace, splice, or combine certain features or examples, and these should still be considered as the disclosure of the present invention.

[0034] Reference Figure 1 , Figure 2 as well as Figure 3 The impedance test structure 10 provided in this embodiment of the invention is located at the edge of the production panel of the circuit board, and specifically includes multiple stacked circuit layers. It should be noted that the number of circuit layers in the impedance test structure 10 is the same as the number of circuit layers in the circuit board, so that the circuit board and the impedance test structure 10 can be formed using synchronous process technology during the subsequent production process.

[0035] For example, each circuit layer is provided with an impedance line 14, which is located within the detection area of ​​the circuit layer. In this embodiment, the impedance test structure 10 has a test plane, which is the side of the outermost circuit layer away from its adjacent circuit layers. The detection area is located within this test plane, which is beneficial for the impedance tester to perform test operations within the detection area of ​​the test plane to test the impedance value of the impedance line 14 in multiple circuit layers.

[0036] It is worth noting that an impedance tester is a testing instrument that inputs a current signal to the structure under test and determines the impedance value by detecting the response signal of the input signal. In this embodiment, after inputting a current signal to the impedance line 14, a corresponding TDR (Time Domain Reflectometer) waveform curve can be obtained, and the impedance value of the impedance line 14 can be determined based on the TDR waveform curve. Specifically, an impedance tester typically includes a test probe, and the impedance tester is usually connected to the structure under test through the test probe.

[0037] In one possible implementation, multiple through-hole conductive holes can be provided on the circuit layer, with the center line of the conductive holes perpendicular to the plane of the circuit layer, so that the two ends of the impedance line 14 are connected to the conductive holes respectively. The multiple conductive holes can form the detection area of ​​the circuit layer. By contacting the impedance tester with the conductive holes, the impedance value of the impedance line 14 between the conductive holes can be detected.

[0038] In another possible implementation, a set of conductive leads can be provided on the surface of each circuit layer, with both ends of the impedance line 14 connected to the conductive leads, and the other end of the conductive leads exposed in the test plane of the impedance test structure 10. The conductive leads exposed in the test plane of the impedance test structure 10 can form the detection area of ​​the circuit layer. By contacting the impedance tester with the conductive leads, the impedance value of the impedance line 14 between the conductive holes can be detected.

[0039] In this embodiment, the impedance values ​​of the two impedance lines 14 in adjacent circuit layers are not equal, so that when the impedance is detected by the impedance tester, it is possible to determine whether the adjacent circuit layers have misaligned based on the impedance values ​​of the adjacent circuit layers, thereby determining whether the printed circuit board has misaligned.

[0040] This invention provides an impedance testing structure 10, comprising multiple stacked circuit layers. Each circuit layer has an impedance line 14 located within a detection area of ​​the circuit layer. The impedance values ​​of two impedance lines 14 in adjacent circuit layers are unequal. When testing the impedance testing structure 10, an impedance tester is used to detect the impedance of the detection area. Since different impedance values ​​yield different detection signals, the detection signals and waveforms can be distinguished to test whether layer misalignment has occurred on the printed circuit board, thus improving testing efficiency and saving manpower.

[0041] Furthermore, the impedance testing structure 10 can also determine whether the circuit impedance of the circuit board is qualified by testing the impedance value of the impedance line 14, thereby realizing quality control and inspection in the circuit board manufacturing process and improving product yield. In related technologies, impedance test strips are usually provided for achieving quality control of circuit impedance. Compared with the impedance test strips in related technologies, this embodiment can achieve both quality control of the circuit impedance within the circuit board and detection of whether the circuit board has layer misalignment, thus improving the integration of the impedance testing structure 10.

[0042] Optionally, the impedance value of each impedance line 14 is not equal to the impedance value of the other impedance lines 14, so that each impedance line 14 has a different impedance value. Accordingly, when the impedance line 14 is tested using an impedance tester, each impedance line 14 can obtain a different TDR curve, which is helpful to further determine whether the circuit layer corresponding to the impedance line 14 has a layer misalignment phenomenon.

[0043] For example, the impedance value of impedance line 14 can be set by adjusting its length and width. For instance, each impedance line 14 can be configured with a different width or length so that the impedance value of each impedance line 14 is not equal to the impedance values ​​of the other impedance lines 14. It should be noted that the length and width of the impedance line 14 must be set according to the capabilities of the impedance tester. For example, if the impedance tester can measure the length of the impedance line 14 in the range of 0.1 inch to 1 inch, then the length of the impedance line 14 can be set to 0.1 inch, 0.5 inch, or 1 inch.

[0044] In this embodiment, in addition to setting the length and width of the impedance line 14, the impedance value of the impedance line 14 can also be set by setting the material of the circuit layer.

[0045] Furthermore, by setting the impedance value of impedance line 14, it is possible to test the impedance of different lines within the circuit board, thereby improving the testing capability of impedance test structure 10 and meeting the testing needs of different products.

[0046] Optionally, the impedance test structure 10 also includes multiple signal holes 11, which are arranged through the circuit layer. Any impedance line 14 is located between two adjacent signal holes 11, so that all impedance lines 14 are connected in series. For example... Figure 2 and Figure 3 As shown, each circuit layer has an impedance line 14, and the two ends of the impedance line 14 are connected to two adjacent signal holes 11. It should be noted that the inner wall of the signal hole 11 has a conductive layer so that the impedance lines 14 located in different circuit layers can be electrically connected through the signal hole 11. The material of the conductive layer can be, for example, a metal such as copper.

[0047] In one possible implementation, the impedance lines 14 can be arranged in a stepped configuration, connected in series. For example, continue to refer to... Figure 2The impedance test structure 10 shown in the figure includes a first circuit layer 101, a second circuit layer 102, a third circuit layer 103, a fourth circuit layer 104, and a fifth circuit layer 105 stacked sequentially, with the first circuit layer 101 located at the top layer in the figure. Correspondingly, each circuit layer has an impedance line 14. Along the extension direction of the impedance test structure 10, a first signal hole 111, a second signal hole 112, a third signal hole 113, a fourth signal hole 114, and a fifth signal hole 115 are sequentially arranged, with the first signal hole 111 located at the left end in the figure. One end of the first impedance line 141 located in the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 located in the second circuit layer 102 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; the impedance lines 14 of the other circuit layers are arranged according to the above rules to form a stepped series arrangement of the impedance lines 14, which will not be described further here.

[0048] In another possible implementation, the impedance lines 14 can be arranged in a series configuration with an uneven or concave shape. For example, see [reference]. Figure 3 The impedance test structure 10 shown in the figure, except for the arrangement of the impedance lines 14, is the same as... Figure 2 The same applies. One end of the first impedance line 141 located in the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 located in the second circuit layer 102 is connected to the fifth signal hole 115, and the other end is connected to the fourth signal hole 114; one end of the third impedance line 143 located in the third circuit layer 103 is connected to the third signal hole 113, and the other end is connected to the fourth signal hole 114; one end of the fourth impedance line 144 located in the fourth circuit layer 104 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; one end of the fifth impedance line 145 located in the fifth circuit layer 105 is connected to the third signal hole 113, and the other end is connected to the second signal hole 112. Through the above connection method, a series connection is formed in which the impedance lines 14 are arranged in a concave-convex shape.

[0049] The following is based on Figure 2For example, the process of testing the impedance test structure 10 using an impedance tester is briefly explained. For instance, when the test probe contacts the third signal hole 113, since the impedance lines 14 are connected in series, the impedance tester can pass the same current signal to the first impedance line 141, the second impedance line 142, and the third impedance line 143. Since the signal hole 11 also has a certain impedance, the obtained TDR curve includes two curves with obvious fluctuations. These two curves correspond to the impedance of the first signal hole 111 and the impedance of the second signal hole 112, respectively. Thus, the TDR curve can be sequentially divided into the first segment, the second segment, and the third segment, corresponding to the impedance of the first impedance line 141, the impedance of the second impedance line 142, and the impedance of the third impedance line 143, respectively. This allows it to determine whether there is a layer misalignment between the first impedance line 141, the second impedance line 142, and the third impedance line 143, and also to determine whether the circuit impedance of the circuit board is qualified.

[0050] It is worth noting that when the test probe contacts the third signal hole 113, the third circuit layer 103 is the reference layer in the impedance test structure 10. The surface of the third circuit layer 103 needs to be covered with copper to shield the impedance lines 14 of other circuit layers.

[0051] Optionally, the impedance test structure 10 also includes a grounding hole 12, which is spaced at a preset distance from the signal hole 11. For example, the grounding hole 12 extends through the impedance test structure 10, with one end exposed in the test plane and the other end connected to the shielding layer of the circuit board. The preset distance between the grounding hole 12 and the signal hole 11 accommodates the spacing between the test probes of the impedance tester, thus facilitating impedance testing where one test probe is connected to the grounding hole 12 and the other test probe is in contact with the signal hole 11.

[0052] by Figure 1 For example, a grounding hole 12 can be provided on one side of the first signal hole 111, and the grounding hole 12 and the first signal hole 111 can be at a preset distance. Of course, in some other examples, multiple grounding holes 12 can be provided, with one grounding hole 12 corresponding to one side of each signal hole 11, and the grounding hole 12 and its corresponding signal hole 11 can be at a preset distance.

[0053] Optionally, multiple impedance lines 14 are arranged in an array on the impedance test structure 10, thereby further providing multiple signal holes 11 on the impedance test structure 10 without increasing its length, thus improving the integration of the impedance test structure 10. Figure 4 As shown, the impedance test structure 10 has two rows of signal holes 11, each row including five signal holes 11 spaced apart along the extending direction of the impedance test structure 10. Correspondingly, Figure 4 The impedance test structure 10 shown includes 11 stacked circuit layers, each circuit layer is provided with an impedance line 14, and the projection of the impedance line 14 on the impedance test structure 10 is a broken line shape, so that the impedance lines 14 are connected in series.

[0054] Continue to refer to Figure 1 and Figure 4 The impedance test structure 10 is also provided with a positioning hole 13, which is used to prevent the impedance test structure 10 from moving during the test. During the test, after aligning the positioning hole 13 with the mating hole on the fixture used to fix the impedance test structure 10, the probe is inserted to fix the impedance test structure 10 on the fixture.

[0055] This invention also provides a design method for an impedance testing structure 10, used to design the impedance testing structure 10 in the above embodiments. The testing principle of the impedance tester has been briefly described above, and will not be repeated in this embodiment.

[0056] like Figure 5 As shown, the design method of the impedance test structure 10 provided in this embodiment includes the following steps:

[0057] Step S101: Design the length and width of the impedance test structure. The impedance test structure has multiple stacked circuit layers.

[0058] For example, the length and width of the impedance test structure 10 are designed based on the process capabilities of the circuit board manufacturing equipment and the equipment capabilities of the impedance tester. The process capabilities of the circuit board may include, for example, the diameter of the drilled holes, the line width and line length of the etched lines, etc. The equipment capabilities of the impedance tester may include, for example, the spacing between the test probes, the line length and line width of the impedance lines 14 that can be measured, etc.

[0059] It should be noted that the number of circuit layers is the same as the number of circuit layers in the circuit board, so that the circuit board and the impedance test structure 10 can be formed using the same process technology in the subsequent manufacturing process.

[0060] Step S102: Design signal holes within the impedance test structure. The signal holes penetrate the circuit layer to form a detection area for impedance detection.

[0061] For example, the impedance test structure 10 includes a plurality of signal holes 11, which together form a detection area for impedance detection. It should be noted that the inner wall of the signal hole 11 has a conductive layer so that impedance lines 14 located in different circuit layers can be electrically connected through the signal hole 11. The conductive layer can be made of a metal such as copper.

[0062] Step S103: Design impedance lines in each circuit layer so that the impedance lines are located within the detection area and the impedance values ​​of two impedance lines in adjacent circuit layers are not equal.

[0063] In this embodiment, the impedance values ​​of the two impedance lines 14 in adjacent circuit layers are not equal, so that when the impedance is detected by the impedance tester, it is possible to determine whether the adjacent circuit layers have misaligned based on the impedance values ​​of the adjacent circuit layers, thereby determining whether the printed circuit board has misaligned.

[0064] Step S104: Design a grounding hole within the impedance test structure.

[0065] For example, a grounding hole 12 is provided through the impedance test structure 10, with one end of the grounding hole 12 exposed in the test plane and the other end connected to the shielding layer of the circuit board. There is a preset distance between the grounding hole 12 and the signal hole 11 to accommodate the spacing between the test probes of the impedance tester, thereby facilitating the impedance tester to connect one test probe to the grounding hole 12 and contact the signal hole 11 when testing impedance.

[0066] This invention provides a design method for an impedance test structure 10, including designing the length and width of the impedance test structure 10. The impedance test structure 10 has multiple stacked circuit layers. Signal vias 11 are designed within the impedance test structure 10, penetrating the circuit layers to form a detection area for impedance detection. Impedance lines 14 are designed within each circuit layer, ensuring that the impedance lines 14 are located within the detection area and that the impedance values ​​of two impedance lines 14 in adjacent circuit layers are unequal. Grounding vias 12 are designed within the impedance test structure 10. When testing the impedance test structure 10 designed in this embodiment, an impedance tester is used to detect the impedance in the detection area. Since different impedance values ​​yield different detection signals, distinguishing the detection signals and waveforms allows for testing whether layer misalignment has occurred on the printed circuit board, improving detection efficiency and saving manpower.

[0067] Furthermore, the impedance testing structure 10 designed in this embodiment can also determine whether the circuit impedance of the circuit board is qualified by testing the impedance value of the impedance line 14, thereby realizing quality control and inspection in the circuit board manufacturing process and improving product yield. In related technologies, impedance test strips are usually provided for realizing quality control of circuit impedance. Compared with the impedance test strips in related technologies, the impedance testing structure 10 designed in this embodiment can not only realize quality control of the circuit impedance within the circuit board, but also detect whether the circuit board has layer misalignment, thus improving the integration of the impedance testing structure 10.

[0068] In this embodiment, the step of designing impedance lines 14 in each circuit layer includes: the impedance value of each impedance line 14 is not equal to the impedance value of other impedance lines 14, so that each impedance line 14 has a different impedance value. Accordingly, when the impedance line 14 is tested using an impedance tester, each impedance line 14 can obtain a different TDR curve, which is helpful to further determine whether the circuit layer corresponding to the impedance line 14 has a layer misalignment phenomenon.

[0069] Optionally, each impedance line 14 can be designed with a different line width and length so that the impedance value of each impedance line 14 is not equal to the impedance values ​​of the other impedance lines 14. For example, each impedance line 14 can be set with a different line width or length to ensure that the impedance value of each impedance line 14 is not equal to the impedance values ​​of the other impedance lines 14. It should be noted that the line length and line width of the impedance line 14 also need to be set according to the capabilities of the impedance tester. For example, when the impedance tester can measure the length of the impedance line 14 in the range of 0.1 inch to 1 inch, the line length of the impedance line 14 can be set to 0.1 inch, 0.5 inch, or 1 inch.

[0070] In this embodiment, in addition to setting the length and width of the impedance line 14, the impedance value of the impedance line 14 can also be set by setting the material of the circuit layer.

[0071] Furthermore, by setting the impedance value of impedance line 14, it is possible to test the impedance of different lines within the circuit board, thereby improving the testing capability of impedance test structure 10 and meeting the testing needs of different products.

[0072] In this embodiment, an arbitrary impedance line 14 is designed to be located between two adjacent signal holes 11 so that the impedance lines 14 are connected in series.

[0073] In one possible implementation, the impedance lines 14 can be arranged in a stepped configuration, as exemplified by [reference needed]. Figure 2The impedance test structure 10 shown in the figure includes a first circuit layer 101, a second circuit layer 102, a third circuit layer 103, a fourth circuit layer 104, a fifth circuit layer 105, and a sixth circuit layer stacked sequentially, with the first circuit layer 101 located at the top layer in the figure. Correspondingly, each circuit layer has an impedance line 14. Along the extension direction of the impedance test structure 10, a first signal hole 111, a second signal hole 112, a third signal hole 113, a fourth signal hole 114, and a fifth signal hole 115 are sequentially arranged, with the first signal hole 111 located at the left end in the figure. One end of the first impedance line 141 located in the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 located in the second circuit layer 102 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; the impedance lines 14 of the other circuit layers are arranged according to the above rules to form a stepped series arrangement of the impedance lines 14, which will not be elaborated further here.

[0074] In another possible implementation, the impedance lines 14 can be arranged in a series configuration with an uneven or concave shape. For example, see [reference]. Figure 3 The impedance test structure 10 shown in the figure, except for the arrangement of the impedance lines 14, is the same as... Figure 2 The same applies. One end of the first impedance line 141 located in the first circuit layer 101 is connected to the first signal hole 111; one end of the second impedance line 142 located in the second circuit layer 102 is connected to the fifth signal hole 115, and the other end is connected to the fourth signal hole 114; one end of the third impedance line 143 located in the third circuit layer 103 is connected to the third signal hole 113, and the other end is connected to the fourth signal hole 114; one end of the fourth impedance line 144 located in the fourth circuit layer 104 is connected to the first signal hole 111, and the other end is connected to the second signal hole 112; one end of the fifth impedance line 145 located in the fifth circuit layer 105 is connected to the third signal hole 113, and the other end is connected to the second signal hole 112. Through the above connection method, a series connection is formed in which the impedance lines 14 are arranged in a concave-convex shape.

[0075] certainly, Figure 2 and Figure 3 The two arrangements shown are just examples; impedance lines 14 can also be arranged in other ways that can be connected in series.

[0076] The following is based on Figure 2For example, the process of testing the impedance test structure 10 using an impedance tester is briefly explained. For instance, when the test probe contacts the third signal hole 113, since the impedance lines 14 are connected in series, the impedance tester can pass the same current signal to the first impedance line 141, the second impedance line 142, and the third impedance line 143. Since the signal hole 11 also has a certain impedance, the obtained TDR curve includes two curves with obvious fluctuations. These two curves correspond to the impedance of the first signal hole 111 and the impedance of the second signal hole 112, respectively. Thus, the TDR curve can be sequentially divided into the first segment, the second segment, and the third segment, corresponding to the impedance of the first impedance line 141, the impedance of the second impedance line 142, and the impedance of the third impedance line 143, respectively. This allows it to determine whether there is a layer misalignment between the first impedance line 141, the second impedance line 142, and the third impedance line 143, and also to determine whether the circuit impedance of the circuit board is qualified.

[0077] It is worth noting that when the test probe contacts the third signal hole 113, the third circuit layer 103 is the reference layer in the impedance test structure 10. A layer of copper metal needs to be designed on the surface of the third circuit layer 103 to shield the impedance lines 14 of other circuit layers.

[0078] In this embodiment, the step of designing signal holes 11 within the impedance test structure 10 further includes: designing multiple signal holes 11 arranged in an array within the impedance test structure 10, thereby further providing multiple signal holes 11 on the impedance test structure 10 without increasing its length, thus improving the integration of the impedance test structure 10. Figure 4 As shown, the impedance test structure 10 has two rows of signal holes 11, each row including five signal holes 11 spaced apart along the extending direction of the impedance test structure 10. Correspondingly, Figure 4 The impedance test structure 10 shown includes 11 stacked circuit layers, each circuit layer is provided with an impedance line 14, and the projection of the impedance line 14 on the impedance test structure 10 is a broken line shape, so that the impedance lines 14 are connected in series.

[0079] In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of the present invention, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0081] In the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An impedance testing structure, characterized in that, It includes multiple stacked circuit layers and multiple signal holes. Each circuit layer is provided with an impedance line, which is located in the detection area of ​​the circuit layer. The impedance values ​​of two impedance lines in adjacent circuit layers are not equal. The impedance value of each impedance line is different from the impedance values ​​of the other impedance lines; The signal vias penetrate the circuit layer, and any impedance line is located between two adjacent signal vias, so that the impedance lines are connected in series. By using an impedance tester to detect the impedance of the detection area, different impedance values ​​will generate different detection signals. By distinguishing the detection signals and waveforms, it is possible to test whether the printed circuit board has a layer misalignment phenomenon.

2. The impedance testing structure according to claim 1, characterized in that, It also includes a grounding hole, and the grounding hole and the signal hole are at a preset distance.

3. The impedance testing structure according to claim 1, characterized in that, Multiple signal holes are arranged in an array on the impedance test structure.

4. A design method applicable to the impedance test structure as described in any one of claims 1-3, characterized in that, include: The length and width of the impedance test structure are designed, and the impedance test structure has multiple stacked circuit layers. A signal aperture is designed within the impedance test structure, the signal aperture penetrating the circuit layer to form a detection area for impedance detection; Impedance lines are designed within each of the circuit layers so that the impedance lines are located within the detection area, and the impedance values ​​of two impedance lines in adjacent circuit layers are not equal. A grounding hole is designed within the impedance test structure.

5. The design method of the impedance test structure according to claim 4, characterized in that, Impedance lines are designed within each of the circuit layers, including the following: the impedance value of each impedance line is not equal to the impedance value of the other impedance lines.

6. The design method of the impedance test structure according to claim 5, characterized in that, By designing each of the impedance lines to have a different line width and line length, the impedance value of each impedance line is not equal to the impedance values ​​of the other impedance lines.

7. The design method of the impedance test structure according to claim 6, characterized in that, The impedance lines are designed to be located between two adjacent signal holes, so that the impedance lines are connected in series.

8. The design method of the impedance test structure according to any one of claims 4-7, characterized in that, Designing signal holes within the impedance test structure includes: designing multiple signal holes arranged in an array within the impedance test structure.

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