Bandgap reference circuit, chip, bandgap reference voltage source, and electronic device
By employing a clamping unit and a reference voltage output unit in the bandgap reference circuit, the influence of offset voltage is reduced, the accuracy and stability of the bandgap reference voltage are improved, and the circuit instability problem caused by operational amplifier offset is solved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI AWINIC TECH CO LTD
- Filing Date
- 2022-12-08
- Publication Date
- 2026-07-21
AI Technical Summary
In the prior art, the accuracy of bandgap reference voltage sources is unstable due to the offset voltage generated by the operational amplifier, which affects the stability of the circuit.
A clamping unit is used to clamp the voltage clamping point, and the clamping voltage is responded to by a reference voltage output unit, which reduces the impact of offset voltage on the bandgap reference voltage and improves accuracy.
By improving the connection method between the reference voltage output unit and the clamping unit, the influence of offset voltage is reduced, thereby improving the accuracy of the bandgap reference voltage and the stability of the circuit.
Smart Images
Figure CN115756065B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a bandgap reference circuit, chip, bandgap reference voltage source, and electronic device. Background Technology
[0002] In the field of analog integrated circuit design, the bandgap voltage reference is a crucial component, widely used in power supplies, analog-to-digital converters, and other circuits. A classic bandgap voltage reference is obtained by combining positive and negative temperature coefficient voltages in a specific ratio to achieve a system reference voltage that is approximately independent of process technology, power supply, and temperature. This reference voltage serves as the voltage reference for other modules during operation. Therefore, the performance of the bandgap voltage reference has a significant impact on the performance of the chip system, and variations in its accuracy can directly affect the design precision of subsequent circuits.
[0003] In existing technologies, to obtain a bandgap reference voltage, designers typically use operational amplifiers for voltage clamping, and then use the obtained clamping voltage to obtain the bandgap reference voltage. However, when using operational amplifiers for voltage clamping, offset voltage is generated, which affects the accuracy of the bandgap reference voltage, thus causing circuit instability. Summary of the Invention
[0004] In view of this, embodiments of this application provide a bandgap reference circuit, a chip, a bandgap reference voltage source, and an electronic device to improve the problem of the impact of offset voltage generation on the accuracy of the bandgap reference voltage.
[0005] This application provides a bandgap reference circuit, including: The clamping unit is used to clamp the voltage clamping point and output the clamping voltage. A reference voltage output unit, connected to the clamping unit, is used to receive the clamping voltage and output the corresponding bandgap reference voltage.
[0006] Optionally, the clamping unit includes an operational amplifier subunit connected to the reference voltage output unit, used to clamp the voltage clamping point and output the clamping voltage to the reference voltage output unit.
[0007] Optionally, the bandgap reference circuit further includes: a feedback compensation unit, connected to the clamping unit and the reference voltage output unit respectively, for compensating the clamping unit and the reference voltage output unit; and a bias unit, connected to the clamping unit and the reference voltage output unit respectively, for providing a bias voltage to the clamping unit.
[0008] Optionally, the bandgap reference circuit further includes: a startup unit, connected to the clamping unit and the bias unit respectively, for starting the operational amplifier subunit, and starting the reference voltage output unit and the bias unit through the feedback compensation unit.
[0009] Optionally, the startup unit includes: a control subunit for receiving an enable signal sent by a control terminal and outputting an enable control signal; and a startup subunit connected to the control subunit, the clamping unit, and the biasing unit, for acquiring the enable control signal, inputting a startup current to the clamping unit according to the enable control signal, and copying the bias current of the biasing unit to the biasing unit.
[0010] Optionally, the reference voltage output unit includes: a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the first terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the first transistor is connected to the first terminal of the first resistor, the third terminal of the second transistor, and the clamping unit, respectively; the second terminal of the first resistor is connected to the first terminal of the third resistor, the third terminal of the first transistor, and the second terminal of the second resistor, respectively; the second terminal of the second transistor is connected to the first terminal of the second resistor and the clamping unit, respectively; the second terminal of the third resistor is connected to the first terminal of the fourth resistor, the second terminal of the fourth resistor is used to output a bandgap reference voltage, the first terminal of the fifth resistor is connected to the first terminal of the first transistor and the second terminal of the second transistor, and the second terminal of the fifth resistor is grounded.
[0011] Optionally, the operational amplifier subunit includes: a third transistor, a fourth transistor, a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET; the first terminals of the third transistor and the fourth transistor are both grounded, the second terminals of the third transistor and the fourth transistor are both connected to the reference voltage output unit, the third terminal of the third transistor is connected to the first terminal of the first MOSFET, the second terminal of the first MOSFET is connected to the second terminal of the second MOSFET and the reference voltage output unit, and the third terminal of the first MOSFET is connected to the first terminal of the third MOSFET, the second terminal of the third MOSFET, and the second terminal of the fourth MOSFET; the third terminal of the fourth transistor is connected to the first terminal of the second MOSFET, the third terminal of the second MOSFET is connected to the first terminal of the fourth MOSFET, and the third terminals of the third MOSFET and the fourth MOSFET are both connected to a power supply.
[0012] Optionally, the feedback compensation unit includes: a first energy storage element, a second energy storage element, a sixth resistor, and an eighth MOSFET; the first terminal of the first energy storage element is connected to the reference voltage output unit and the first terminal of the eighth MOSFET respectively; the second terminal of the first energy storage element is connected to the reference voltage output unit and the clamping unit respectively; the second terminal of the eighth MOSFET is connected to the clamping unit and the first terminal of the first resistor respectively, and the third terminal of the eighth MOSFET is connected to a power supply; the second terminal of the sixth resistor is connected to the first terminal of the second energy storage element, and the second terminal of the second energy storage element is connected to the second terminal of the first energy storage element, the reference voltage output unit, and the clamping unit respectively.
[0013] Optionally, the bias unit includes: a seventh resistor, a fifth transistor, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET; the first terminal of the seventh resistor is grounded, the second terminal of the seventh resistor is connected to the first terminal of the fifth transistor, the second terminal of the fifth transistor is connected to the reference voltage output unit, the third terminal of the fifth transistor is connected to the first terminal of the fifth MOSFET, the second terminal of the fifth MOSFET is connected to both the reference voltage output unit and the clamping unit, the third terminal of the fifth MOSFET is connected to the first terminal of the sixth MOSFET, the second terminal of the sixth MOSFET, and the second terminal of the seventh MOSFET, the third terminals of the sixth MOSFET and the seventh MOSFET are both connected to a power supply, and the first terminal of the seventh MOSFET serves as a bias signal receiver to receive a bias signal.
[0014] Optionally, the control subunit includes: a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; the first terminal of the ninth MOS transistor is connected to a power supply, the second terminals of the ninth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are all used to receive an enable signal, the third terminal of the ninth MOS transistor, the first terminal of the tenth MOS transistor, and the first terminal of the eleventh MOS transistor are all connected to the startup subunit, and the third terminals of the tenth MOS transistor and the eleventh MOS transistor are both grounded.
[0015] Optionally, the startup subunit includes: a thirteenth MOSFET, a ninth resistor, a first inverter, a sixteenth MOSFET, a tenth resistor, a third energy storage element, a seventeenth MOSFET, and a fourth energy storage element; the first terminal of the thirteenth MOSFET is connected to the power supply, and the second terminal of the thirteenth MOSFET is connected to the bias unit; the third terminal of the thirteenth MOSFET is connected to the first terminal of the tenth resistor, the control subunit, the first terminal of the third energy storage element, and the first terminal of the seventeenth MOSFET; the first terminal of the ninth resistor is connected to the control subunit and the second terminal of the sixteenth MOSFET, and the second terminal of the ninth resistor is connected to the second terminal of the seventeenth MOSFET, the control subunit, the first terminal of the fourth energy storage element, and the first terminal of the first inverter; the second terminal of the first inverter is connected to the first terminal of the sixteenth MOSFET, and the third terminal of the sixteenth MOSFET is used to input startup current to the clamping unit; the second terminals of the tenth resistor, the third energy storage element, the seventeenth MOSFET, and the fourth energy storage element are all grounded.
[0016] This application also provides a chip including any of the above-described bandgap reference circuits.
[0017] This application also provides a bandgap reference voltage source, including any of the above-described bandgap reference circuits or any of the above-described chips.
[0018] This application provides an electronic device, including a housing, wherein any of the above-mentioned bandgap reference circuits, any of the above-mentioned chips, or any of the above-mentioned bandgap reference voltage sources are disposed within the housing.
[0019] The bandgap reference circuit provided in this embodiment clamps the voltage clamping point to obtain the clamping voltage through the clamping unit. Then, the reference voltage output unit can respond to the clamping voltage and generate the bandgap reference voltage to weaken the influence of the offset voltage, improve the accuracy of the bandgap reference voltage, and enable the output bandgap reference voltage to obtain higher accuracy, thereby further ensuring the stability of the circuit. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A schematic diagram of the structure of a bandgap reference circuit provided by the prior art.
[0022] Figure 2This is a schematic diagram of the bandgap reference circuit provided in an embodiment of this application.
[0023] Figure 3 A schematic diagram of an optional bandgap reference circuit provided in an embodiment of this application.
[0024] Figure 4 A schematic diagram of an optional bandgap reference circuit provided in an embodiment of this application.
[0025] Figure 5 A schematic diagram of the circuit structure of the bandgap reference circuit provided in the embodiments of this application.
[0026] Figure Labels 10-Clamping unit; 20-Reference voltage output unit; 30-Feedback compensation unit; 40-Bias unit; 50-Startup unit; 101-Operational amplifier subunit; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; R7 - Seventh resistor; R8 - Eighth resistor; R9 - Ninth resistor; R10 - Tenth resistor; M1 - First MOSFET; M2 - Second MOSFET; M3 - Third MOSFET; M4 - Fourth MOSFET; M5 - Fifth MOSFET; M6 - Sixth MOSFET; M7 - Seventh MOSFET; M8 - Eighth MOSFET; M9 - Ninth MOSFET; M10 - Tenth MOSFET; M11 - Eleventh MOSFET; M12 - Twelfth MOSFET; M13 - Thirteenth MOSFET; M14 - Fourteenth MOSFET; M15 - Fifteenth MOSFET; M16 - Sixteenth MOSFET; M17 - Seventeenth MOSFET; M18 - Eighteenth MOSFET; C1 - First capacitor; C2 - Second capacitor; C3 - Third capacitor; C4 - Fourth capacitor; C5 - Fifth capacitor; Q1 - First transistor; Q2 - Second transistor; Q3 - Third transistor; Q4 - Fourth transistor; A1 - First inverter; A2 - Second inverter; A3 - Third inverter. Detailed Implementation
[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and their technical features can be combined with each other.
[0028] like Figure 1 As shown, Figure 1 This is a schematic diagram of a bandgap reference circuit provided by the prior art. In existing bandgap reference circuits, designers typically use operational amplifiers to clamp the voltage at nodes A and B in the core bandgap circuit. However, factors detrimental to the stability of the bandgap reference voltage often arise at these nodes. This is because the operational amplifier used for voltage clamping has an offset voltage at its input, which causes deviations in the positive and negative temperature coefficient voltages, thus affecting the accuracy of the bandgap reference voltage and causing circuit instability.
[0029] Therefore, in order to reduce the impact of offset voltage on the accuracy of the bandgap reference voltage and the stability of the circuit, this invention discloses a bandgap reference circuit. This circuit can be applied to self-biased bandgap reference circuits with low offset voltage, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of the bandgap reference circuit provided in an embodiment of this application.
[0030] This application provides a bandgap reference circuit, comprising: Clamping unit 10 is used to clamp the voltage clamping point and output the clamping voltage; the voltage clamping point may include a point in the bandgap reference circuit that characterizes the voltage of the corresponding transistor, for example, in subsequent... Figure 3 Points M and N are shown.
[0031] The reference voltage output unit 20 is connected to the clamping unit 10 and is used to receive the clamping voltage and output the corresponding bandgap reference voltage.
[0032] During the operation of the bandgap reference circuit, the clamping unit 10 clamps the voltage clamping point to obtain the clamping voltage. However, since there is already an offset voltage when the voltage clamping is performed, the accuracy of the clamping voltage obtained at this time is affected by the offset voltage. In order to obtain better reference voltage accuracy and ensure the stability of the bandgap reference voltage output, this embodiment improves the connection method between the reference voltage output unit 20 and the clamping unit 10. When the clamping voltage is output from the clamping point, the reference voltage output unit 20 responds to the clamping voltage and outputs the corresponding bandgap reference voltage, gradually reducing / weakening the impact of the offset voltage on the accuracy of the reference voltage, thereby improving the accuracy of the bandgap reference voltage.
[0033] Optionally, to obtain a stable bandgap reference voltage, the clamping unit 10 can be a clamping circuit composed of switching pairs. The switching pairs can be diodes or transistors. Preferably, in this embodiment, the switching pairs used in the clamping circuit to obtain a stable reference voltage are transistors.
[0034] In order to obtain a low offset bandgap reference voltage after obtaining the clamping voltage, the bandgap reference circuit provided in this embodiment can obtain a higher precision reference voltage by setting the reference voltage output unit 20 to respond to the clamping voltage output by the clamping unit 10.
[0035] Optionally, the reference voltage output unit 20 can be a component with a preset resistance value calculated by the user according to requirements. Optionally, for ease of accuracy adjustment, the reference voltage output unit 20 can be an adjustable resistor.
[0036] like Figure 3 As shown, Figure 3 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of this application. The bandgap reference circuit provided in this embodiment may include the clamping unit 10 and the reference voltage output unit 20 provided in the above embodiment.
[0037] It should be noted that in this embodiment, points M and N are voltage clamping points, and V DD For power supply, V REF This is the output terminal of the bandgap reference voltage. The normal startup current of this bandgap reference circuit is obtained from point a, so that the bandgap reference circuit can be taken out of the initial state. Its startup current can be provided by the startup circuit, power supply unit or module, and in this embodiment, the current and power of the circuit meet the design requirements.
[0038] Optionally, the starting current at point a can be output by the starting circuit.
[0039] In one example, the clamping unit 10 may include an operational amplifier subunit 101, which is used to clamp the voltage clamping point so that the clamping unit 10 outputs a clamping voltage.
[0040] In one example, the reference voltage output unit 20 may include a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, which can form a bandgap reference voltage output circuit.
[0041] In this configuration, the first terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2. The second terminal of the first transistor Q1 is connected to the first terminal of the first resistor R1, the third terminal of the second transistor Q2, and the clamping unit 10. The second terminal of the first resistor R1 is connected to the first terminal of the third resistor R3, the third terminal of the first transistor Q1, and the second terminal of the second resistor R2. The second terminal of the second transistor Q2 is connected to the first terminal of the second resistor R2 and the clamping unit 10. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is used to output the bandgap reference voltage. The first terminal of the fifth resistor R5 is connected to the first terminal of the first transistor Q1 and the second terminal of the second transistor Q2. The second terminal of the fifth resistor R5 is grounded.
[0042] The operational amplifier subunit 101 may include a third transistor Q3, a fourth transistor Q4, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4. These devices can form an operational amplifier circuit.
[0043] In this configuration, the first terminals of the third transistor Q3 and the fourth transistor Q4 are both grounded. The second terminals of the third transistor Q3 and the fourth transistor Q4 are both connected to the reference voltage output unit 20. The third terminal of the third transistor Q3 is connected to the first terminal of the first MOSFET M1. The second terminal of the first MOSFET M1 is connected to the second terminal of the second MOSFET M2 and the reference voltage output unit 20, respectively. The third terminal of the first MOSFET M1 is connected to the first terminal of the third MOSFET M3, the second terminal of the third MOSFET M3, and the second terminal of the fourth MOSFET M4, respectively. The third terminal of the fourth transistor Q4 is connected to the first terminal of the second MOSFET M2. The third terminal of the second MOSFET M2 is connected to the first terminal of the fourth MOSFET M4. The third terminals of the third MOSFET M3 and the third terminal of the fourth MOSFET M4 are both connected to the power supply.
[0044] Among them, the first end of the third resistor R3 is connected to the reference voltage output unit 20, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and the operational amplifier subunit 101 respectively, the second end of the fourth resistor R4 is used to output the bandgap reference voltage, the first end of the fifth resistor R5 is connected to the reference voltage output unit 20, and the second end of the fifth resistor R5 is grounded.
[0045] In this embodiment, the operational amplifier subunit 101 performs voltage clamping on points M and N in the reference voltage output unit 20. Then, the reference voltage output unit 20 generates the corresponding bandgap reference voltage in response to the clamping voltage at the voltage clamping point. By improving the connection method between the reference voltage output unit 20 and the clamping unit 10, the influence of offset voltage on the bandgap reference voltage can be reduced. The accuracy of the bandgap reference voltage can be improved by setting the reference voltage output unit 20.
[0046] like Figure 4 As shown, Figure 4 This is a schematic diagram of a bandgap reference circuit provided in another embodiment of this application. The bandgap reference circuit provided in this embodiment includes: a clamping unit 10, an operational amplifier subunit 101, a reference voltage output unit 20, a feedback compensation unit 30, a bias unit 40, and a startup unit 50 as provided in the above embodiment. The clamping unit 10, the operational amplifier subunit 101, the reference voltage output unit 20, the feedback compensation unit 30, and the bias unit 40 constitute the bandgap reference unit 60.
[0047] When the bandgap reference unit 60 is powered on, the startup unit 50 injects current into the relevant nodes of the clamping unit 10 and the reference voltage output unit 20 to cause the bandgap reference circuit to leave the initial state. Then, the corresponding nodes in the clamping unit 10 perform voltage clamping. After that, the reference voltage output unit 20 responds to the corresponding clamping voltage and generates the corresponding bandgap reference voltage, thereby reducing the offset voltage generated by the operational amplifier and improving the accuracy of the bandgap reference voltage.
[0048] Optionally, to ensure the normal operation of the bandgap reference circuit, the operational amplifier subunit 101 can be implemented using current transistors and power transistors to achieve two-stage amplification, or it can be implemented using existing operational amplifier modules.
[0049] Optionally, in this embodiment, both the startup unit 50 and the bandgap reference unit 60 need to be connected to a separate power supply VDD or grounded.
[0050] Optionally, in this embodiment, the stability of the bandgap reference voltage can be further ensured by using a negative feedback connection between the output terminal of the operational amplifier subunit 101 and the reference voltage output unit 101.
[0051] Optional, such as Figure 5 As shown, Figure 5 This is a schematic diagram of an optional bandgap reference circuit provided in an embodiment of this application. To ensure stable operation of the bandgap reference circuit, the bandgap reference circuit provided in this embodiment may include: a clamping unit 10, a reference voltage output unit 20, a startup unit 50, a feedback compensation unit 30, and a bias unit 40. The clamping unit further includes an operational amplifier unit 101, and the startup unit further includes a control subunit and a startup subunit.
[0052] The startup unit 50 is connected to the clamping unit 10 and the bias unit 50 respectively, and is used to start the operational amplifier subunit 102. The feedback compensation unit 30 starts the reference voltage output unit 20 and the bias unit 50 to realize the startup of the entire bandgap reference circuit.
[0053] Optionally, a control subunit is used to receive an enable signal sent by the control terminal and output an enable control signal.
[0054] The startup subunit is connected to the control subunit, clamping unit 10 and biasing unit 40 respectively. It is used to acquire the enable control signal, input the startup current to the clamping unit 10 according to the enable control signal, and copy the bias current of the biasing unit 40 to the biasing unit.
[0055] The feedback compensation unit 30 is connected to the clamping unit 10 and the reference voltage output unit 20, and is used to compensate the clamping unit 10 and the reference voltage output unit 20. Specifically, it can compensate for parameters such as the phase margin of the clamping unit 10 and the reference voltage output unit 20. The feedback compensation unit 30 can be an energy storage element, such as a capacitor.
[0056] The bias unit 40 is connected to the operational amplifier subunit 101 of the clamping unit 10 and the reference voltage output unit 20 respectively, and is used to provide bias voltage to the operational amplifier subunit 101 and the reference voltage output unit 20.
[0057] The bandgap reference circuit provided in this application embodiment injects current into node a of the clamping unit 10 to free the bandgap reference from its initial state. The operational amplifier subunit 101 in the clamping unit 10 maintains equal voltages at the two voltage clamping points of the reference voltage output unit 20. The feedback voltage output by the operational amplifier subunit 101 is then output to the reference voltage output unit 20 to form a feedback loop, thereby promoting the stability of the bandgap reference voltage. Optionally, the bandgap reference circuit provided in this application embodiment can be used in analog integrated circuits.
[0058] like Figure 5 As shown, Figure 5 This is a schematic diagram of the circuit structure of the bandgap reference circuit provided in an embodiment of this application. The bandgap reference circuit provided in this application includes the various units provided in the above embodiments, and the circuit corresponding to each unit can be: The clamping unit 10 includes a third transistor Q3, a fourth transistor Q4, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4.
[0059] The reference voltage output unit 20 includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.
[0060] The feedback compensation unit 30 includes a first energy storage element C1, a second energy storage element C2, a sixth resistor R6, and an eighth MOSFET M8.
[0061] The bias unit 50 includes a seventh resistor R7, a fifth transistor Q5, a fifth MOSFET M5, a sixth MOSFET M6, and a seventh MOSFET M7.
[0062] In some embodiments, when there is no need to output the digital signal BG_OK, the startup unit 50 may include: a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11; a thirteenth MOSFET M13, a ninth resistor R9, a first inverter A1, a sixteenth MOSFET M16, a tenth resistor R10, a third energy storage element C3, a seventeenth MOSFET M17, and a fourth energy storage element C4.
[0063] In some embodiments, when it is necessary to output the digital signal BG_OK, the startup unit 50 may include the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the thirteenth MOSFET M13, the fourteenth MOSFET M14, the eighth resistor R8, the ninth resistor R9, the fifteenth MOSFET M15, the first inverter A1, the sixteenth MOSFET M16, the second inverter A2, the third inverter A3, the tenth resistor R10, the third energy storage element C3, the seventeenth MOSFET M17, the fourth energy storage element C4, the eighteenth MOSFET M18, and the fifth energy storage element C5.
[0064] In addition, in this embodiment, the voltage clamping point may include: a first clamping point M and a second clamping point N.
[0065] The bandgap reference circuit provided in this embodiment may include a clamping unit 10, a reference voltage output unit 20, a feedback compensation unit 30, and a bias unit 40. The connection relationship of the devices included in each unit is as follows: the first end of the first transistor Q1 is connected to the first end of the second transistor Q2; the second end of the first transistor Q1 is connected to the first end of the first resistor R1, the second end of the third transistor Q3, and the third end of the second transistor Q2; the second end of the first resistor R1 is connected to the first end of the third resistor R3, the third end of the first transistor Q1, the second end of the second resistor R2, and the second end of the fifth transistor Q5; the second end of the second transistor Q2 is connected to the first end of the second resistor R2, the second end of the first energy storage element C1, and the second end of the fourth transistor Q4.
[0066] The first terminals of the third transistor Q3 and the fourth transistor Q4 are both grounded. The second terminal of the third transistor Q3 is connected to the third terminal of the second transistor Q2, the second terminal of the first transistor Q1, and the first terminal of the first resistor R1. The second terminal of the fourth transistor Q4 is connected to the second terminal of the first energy storage element C1 and the second terminal of the second transistor Q2. The third terminal of the third transistor Q3 is connected to the first terminal of the first MOSFET M1. The second terminal of the first MOSFET M1 is connected to the second terminal of the second MOSFET M2, the second terminal of the fifth MOSFET M5, the second terminal of the third resistor R3, and the second terminal of the fourth transistor Q4. The first terminal of the fourth resistor R4 is connected to the first terminal of the first MOSFET M1, the second terminal of the third MOSFET M3, and the second terminal of the fourth MOSFET M4 are connected to the first terminal of the third MOSFET M3, the second terminal of the third MOSFET M3, and the second terminal of the fourth MOSFET M4, respectively. The third terminal of the fourth transistor Q4 is connected to the first terminal of the second MOSFET M2, the third terminal of the second MOSFET M2 is connected to the first terminal of the fourth MOSFET M4, the second terminal of the sixth resistor R6, the second terminal of the eighth MOSFET M8, and the third terminal of the sixteenth MOSFET M16, respectively. The third terminals of the third MOSFET M3 and the third terminals of the fourth MOSFET M4 are both connected to the power supply VDD.
[0067] The first end of the third resistor R3 is connected to the first end of the first resistor R1, the third end of the first transistor Q1, the second end of the second resistor R2, and the second end of the fifth transistor Q5. The second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fifth MOSFET M5, the second end of the first MOSFET M1, and the second end of the second MOSFET M2. The second end of the fourth resistor R4 is connected to the third end of the eighth MOSFET M8 and the first end of the first energy storage element. The second end of the fourth resistor R4 is also used to output a reference voltage. The first end of the fifth resistor R5 is connected to the first end of the first transistor Q1 and the first end of the second transistor Q2. The second end of the fifth resistor R5 is grounded.
[0068] The first terminal of the first energy storage element C1 is connected to the second terminal of the fourth resistor R4 and the third terminal of the eighth MOSFET M8. The second terminal of the first energy storage element C1 is connected to the second terminal of the second transistor Q2, the second terminal of the second resistor R2, the second terminal of the fourth transistor Q4, and the second terminal of the second energy storage element C2. The first terminal of the second energy storage element C2 is connected to the second terminal of the sixth resistor R6. The first terminal of the sixth resistor R6 is connected to the third terminal of the second MOSFET M2, the first terminal of the fourth MOSFET M4, the second terminal of the eighth MOSFET M8, and the third terminal of the sixteenth MOSFET M16.
[0069] The first terminal of the seventh resistor R7 is grounded. The second terminal of the seventh resistor R7 is connected to the first terminal of the fifth transistor Q5. The second terminal of the fifth transistor Q5 is connected to the second terminal of the second resistor R2, the second terminal of the first resistor R1, the first terminal of the third resistor R3, and the third terminal of the first transistor Q1. The third terminal of the fifth transistor Q5 is connected to the first terminal of the fifth MOSFET M5. The second terminal of the fifth MOSFET M5 is connected to the second terminal of the third resistor R3, the first terminal of the fourth resistor R4, the second terminal of the first MOSFET M1, and the second terminal of the second MOSFET M2. The third terminal of the fifth MOSFET M5 is connected to the first terminal of the sixth MOSFET M6, the second terminal of the sixth MOSFET M6, and the second terminal of the seventh MOSFET M7. The third terminals of the sixth MOSFET M6 and the seventh MOSFET M7 are connected to the power supply. The first terminal of the seventh MOSFET M7 is connected to the startup unit 50.
[0070] The first terminal of the eighth MOSFET M8 is connected to the power supply VDD. The second terminal of the eighth MOSFET M8 is connected to the first terminal of the sixth resistor R6, the third terminal of the second MOSFET M2, the first terminal of the fourth MOSFET M4, and the third terminal of the sixteenth MOSFET M16. The third terminal of the eighth MOSFET M8 is connected to the first terminal of the first energy storage element C1 and the second terminal of the fourth resistor R4.
[0071] Optionally, when the output of the digital signal BG_OK is not required, the circuit of the startup unit 50 can be as follows: the first terminal of the ninth MOSFET M9 is connected to the power supply; the second terminals of the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 are all used to receive the enable signal; the third terminal of the ninth MOSFET M9 is connected to the first terminal of the ninth resistor R9 and the first terminal of the sixteenth MOSFET M16, respectively; the first terminal of the tenth MOSFET M10 is connected to the first terminal of the tenth resistor R10, the third terminal of the thirteenth MOSFET M13, the first terminal of the third energy storage element C3, and the second terminal of the seventeenth MOSFET M17, respectively; the first terminal of the eleventh MOSFET M11 is connected to the first terminal of the fourth energy storage element C4, the second terminal of the ninth resistor R9, the first terminal of the seventeenth MOSFET M17, and the first terminal of the first inverter A1, respectively; and the third terminals of the tenth MOSFET M10 and the eleventh MOSFET M11 are both grounded.
[0072] The first terminal of the thirteenth MOSFET M13 is connected to the power supply, the second terminal of the thirteenth MOSFET M13 is connected to the bias unit, and the third terminal of the thirteenth MOSFET M13 is connected to the first terminal of the tenth resistor R10, the first terminal of the tenth MOSFET M10, the first terminal of the third energy storage element C3, and the second terminal of the seventeenth MOSFET M17.
[0073] The first terminal of the ninth resistor R9 is connected to the third terminal of the ninth MOSFET M9 and the second terminal of the sixteenth MOSFET M16. The second terminal of the ninth resistor R9 is connected to the first terminal of the seventeenth MOSFET M17, the first terminal of the eleventh MOSFET M11, the first terminal of the fourth energy storage element C4, and the first terminal of the first inverter A1. The second terminal of the first inverter A1 is connected to the first terminal of the sixteenth MOSFET M16. The third terminal of the sixteenth MOSFET M16 is connected to the first terminal of the sixth resistor R6, the third terminal of the second MOSFET M2, the first terminal of the fourth MOSFET M4, and the second terminal of the eighth MOSFET M8. The third terminal of the sixteenth MOSFET M16 is used to input the start-up current to the clamping unit 10 and the reference voltage output unit 20. The second terminals of the tenth resistor R10, the third terminal of the third energy storage element C3, the third terminal of the seventeenth MOSFET M17, and the second terminal of the fourth energy storage element C4 are all grounded.
[0074] Optionally, when the digital signal BG_OK needs to be output, the circuit of the startup unit 50 can be as follows: the first terminal of the ninth MOSFET M9 is connected to the power supply; the second terminals of the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 are all used to receive the enable signal; the third terminal of the ninth MOSFET M9 is connected to the first terminal of the ninth resistor R9 and the first terminal of the sixteenth MOSFET M16, respectively; the first terminal of the tenth MOSFET M10 is connected to the first terminal of the tenth resistor R10, the third terminal of the thirteenth MOSFET M13, the first terminal of the third energy storage element C3, and the first terminal of the seventeenth MOSFET M17, respectively. The first terminal of the eleventh MOSFET M11 is connected to the first terminal of the fourth energy storage element C4, the second terminal of the ninth resistor R9, the first terminal of the seventeenth MOSFET M17, the second terminal of the eighteenth MOSFET M18, and the first terminal of the first inverter A1. The first terminal of the twelfth MOSFET M12 is connected to the first terminal of the fifth energy storage element C5, the first terminal of the second inverter A2, the third terminal of the fifteenth MOSFET M15, the third terminal of the fourteenth MOSFET M14, and the first terminal of the eighteenth MOSFET M18. The third terminals of the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 are all grounded.
[0075] The first terminal of the thirteenth MOSFET M13, the first terminal of the fourteenth MOSFET M14, and the first terminal of the eighth resistor R8 are all connected to the power supply. The second terminal of the thirteenth MOSFET M13 and the second terminal of the fourteenth MOSFET M14 are both connected to the bias unit. The third terminal of the thirteenth MOSFET M13 is connected to the first terminal of the tenth resistor R10, the first terminal of the tenth MOSFET M10, the first terminal of the third energy storage element C3, and the second terminal of the seventeenth MOSFET M17, respectively.
[0076] The third terminal of the fourteenth MOSFET M14 is connected to the third terminal of the fifteenth MOSFET M15, the first terminal of the eighteenth MOSFET M18, the first terminal of the fifth energy storage element C5, the first terminal of the twelfth MOSFET M12, and the first terminal of the second inverter A2.
[0077] The second terminal of the eighth resistor R8 is connected to the first terminal of the fifteenth MOSFET M15. The second terminal of the fifteenth MOSFET M15 is connected to the second terminal of the second inverter A2 and the first terminal of the third inverter A3, respectively. The second terminal of the third inverter A3 is used to send system test signals. The first terminal of the ninth resistor R9 is connected to the third terminal of the ninth MOSFET M9 and the second terminal of the sixteenth MOSFET M16, respectively. The second terminal of the ninth resistor R9 is connected to the first terminal of the seventeenth MOSFET M17, the first terminal of the eleventh MOSFET M11, the first terminal of the fourth energy storage element C4, the second terminal of the eighteenth MOSFET M18, and the first terminal of the first inverter A1, respectively. The second terminal of inverter A1 is connected to the first terminal of the sixteenth MOSFET M16. The third terminal of the sixteenth MOSFET M16 is connected to the first terminal of the sixth resistor R6, the third terminal of the second MOSFET M2, the first terminal of the fourth MOSFET M4, and the second terminal of the eighth MOSFET M8. The third terminal of the sixteenth MOSFET M16 is used to input the start-up current to the clamping unit 10 and the reference voltage output unit 20. The second terminal of the tenth resistor R10, the second terminal of the third energy storage element C3, the third terminal of the seventeenth MOSFET M17, the second terminal of the fourth energy storage element C4, the third terminal of the eighteenth MOSFET M18, and the second terminal of the fifth energy storage element C5 are all grounded.
[0078] Optionally, in this embodiment, a first clamping point M and a second clamping point N are also provided. The first clamping point M is located at the connection between the first end of the first resistor R1 and the second end of the first transistor Q1; the second clamping point N is located at the connection between the first end of the second resistor R2 and the second end of the second transistor Q2.
[0079] Optionally, the type of power transistor or current transistor used in this embodiment can be flexibly set according to user needs, for example, using a PMOS transistor or an MMOS transistor.
[0080] Optionally, the inventors... Figure 1 and Figure 5 Comparative analysis revealed that in Figure 1 In the classic bandgap reference core circuit shown, a voltage ΔV with a positive temperature coefficient is obtained by clamping the op-amp. BE After considering the operational amplifier offset, the bandgap reference voltage V REF =V BE +[(ΔV BE +V OS ) / R1'](R1'+R2'). And in Figure 5 In this configuration, the second terminal of transistor Q1 and the third terminal of transistor Q2 are directly connected to the corresponding resistors. This connection method directly yields a voltage ΔV with a positive temperature coefficient. BE The clamping of the op-amp can ensure the flow... Figure 5 The currents in R1 and R2 are equal. Considering the operational amplifier's offset, the current through R1 is I. R1 =ΔV BE The current through R1 and R2 is I. R2 =(ΔV BE +V OS ) / R2=(ΔV BE +V OS If ) / R1, then after considering the op-amp offset, we have: V REF =V BE +(I R1 +I R2 (R5+R3+R4)=V BE +[(2ΔV BE +V OS ) / R1](R5+R3+R4). A comparison shows that... Figure 5 The op-amp input offset voltage V OS It accounts for a smaller proportion of the bandgap reference voltage, which can further reduce the impact of offset.
[0081] Additionally, please see Figure 5 As shown, in Figure 5 In the above, the operational amplifier subunit 102 performs voltage clamping on the first clamping point M and the second clamping point N of the reference voltage output unit, so that M=N and its resistance R1=R2.
[0082] The formula for calculating the bandgap reference voltage can be: V REF =V BE +[(2ΔV BE / R1)(R3+R4+R5)] Among them, V REF V is the bandgap reference voltage. BE Voltage with a negative temperature coefficient, ΔV BE R3, R4, R5, and R1 are adjustable resistors with a positive temperature coefficient.
[0083] From the above formula, it can be seen that to obtain a bandgap reference voltage V with zero temperature coefficient... REF In V BE ΔV BE Given the information, the bandgap reference voltage V can also be adjusted by setting R3, R4, R5, and R1. REF It has a zero temperature coefficient, thereby increasing the bandgap reference voltage V.REF Precision.
[0084] Optionally, in this embodiment, to reduce offset voltage and improve the accuracy of the bandgap reference voltage, the input transistors in the operational amplifier subunit 102 can be set as BJTs (Bipolar Junction Transistors), namely Q3 and Q4. The voltage and current of a BJT are exponentially related, while the voltage and current of a MOSFET are quadratically related. Using BJTs as the input pair results in a smaller input offset than using MOSFETs, thereby obtaining a more accurate bandgap reference voltage V. REF .
[0085] Optionally, since the drain voltage of the first MOSFET M1 is higher and the drain voltage of the second MOSFET M2 is lower, to avoid reverse leakage to ground or the fourth transistor Q4 caused by the parasitic diode in the first MOSFET M1, which would lead to voltage imbalance in the third transistor Q3 and the fourth transistor Q4, the first MOSFET M1 and the second MOSFET M2 are connected without a substrate bias, with their substrates connected to the source of the first MOSFET M1. Simultaneously, this circuit can autonomously generate an IPTAT current, which powers the internal startup circuit, the BG_OK circuit, and other external circuits, eliminating the need for a separate external startup circuit. In other words, by including a bias unit 50 in the clamping unit 10, a separate bias circuit is unnecessary, thereby reducing current branches and saving power.
[0086] Additionally, please see Figure 5 When the enable signal ENN is high, the ninth MOSFET M9 is turned on, while the tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 are turned off. However, during initial power-up, the bandgap reference circuit has not yet established the bandgap reference voltage V. REF At that time, current is injected into point a from the third terminal (source terminal) of the sixteenth MOSFET M16, thereby completing the startup of clamping unit 10. Meanwhile, the bandgap reference voltage V is established in the bandgap reference circuit. REF Subsequently, the third MOSFET M3 and the fourteenth MOSFET M14 can copy current from the IPTAT current mirror. Furthermore, the current in the thirteenth MOSFET M13 generates a voltage drop across the tenth resistor R10, causing the seventeenth MOSFET M17 to conduct, and then turning off the sixteenth MOSFET M16, so that the startup current is no longer injected into the clamping unit 10.
[0087] Optionally, after the startup current is no longer injected into the clamping unit 10, the bandgap reference circuit still works normally, but the eighteenth MOSFET M18 is turned off, and the current copied from the fourteenth MOSFET M14 will charge the fifth energy storage element C5. After a certain delay time, wait for the BG_OK output high-level indication signal.
[0088] The bandgap reference circuit provided in this application adopts a self-biased structure, which has fewer branches and area costs; and the circuit can achieve a smaller offset effect through optimization of the circuit unit structure without adding additional functional circuits.
[0089] This embodiment also provides a chip, including the bandgap reference circuit provided in any of the above embodiments. The bandgap reference circuit can be a semiconductor integrated circuit, and the layout structure of its bandgap reference circuit is etched onto a silicon wafer to form a semiconductor chip.
[0090] This embodiment provides a bandgap reference voltage source, including the bandgap reference circuit or the chip provided in any of the above embodiments. The bandgap reference circuit can also be built using discrete components. In this embodiment, the provided bandgap reference voltage source is mainly for stabilizing the operating state of the circuit / electronic device.
[0091] This embodiment provides an electronic device, including a housing, in which a bandgap reference circuit, a chip, or a bandgap reference voltage source provided in any of the above embodiments are disposed.
[0092] It should be noted that the embodiments described above in this application can be combined with each other to work together to improve the accuracy of the existing reference voltage and make its reference voltage stable. Examples will not be given one by one here.
[0093] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0094] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0095] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0097] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0098] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
Claims
1. A bandgap reference circuit, characterized in that, include: The clamping unit is used to clamp the voltage clamping point and output the clamping voltage. A reference voltage output unit, connected to the clamping unit, is used to receive the clamping voltage and output the corresponding bandgap reference voltage; The reference voltage output unit includes: a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The first terminal of the first transistor is connected to the first terminal of the second transistor. The second terminal of the first transistor is connected to the first terminal of the first resistor, the third terminal of the second transistor, and the clamping unit to form a first clamping point. The second terminal of the first resistor is connected to the first terminal of the third resistor, the third terminal of the first transistor, and the second terminal of the second resistor. The second terminal of the second transistor is connected to the first terminal of the second resistor and the clamping unit to form a second clamping point. The second terminal of the third resistor is connected to the first terminal of the fourth resistor, which is used to output a bandgap reference voltage. The first terminal of the fifth resistor is connected to the first terminal of the first transistor and the second terminal of the second transistor, and the second terminal of the fifth resistor is grounded.
2. The bandgap reference circuit according to claim 1, characterized in that, The clamping unit includes: The operational amplifier subunit is connected to the reference voltage output unit and is used to clamp the voltage clamping point and output the clamping voltage to the reference voltage output unit.
3. The bandgap reference circuit according to claim 2, characterized in that, Also includes: A feedback compensation unit is connected to the clamping unit and the reference voltage output unit respectively, and is used to compensate the clamping unit and the reference voltage output unit; The bias unit is connected to both the clamping unit and the reference voltage output unit, and is used to provide a bias voltage to the clamping unit.
4. The bandgap reference circuit according to claim 3, characterized in that, Also includes: The startup unit is connected to the clamping unit and the bias unit respectively, and is used to start the operational amplifier subunit and start the reference voltage output unit and the bias unit through the feedback compensation unit.
5. The bandgap reference circuit according to claim 4, characterized in that, The startup unit includes: The control subunit is used to receive the enable signal sent by the control terminal and output the enable control signal; The startup subunit is connected to the control subunit, the clamping unit, and the biasing unit, respectively, and is used to acquire the enable control signal, input a startup current to the clamping unit according to the enable control signal, and copy the bias current of the biasing unit to the biasing unit.
6. The bandgap reference circuit according to claim 2, characterized in that, The operational amplifier subunit includes: a third transistor, a fourth transistor, a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET; The first terminals of the third transistor and the fourth transistor are both grounded. The second terminals of the third transistor and the fourth transistor are both connected to the reference voltage output unit. The third terminal of the third transistor is connected to the first terminal of the first MOSFET. The second terminal of the first MOSFET is connected to the second terminal of the second MOSFET and the reference voltage output unit. The third terminal of the first MOSFET is connected to the first terminal of the third MOSFET, the second terminal of the third MOSFET, and the second terminal of the fourth MOSFET. The third terminal of the fourth transistor is connected to the first terminal of the second MOSFET. The third terminal of the second MOSFET is connected to the first terminal of the fourth MOSFET. The third terminals of both the third and fourth MOSFETs are connected to a power supply.
7. The bandgap reference circuit according to claim 3, characterized in that, The feedback compensation unit includes: a first energy storage element, a second energy storage element, a sixth resistor, and an eighth MOSFET; The first terminal of the first energy storage element is connected to the reference voltage output unit and the first terminal of the eighth MOS transistor, respectively; the second terminal of the first energy storage element is connected to the reference voltage output unit and the clamping unit, respectively; the second terminal of the eighth MOS transistor is connected to the clamping unit and the first terminal of the first resistor, respectively, and the third terminal of the eighth MOS transistor is connected to the power supply; the second terminal of the sixth resistor is connected to the first terminal of the second energy storage element, and the second terminal of the second energy storage element is connected to the second terminal of the first energy storage element, the reference voltage output unit, and the clamping unit, respectively.
8. The bandgap reference circuit according to claim 4, characterized in that, The bias unit includes: a seventh resistor, a fifth transistor, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET; The first terminal of the seventh resistor is grounded, the second terminal of the seventh resistor is connected to the first terminal of the fifth transistor, the second terminal of the fifth transistor is connected to the reference voltage output unit, the third terminal of the fifth transistor is connected to the first terminal of the fifth MOSFET, the second terminal of the fifth MOSFET is connected to both the reference voltage output unit and the clamping unit, the third terminal of the fifth MOSFET is connected to the first terminal of the sixth MOSFET, the second terminal of the sixth MOSFET, and the second terminal of the seventh MOSFET, the third terminals of the sixth MOSFET and the seventh MOSFET are both connected to the power supply, and the first terminal of the seventh MOSFET serves as a bias signal receiver to receive the bias signal.
9. The bandgap reference circuit according to claim 5, characterized in that, The control subunit includes: a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; The first terminal of the ninth MOS transistor is connected to the power supply. The second terminals of the ninth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are all used to receive the enable signal. The third terminal of the ninth MOS transistor, the first terminal of the tenth MOS transistor, and the first terminal of the eleventh MOS transistor are all connected to the startup subunit. The third terminals of the tenth MOS transistor and the eleventh MOS transistor are both grounded.
10. The bandgap reference circuit according to claim 5, characterized in that, The startup subunit includes: a thirteenth MOSFET, a ninth resistor, a first inverter, a sixteenth MOSFET, a tenth resistor, a third energy storage element, a seventeenth MOSFET, and a fourth energy storage element; The first terminal of the thirteenth MOSFET is connected to the power supply, and the second terminal of the thirteenth MOSFET is connected to the bias unit; the third terminal of the thirteenth MOSFET is connected to the first terminal of the tenth resistor, the control subunit, the first terminal of the third energy storage element, and the first terminal of the seventeenth MOSFET, respectively. The first end of the ninth resistor is connected to the second end of the control subunit and the sixteenth MOS transistor, respectively. The second end of the ninth resistor is connected to the second end of the seventeenth MOS transistor, the control subunit, the first end of the fourth energy storage element, and the first end of the first inverter, respectively. The second terminal of the first inverter is connected to the first terminal of the sixteenth MOS transistor, and the third terminal of the sixteenth MOS transistor is used to input the start-up current to the clamping unit; The second terminal of the tenth resistor, the second terminal of the third energy storage element, the third terminal of the seventeenth MOS transistor, and the second terminal of the fourth energy storage element are all grounded.
11. A chip, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1-10.
12. A bandgap reference voltage source, characterized in that, This includes the bandgap reference circuit as described in any one of claims 1-10 or the chip as described in claim 11.
13. An electronic device, characterized in that, It includes a housing, within which is disposed a bandgap reference circuit as described in any one of claims 1-10, a chip as described in claim 11, or a bandgap reference voltage source as described in claim 12.