Clock switching circuit, clock module, chip and computing device applying the same

Abstract

The application provides a clock switching circuit, a clock module, a chip and a computing device using the clock switching circuit. The clock switching circuit comprises a first synchronization unit configured to receive a selection signal and a first clock signal, and output a first selection synchronization signal; a second synchronization unit configured to receive the selection signal and a second clock signal, and output a second selection synchronization signal; an enable signal generation unit configured to generate a first clock enable signal and a second clock enable signal according to the first selection synchronization signal and the second selection synchronization signal; an enable signal feedback synchronization unit configured to synchronize the first clock enable signal with the second clock signal, and synchronize the second clock enable signal with the first clock signal; a gated clock unit configured to transmit the first clock signal and the second clock signal according to the first clock enable signal and the second clock enable signal; and an output gating unit configured to select the first clock signal or the second clock signal for output.

Description

Technical Field

[0001] This invention relates to a clock switching circuit, and more particularly to a clock switching circuit that can avoid glitches during clock switching, as well as clock modules, chips and computing devices using the same. Background Technology

[0002] As chip technology advances, chips are becoming increasingly larger and their clock structures more complex. Chip operating clocks need to adapt to different operating scenarios and power consumption and performance requirements, thus necessitating frequency switching during operation.

[0003] Clock frequency switching can be achieved by modifying the division factor of the frequency divider, but the frequency achievable by this method is always a multiple of the source clock. In practice, switching between different source clocks is still necessary. Because the clocks are from different sources, switching through a traditional clock gating unit (mux) will inevitably produce clock glitches, affecting chip operation and potentially causing chip failure in severe cases.

[0004] Therefore, how to provide a clock switching circuit that effectively avoids glitches during clock switching, enables fast switching between different source clocks, and avoids cross-clock domain processing issues is a problem that needs to be solved. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a clock switching circuit and clock modules, chips, computing boards, and computing devices that utilize it. This effectively avoids glitches during clock switching, enables rapid switching between different source clocks, and eliminates cross-clock domain processing problems. Clock switching circuits are indeed a problem that needs to be solved, thereby improving the performance of computing devices and reducing power consumption.

[0006] To achieve the above objectives, the present invention provides a clock switching circuit, comprising: a first synchronization unit for receiving a selection signal and a first clock signal, and outputting a first selection synchronization signal; a second synchronization unit for receiving the selection signal and a second clock signal, and outputting a second selection synchronization signal; an enable signal generation unit for generating a first clock enable signal and a second clock enable signal based on the first selection synchronization signal and the second selection synchronization signal; an enable signal feedback synchronization unit for synchronizing the first clock enable signal with the second clock signal, and synchronizing the second clock enable signal with the first clock signal; a gated clock unit for transmitting the first clock signal and the second clock signal based on the first clock enable signal and the second clock enable signal; and an output gating unit for selecting to output either the first clock signal or the second clock signal.

[0007] In the aforementioned clock switching circuit, when the selection signal changes, the first clock signal or the second clock signal is completely turned off before switching to output the second clock signal or the first clock signal.

[0008] In the aforementioned clock switching circuit, the first clock signal or the second clock signal is turned off for a certain period of time before the second clock signal or the first clock signal is switched to be output.

[0009] In the aforementioned clock switching circuit, the time length is greater than or equal to the sum of half a cycle of the first clock signal and half a cycle of the second clock signal.

[0010] In the aforementioned clock switching circuit, the first synchronization unit includes a first inverter and at least one flip-flop connected in series.

[0011] In the aforementioned clock switching circuit, the at least one flip-flop includes a first flip-flop and a second flip-flop; the first inverter has a first terminal and a first second terminal, the first terminal of the first inverter being electrically connected to the selection signal; the first flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the first flip-flop being electrically connected to the second terminal of the first inverter, and the second terminal of the first flip-flop being electrically connected to the first clock signal; the second flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the second flip-flop being electrically connected to the third terminal of the first flip-flop, the second terminal of the second flip-flop being electrically connected to the first clock signal, and the third terminal of the second flip-flop being electrically connected to the first selection synchronization signal.

[0012] In the aforementioned clock switching circuit, the second synchronization unit includes at least one flip-flop connected in series.

[0013] In the aforementioned clock switching circuit, the at least one flip-flop includes a third flip-flop and a fourth flip-flop; the third flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the third flip-flop is electrically connected to the selection signal, and the second terminal of the third flip-flop is electrically connected to the second clock signal; the fourth flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the fourth flip-flop is electrically connected to the third terminal of the third flip-flop, the second terminal of the fourth flip-flop is electrically connected to the second clock signal, and the third terminal of the fourth flip-flop is electrically connected to the second selection synchronization signal.

[0014] In the aforementioned clock switching circuit, the enable signal feedback synchronization unit includes a third synchronization unit and a fourth synchronization unit.

[0015] In the aforementioned clock switching circuit, the third synchronization unit includes at least one flip-flop and a second inverter connected in series.

[0016] In the aforementioned clock switching circuit, the at least one flip-flop includes a fifth flip-flop and a sixth flip-flop; the fifth flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the fifth flip-flop is electrically connected to the second clock enable signal, and the second terminal of the fifth flip-flop is electrically connected to the first clock signal; the sixth flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the sixth flip-flop is electrically connected to the third terminal of the fifth flip-flop, and the second terminal of the sixth flip-flop is electrically connected to the first clock signal; the second inverter has a first terminal and a first and a second terminal, the first terminal of the second inverter is electrically connected to the second terminal of the sixth flip-flop, and the second terminal of the second inverter is electrically connected to the enable signal generation unit.

[0017] In the aforementioned clock switching circuit, the fourth synchronization unit includes at least one flip-flop connected in series and a third inverter.

[0018] In the aforementioned clock switching circuit, the at least one flip-flop includes a seventh flip-flop and an eighth flip-flop; the seventh flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the seventh flip-flop is electrically connected to the first clock enable signal, and the second terminal of the seventh flip-flop is electrically connected to the second clock signal; the eighth flip-flop has a first terminal, a second terminal, and a third terminal, the first terminal of the eighth flip-flop is electrically connected to the third terminal of the seventh flip-flop, and the second terminal of the eighth flip-flop is electrically connected to the second clock signal; the third inverter has a first terminal and a first and a second terminal, the first terminal of the third inverter is electrically connected to the second terminal of the eighth flip-flop, and the second terminal of the third inverter is electrically connected to the enable signal generation unit.

[0019] In the aforementioned clock switching circuit, the enable signal generation unit includes a first AND gate and a second AND gate.

[0020] In the aforementioned clock switching circuit, the first AND gate has a first terminal, a second terminal, and a third terminal. The first terminal of the first AND gate is electrically connected to the first selection synchronization signal, and the second terminal of the first AND gate is electrically connected to the enable signal feedback synchronization unit. The second AND gate has a first terminal, a second terminal, and a third terminal. The first terminal of the second AND gate is electrically connected to the second selection synchronization signal, and the second terminal of the second AND gate is electrically connected to the enable signal feedback synchronization unit.

[0021] The clock switching circuit described above includes a first gated clock circuit and a second gated clock circuit.

[0022] In the aforementioned clock switching circuit, the first gated clock circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the first gated clock circuit is electrically connected to the first clock signal, the second terminal of the first gated clock circuit is electrically connected to the first clock enable signal, and the third terminal of the first gated clock circuit is electrically connected to the output gating unit. The second gated clock circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the second gated clock circuit is electrically connected to the second clock signal, the second terminal of the second gated clock circuit is electrically connected to the second clock enable signal, and the third terminal of the second gated clock circuit is electrically connected to the output gating unit.

[0023] The clock switching circuit described above, wherein the first gated clock circuit and / or the second gated clock circuit includes AND gates.

[0024] In the aforementioned clock switching circuit, the output gating unit includes an OR gate.

[0025] To better achieve the above objectives, the present invention also provides a multi-channel clock switching circuit, which includes at least one of the clock switching circuits described above.

[0026] The aforementioned multi-channel clock switching circuit includes a first clock switching circuit, a second clock switching circuit, and a third clock switching circuit.

[0027] In the aforementioned multi-channel clock switching circuit, the first clock switching circuit and the second clock switching circuit are electrically connected to the third clock switching circuit.

[0028] To better achieve the above objectives, the present invention also provides a clock module, wherein it includes at least one clock switching circuit as described above.

[0029] To better achieve the above objectives, the present invention also provides a chip, wherein it includes at least one clock module as described above.

[0030] To better achieve the above objectives, the present invention also provides a computing device, wherein at least one of the chips described above is included.

[0031] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the circuit structure of a clock switching circuit according to an embodiment of the present invention.

[0033] Figure 2 This is a waveform diagram of a clock switching circuit according to an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the circuit structure of a clock switching circuit according to another embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the circuit structure of a multi-channel clock switching circuit according to an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of the circuit structure of a multi-channel clock switching circuit according to another embodiment of the present invention. Detailed Implementation

[0037] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0038] Certain terms are used in the specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but rather by differences in function.

[0039] Throughout this specification and in the following claims, the terms "comprising" and "including" are open-ended and should be interpreted as "comprising but not limited to". Furthermore, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0040] Figure 1 This is a schematic diagram of the circuit structure of a clock switching circuit according to an embodiment of the present invention. Figure 1As shown, the clock switching circuit 100 of the present invention includes a first synchronization unit 101, used to receive a selection signal sel and a first clock signal clk0, and output a first selection synchronization signal clk0_en0; a second synchronization unit 102, used to receive a selection signal sel and a second clock signal clk1, and output a second selection synchronization signal clk1_en0; and an enable signal generation unit 103, used to generate a first clock enable signal clk0_en and a second clock enable signal clk0_en based on the first selection synchronization signal clk0_en0 and the second selection synchronization signal clk1_en0. Signal clk1_en; Enable signal feedback synchronization unit 104, used to synchronize the first clock enable signal clk0_en with the second clock signal clk1, and synchronize the second clock enable signal clk1_en with the first clock signal clk0; Gated clock unit 105, used to transmit the first clock signal clk0 and the second clock signal clk1 according to the first clock enable signal clk0_en and the second clock enable signal clk1_en; Output gating unit 106, used to select to output the first clock signal clk0 or the second clock signal clk1.

[0041] In the clock switching circuit 100 of the present invention, when the selection signal sel changes, the first clock signal clk0 or the second clock signal clk1 is completely turned off before switching to output the second clock signal clk1 or the first clock signal clk0. That is, after receiving the selection signal sel, the clock switching circuit 100 of the present invention will select to switch the output clock signal according to the selection signal sel, but will wait until the currently output clock signal is completely turned off before outputting the clock signal selected by the selection signal sel.

[0042] To achieve a more complete shutdown, the first clock signal clk0 or the second clock signal clk1 is turned off for a certain duration before switching the output to another clock signal, i.e., outputting the second clock signal clk1 or the first clock signal clk0. The shutdown duration is greater than or equal to the sum of half a cycle of the first clock signal clk0 and half a cycle of the second clock signal clk1.

[0043] Specifically, such as Figure 1As shown, the first synchronization unit 101 includes a first inverter, a first flip-flop DFF0, and a second flip-flop DFF1 connected in series. The first terminal (input terminal) of the first inverter is electrically connected to the selection signal sel, and the second terminal (output terminal) is electrically connected to the first terminal (D terminal) of the first flip-flop DFF0. The second terminal (CLK terminal) of the first flip-flop DFF0 is electrically connected to the first clock signal clk0. The third terminal (Q terminal) of the first flip-flop DFF0 is electrically connected to the first terminal (D terminal) of the second flip-flop DFF1. The second terminal (CLK terminal) of the second flip-flop DFF1 is electrically connected to the first clock signal clk0. The third terminal (Q terminal) of the second flip-flop DFF1 is used to output the first selection synchronization signal clk0_en0.

[0044] In this invention, only the first flip-flop DFF0 and the second flip-flop DFF1, which are connected in series, are used as examples for illustration.

[0045] The second synchronization unit 102 includes a third flip-flop DFF6 and a fourth flip-flop DFF7 connected in series. The first terminal (D) of the third flip-flop DFF6 is electrically connected to the selection signal sel. The second terminal (CLK) of the third flip-flop DFF6 is electrically connected to the second clock signal clk1. The third terminal (Q) of the third flip-flop DFF6 is electrically connected to the first terminal (D) of the fourth flip-flop DFF7. The second terminal (CLK) of the fourth flip-flop DFF7 is electrically connected to the second clock signal clk1. The third terminal (Q) of the fourth flip-flop DFF7 is used to output the second selection synchronization signal clk1_en0.

[0046] In this invention, only the third flip-flop DFF6 and the fourth flip-flop DFF7, which are connected in series, are used as examples for illustration.

[0047] The enable signal feedback synchronization unit 104 includes a third synchronization unit 1041 and a fourth synchronization unit 1042. The third synchronization unit 1041 includes a fifth flip-flop DFF2, a sixth flip-flop DFF3, and a second inverter connected in series. The first terminal (D) of the fifth flip-flop DFF2 is electrically connected to the second clock enable signal clk1_en, the second terminal (CLK) of the fifth flip-flop DFF2 is electrically connected to the first clock signal clk0, the third terminal (Q) of the fifth flip-flop DFF2 is electrically connected to the first terminal (D) of the sixth flip-flop DFF3, the second terminal (CLK) of the sixth flip-flop DFF3 is electrically connected to the first clock signal clk0, and the third terminal (Q) of the sixth flip-flop DFF3 is electrically connected to the first terminal (input) of the second inverter. The second terminal (output) of the second inverter is used to output clk0_en1.

[0048] In this invention, only two-stage series-connected triggers DFF2 and DFF3 are used as examples for illustration.

[0049] The fourth synchronization unit 1042 includes a seventh flip-flop DFF4, an eighth flip-flop DFF5, and a third inverter connected in series. The first terminal (D) of the seventh flip-flop DFF4 is electrically connected to the first clock enable signal clk0_en, the second terminal (CLK) of the seventh flip-flop DFF4 is electrically connected to the second clock signal clk1, the third terminal (Q) of the seventh flip-flop DFF4 is electrically connected to the first terminal (D) of the eighth flip-flop DFF5, the second terminal (CLK) of the eighth flip-flop DFF5 is electrically connected to the second clock signal clk1, the third terminal (Q) of the eighth flip-flop DFF5 is electrically connected to the first terminal (input) of the third inverter, and the second terminal (output) of the third inverter is used to output clk1_en1.

[0050] In this invention, only two-stage series-connected triggers DFF4 and DFF5 are used as examples for illustration.

[0051] In this invention, the enable signal generation unit 103 may include a first AND gate AND0 and a second AND gate AND2. The first AND gate AND0 is used to generate a first clock enable signal clk0_en, and the second AND gate AND2 is used to generate a second clock enable signal clk1_en. In this invention, only AND gates are used as an example for illustration; other circuits capable of generating AND logic may also be used.

[0052] The first input terminal of the first AND gate AND0 is electrically connected to the first selection synchronization signal clk0_en0, and the second input terminal of the first AND gate AND0 is electrically connected to clk0_en1. The first input terminal of the second AND gate AND2 is electrically connected to the second selection synchronization signal clk1_en0, and the second input terminal of the second AND gate AND2 is electrically connected to clk1_en1. The third terminals of both the first AND gate AND0 and the second AND gate AND2 are electrically connected to the gated clock unit 105.

[0053] In this invention, the gated clock unit 105 includes a third gated clock circuit AND1 and a fourth gated clock circuit AND3. The first terminal (one input terminal) of the third gated clock circuit AND1 is electrically connected to the first clock signal clk0, the second terminal (another input terminal) of the third gated clock circuit AND1 is electrically connected to the first clock enable signal clk0_en, and the third terminal (output terminal) of the third gated clock circuit AND1 is electrically connected to the output gating unit 106. The first terminal (one input terminal) of the fourth gated clock circuit AND3 is electrically connected to the second clock signal clk1, the second terminal (another input terminal) of the fourth gated clock circuit AND3 is electrically connected to the second clock enable signal clk1_en, and the third terminal (output terminal) of the fourth gated clock circuit AND3 is electrically connected to the output gating unit 106. In this invention, only an AND gate is used as an example to describe the gated clock circuit; other gated clock circuits (ICG) can also be used, and this invention is not limited thereto.

[0054] The output gating unit 106 of the present invention may be an OR gate or other circuit structures that generate "OR" logic, and the present invention is not limited thereto.

[0055] Working principle:

[0056] Combination Figures 1-2 As shown, the select signal sel is reset to 0, and clk0 is selected by default.

[0057] At time T0: the selection signal sel becomes 1, and clock switching is required.

[0058] At time T1: After two levels of synchronization, the second selection synchronization signal clk1_en0 becomes 1. However, since clk1_en1 is still 0 at this time, after passing through AND gate AND2, the second clock enable signal clk1_en becomes 0, and the second clock signal clk1 is still in the off state.

[0059] At time T2: After two levels of synchronization, the first selection synchronization signal clk0_en0 becomes 0. After AND0, the first clock enable signal clk0_en becomes 0, the first clock signal clk0 becomes off, and the final clock output clkout becomes 0.

[0060] At time T3: After two stages of feedback synchronization, clk1_en1 becomes 1. After passing through AND gate AND2, the second clock enable signal clk1_en becomes 1, and the second clock signal clk1 becomes enabled. clk1_gated is enabled, and the clock output clkout becomes the waveform of the first clock signal clk1.

[0061] At time T4: After two levels of feedback synchronization, clk0_en1 becomes 0.

[0062] At time T5: the selection signal sel changes from 1 to 0, and the clock is switched again.

[0063] At time T6: After passing through two stages of synchronization circuits, the second selection synchronization signal clk1_en0 becomes 0. At the same time, due to the action of AND gate AND2, the second clock enable signal clk1_en becomes 0, clk1_gated becomes 0, and the clock output clkout becomes 0.

[0064] At time T7: After passing through two levels of synchronization circuits, the first selection synchronization signal clk0_en0 changes from 0 to 1. However, since clk0_en1 is still 0 at this time, after passing through AND gate AND0, the first clock enable signal clk0_en is 0, and the first clock signal clk0 is still in the off state.

[0065] At time T8: After two stages of feedback synchronization, clk0_en1 changes from 0 to 1. After passing through AND gate AND0, the first clock enable signal clk0_en changes from 0 to 1, and the first clock signal clk0 becomes enabled. The clk0_gated clock is enabled, and the clock output clkout becomes the waveform of the first clock signal clk0.

[0066] At time T9: After two levels of feedback synchronization, clk1_en1 becomes 0.

[0067] In summary, during the process of switching from the first clock signal clk0 to the second clock signal clk1, the output of the first clock signal clk0 is turned off, and this state is synchronized to the clock domain of the second clock signal clk1. Then, the second clock signal clk1 outputs its clock to clkout, ensuring that the first clock signal clk0 is turned off first and then switched to the second clock signal clk1, without generating glitches during the switching process.

[0068] Similarly, the switching from the second clock signal clk1 to the first clock signal clk0 is also done in the same way. Assume that time T0 is before and very close to the rising edge of the first clock signal clk0, and time T2 is before and very close to the rising edge of the second clock signal clk1. The time during which the intermediate clock is turned off is at least half a clk0 cycle plus half a clk1 cycle.

[0069] In addition, both inputs of AND gate AND0 are synchronized by the first clock signal clk0, ensuring convergence in cross-clock domain processing. Similarly, both inputs of AND gate AND2 are synchronized by the second clock signal clk1, ensuring convergence in cross-clock domain processing.

[0070] Figure 3This is a schematic diagram of the circuit structure of a clock switching circuit according to another embodiment of the present invention. Figure 3 As shown, Figure 3 In the embodiment shown, flip-flops DFF1, DFF3, DFF5, and DFF7 are replaced with rising-edge flip-flops, and AND gates and1 and and3 are replaced with standard clock gating units (ICGs). Figure 1 In the embodiment shown, flip-flops DFF1, DFF3, DFF5, and DFF7 are falling-edge flip-flops. When AND gates AND1 and AND3 perform timing checks, the checks are performed every half cycle. After being replaced with clock gating units (ICG), the timing checks will be performed every one cycle, which is more conducive to timing convergence.

[0071] Figure 4 This is a schematic diagram of the circuit structure of a multi-channel clock switching circuit according to an embodiment of the present invention. Figure 4 As shown, the multi-channel clock switching circuit 200 includes a first clock switching circuit 100-1, a second clock switching circuit 100-2, and a third clock switching circuit 100-3. The first clock switching circuit 100-1, the second clock switching circuit 100-2, and the third clock switching circuit 100-3 can be... Figure 1 The clock switching circuit shown in the embodiment can also be Figure 2 The clock switching circuit shown in the embodiment is not limited to this invention. The multi-channel clock switching circuit 200 can switch between three clock signals clk0, clk1 and clk2, but it requires two selection signals sel0 and sel1.

[0072] Figure 5 This is a schematic diagram of the circuit structure of a multi-channel clock switching circuit according to another embodiment of the present invention. Figure 5 As shown, the multi-channel clock switching circuit 300 includes a first clock switching circuit 100-1, a second clock switching circuit 100-2, and a third clock switching circuit 100-3. The first clock switching circuit 100-1, the second clock switching circuit 100-2, and the third clock switching circuit 100-3 can be... Figure 1 The clock switching circuit shown in the embodiment can also be Figure 2 The clock switching circuit shown in the embodiment is not limited to this invention. The multi-channel clock switching circuit 300 can switch between four clock signals clk0, clk1, clk2 and clk3, but it requires two selection signals sel0 and sel1.

[0073] Therefore, by combining multiple clock switching circuits, more clock signals can be switched between under the selection of multiple selection signals.

[0074] To better achieve the above objectives, the present invention also provides a clock module, wherein it includes at least one clock switching circuit as described above.

[0075] To better achieve the above objectives, the present invention also provides a chip, wherein it includes at least one clock module as described above.

[0076] To better achieve the above objectives, the present invention also provides a computing board for a computing device, wherein it includes at least one of the chips described above.

[0077] To better achieve the above objectives, the present invention also provides a computing device, including a power board, a control board, a connection board, a heat sink, and a plurality of computing boards. The control board is connected to the computing boards through the connection board. The heat sink is disposed around the computing boards. The power board is used to provide power to the connection board, the control board, the heat sink, and the computing boards. The computing boards are as described above.

[0078] It should be noted that in the description of this invention, the terms "lateral", "longitudinal", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0079] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A clock switching circuit, characterized by, include: A first synchronization unit is used to receive a selection signal and a first clock signal, and output a first selection synchronization signal; A second synchronization unit is used to receive the selection signal and a second clock signal, and output a second selection synchronization signal; An enable signal generation unit is configured to generate a first clock enable signal based on the first selection synchronization signal, and to generate a second clock enable signal based on the second selection synchronization signal. An enable signal feedback synchronization unit is used to synchronize the first clock enable signal with the second clock signal, and to synchronize the second clock enable signal with the first clock signal; A gated clock unit is used to transmit the first clock signal according to the first clock enable signal, and to transmit the second clock signal according to the second clock enable signal; An output gating unit is used to select the output of the first clock signal or the second clock signal.

2. The clock switching circuit of claim 1, wherein: When the selection signal changes, the first clock signal or the second clock signal output is completely turned off before switching to outputting the second clock signal or the first clock signal.

3. The clock switching circuit of claim 2, wherein: After the first clock signal or the second clock signal is turned off for a certain period of time, the output of the second clock signal or the first clock signal is switched back on.

4. The clock switching circuit of claim 3, wherein: The duration is greater than or equal to the sum of half a cycle of the first clock signal and half a cycle of the second clock signal.

5. The clock switching circuit of claim 1, wherein: The first synchronization unit includes a first inverter connected in series and at least one trigger.

6. The clock switching circuit of claim 5, wherein: The at least one trigger includes a first trigger and a second trigger; The first inverter has a first terminal and a first second terminal, and the first terminal of the first inverter is electrically connected to the selection signal; The first flip-flop has a first terminal, a second terminal and a third terminal. The first terminal of the first flip-flop is electrically connected to the second terminal of the first inverter, and the second terminal of the first flip-flop is electrically connected to the first clock signal. The second flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the second flip-flop is electrically connected to the third terminal of the first flip-flop, the second terminal of the second flip-flop is electrically connected to the first clock signal, and the third terminal of the second flip-flop is electrically connected to the first selection synchronization signal.

7. The clock switching circuit of claim 1, wherein: The second synchronization unit includes at least one trigger connected in series.

8. The clock switching circuit of claim 7, wherein: The at least one trigger includes a third trigger and a fourth trigger; The third flip-flop has a first terminal, a second terminal and a third terminal. The first terminal of the third flip-flop is electrically connected to the selection signal, and the second terminal of the third flip-flop is electrically connected to the second clock signal. The fourth flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the fourth flip-flop is electrically connected to the third terminal of the third flip-flop, the second terminal of the fourth flip-flop is electrically connected to the second clock signal, and the third terminal of the fourth flip-flop is electrically connected to the second selection synchronization signal.

9. The clock switching circuit of claim 1, wherein: The enable signal feedback synchronization unit includes a third synchronization unit and a fourth synchronization unit.

10. The clock switching circuit of claim 9, wherein: The third synchronization unit includes at least one flip-flop connected in series and a second inverter.

11. The clock switching circuit of claim 10, wherein: The at least one trigger includes a fifth trigger and a sixth trigger; The fifth flip-flop has a first terminal, a second terminal and a third terminal. The first terminal of the fifth flip-flop is electrically connected to the second clock enable signal, and the second terminal of the fifth flip-flop is electrically connected to the first clock signal. The sixth flip-flop has a first terminal, a second terminal and a third terminal. The first terminal of the sixth flip-flop is electrically connected to the third terminal of the fifth flip-flop, and the second terminal of the sixth flip-flop is electrically connected to the first clock signal. The second inverter has a first terminal and a first second terminal. The first terminal of the second inverter is electrically connected to the second terminal of the sixth flip-flop, and the second terminal of the second inverter is electrically connected to the enable signal generation unit.

12. The clock switching circuit as described in claim 9, characterized in that: The fourth synchronization unit includes at least one flip-flop connected in series and a third inverter.

13. The clock switching circuit as described in claim 12, characterized in that: The at least one trigger includes a seventh trigger and an eighth trigger; The seventh flip-flop has a first terminal, a second terminal and a third terminal. The first terminal of the seventh flip-flop is electrically connected to the first clock enable signal, and the second terminal of the seventh flip-flop is electrically connected to the second clock signal. The eighth flip-flop has a first terminal, a second terminal and a third terminal. The first terminal of the eighth flip-flop is electrically connected to the third terminal of the seventh flip-flop, and the second terminal of the eighth flip-flop is electrically connected to the second clock signal. The third inverter has a first terminal and a first second terminal. The first terminal of the third inverter is electrically connected to the second terminal of the eighth flip-flop, and the second terminal of the third inverter is electrically connected to the enable signal generation unit.

14. The clock switching circuit as described in claim 1, characterized in that: The enable signal generation unit includes a first AND gate and a second AND gate.

15. The clock switching circuit as described in claim 14, characterized in that: The first AND gate has a first terminal, a second terminal and a third terminal. The first terminal of the first AND gate is electrically connected to the first selection synchronization signal, and the second terminal of the first AND gate is electrically connected to the enable signal feedback synchronization unit. The second AND gate has a first terminal, a second terminal and a third terminal. The first terminal of the second AND gate is electrically connected to the second selection synchronization signal, and the second terminal of the second AND gate is electrically connected to the enable signal feedback synchronization unit.

16. The clock switching circuit as described in claim 1, characterized in that: The gated clock unit includes a first gated clock circuit and a second gated clock circuit.

17. The clock switching circuit as described in claim 16, characterized in that: The first gated clock circuit has a first terminal, a second terminal and a third terminal. The first terminal of the first gated clock circuit is electrically connected to the first clock signal, the second terminal of the first gated clock circuit is electrically connected to the first clock enable signal, and the third terminal of the first gated clock circuit is electrically connected to the output gating unit. The second gated clock circuit has a first terminal, a second terminal and a third terminal. The first terminal of the second gated clock circuit is electrically connected to the second clock signal, the second terminal of the second gated clock circuit is electrically connected to the second clock enable signal, and the third terminal of the second gated clock circuit is electrically connected to the output gating unit.

18. The clock switching circuit as described in claim 16, characterized in that: The first gated clock circuit and / or the second gated clock circuit include AND gates.

19. The clock switching circuit as described in claim 1, characterized in that: The output gating unit includes an OR gate.

20. A multi-channel clock switching circuit, characterized in that: It includes at least one clock switching circuit as described in claims 1-19.

21. The multi-channel clock switching circuit as described in claim 20, characterized in that: The clock switching circuit includes a first clock switching circuit, a second clock switching circuit, and a third clock switching circuit.

22. The multi-channel clock switching circuit as described in claim 21, characterized in that: The first clock switching circuit and the second clock switching circuit are electrically connected to the third clock switching circuit.

23. A clock module, characterized in that, It includes at least one clock switching circuit as described in claims 1-19.

24. A chip, characterized in that, It includes at least one clock module as described in claim 23.

25. A computing device, characterized in that, It includes at least one chip as described in claim 24.

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