SoC chip-oriented general software design method, device, equipment and storage medium

Abstract

Embodiments of the present disclosure provide a general software design method, device and equipment for SoC chips and a storage medium. The method comprises: obtaining a device requirement task sheet, decomposing the device requirement task sheet, and generating a corresponding software task; setting a state set of a state machine according to device application requirements; the state set corresponds to the software task; confirming a state machine pulse and a pulse type according to the device application requirements; setting an input interface and an input parameter of the state machine jump; setting a state transition condition corresponding to the state set and specifying a state transition function; setting a task to be executed when the state transition condition triggers the state transition; and generating a required software design task sheet after the setting is completed. In this way, a general software framework for SoC chips can be quickly constructed, the maintainability of software design is improved, the use cost of the data link SoC chip is reduced, the problem code is located faster by using state information and event information, and the product iteration speed is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer application technology, and in particular to general software design methods, apparatus, devices and storage media for SoC chips. Background Technology

[0002] Data link SoC chips provide wideband spread spectrum and wideband FSK communication capabilities, meeting the signal processing needs of data link products and their supporting products. In the application design process based on data link SoC chips, designers need to modify the design software according to the design requirements of different products to achieve compatibility of the data link SoC chip on different products. This necessitates a structured software design methodology for data link products. This methodology should provide users with a universal data link software product design approach while simultaneously accelerating the iteration and upgrade speed of data link SoC products and shortening the time-to-market, while ensuring product stability. Summary of the Invention

[0003] This disclosure provides a general software design method, apparatus, device, and storage medium for SoC chips.

[0004] According to a first aspect of this disclosure, a general software design method for SoC chips is provided. The method includes:

[0005] Obtain the equipment requirements document, break down the equipment requirements document, and generate the corresponding software tasks.

[0006] The state set of the state machine is set according to the application requirements of the device; the state set corresponds to the software task.

[0007] Confirm the state machine pulse and pulse type according to the equipment application requirements; set the input interface and input parameters for state machine transitions;

[0008] Set the state transition conditions corresponding to the state set and specify the state transition function;

[0009] Set the state transition conditions to trigger the task to be executed when a state transition occurs;

[0010] After the settings are completed, the required software design task document will be generated.

[0011] In some possible implementations of the first aspect, the state machine pulse and pulse type are determined according to the device application requirements, including:

[0012] If the device has a minimum cycle in the software development process, then the state machine pulse is confirmed to be periodic.

[0013] If the device does not have a minimum cycle in the software development process, then the state machine pulse is confirmed to be aperiodic.

[0014] In some possible implementations of the first aspect, if the device has a minimum cycle in the software development process, then the state machine pulse is confirmed to be periodic, including:

[0015] If the device has a minimum cycle in the software development process, the state machine uses the minimum cycle as its pulse; at the end of the minimum cycle, the state machine obtains input instructions and performs state transitions to execute the corresponding tasks.

[0016] In some possible implementations of the first aspect, if the device does not have a minimum cycle in the software development process, then the state machine pulse is confirmed to be aperiodic, including:

[0017] If the device does not have a minimum cycle in the software development process, the state machine takes the new external instructions it receives as its pulse. When a new external instruction is received, the state machine obtains the input instruction and performs a state transition to execute the corresponding task.

[0018] Among some possible implementations of the first aspect, the method also includes:

[0019] If the state machine pulse is aperiodic, then the state of the state machine needs to be divided into forced state and non-forced state according to the transition situation;

[0020] If the state machine is in a state that requires an immediate transition, then the state is a forced state. In a forced state, the state machine immediately transitions to the new state based on the current instruction and executes the corresponding state transition function.

[0021] If the state of the state machine is a state that needs to be transitioned to in the next state machine pulse, then the state is a non-forced state. In a non-forced state, when the state machine receives a new external instruction, it will transition to the new state according to the new external instruction and execute the corresponding state transition function.

[0022] Among some possible implementations of the first aspect, the method also includes:

[0023] If the task to be executed during a state transition changes, the task to be executed during the state transition is modified by modifying the corresponding state transition function.

[0024] Among some possible implementations of the first aspect, the method also includes:

[0025] If there are new requirements for the device application, then the corresponding state and state transition function are added to the state machine according to the new requirements.

[0026] According to a second aspect of this disclosure, a general-purpose software design apparatus for SoC chips is provided. The apparatus includes:

[0027] The receiving module obtains the equipment requirement task book;

[0028] Decompose the module and break down the equipment requirements document;

[0029] The first processing module generates the corresponding software task; sets the state set of the state machine according to the device application requirements; the state set corresponds to the software task.

[0030] The second processing module confirms the state machine pulse and pulse type; sets the input interface and input parameters for state machine transitions; sets the state transition conditions corresponding to the state set and defines the state transition function; and sets the tasks to be executed when the state transition conditions trigger a state transition.

[0031] The third processing module generates a software design task book based on the processing results of the first and second processing modules.

[0032] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described above.

[0033] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform the methods described above.

[0034] In this disclosure, by clarifying the selection rules for the state machine pulse in state machine design and dividing the states within the state machine into mandatory and non-mandatory states, the readability of the software system is enhanced, the software coupling between various sub-functions is reduced, and a more comprehensive design criterion is provided for the selection of state machine driving sources. The division of mandatory and non-mandatory states further improves the versatility of this software design method.

[0035] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0036] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0037] Figure 1 A schematic diagram illustrates an exemplary operating environment in which embodiments of the present disclosure can be implemented;

[0038] Figure 2 It shows Figure 1 A schematic diagram of the working method of a state machine;

[0039] Figure 3 A schematic diagram of a general software design method for SoC chips according to an embodiment of the present disclosure is shown;

[0040] Figure 4 A flowchart illustrating a general software design method for SoC chips according to embodiments of the present disclosure is shown;

[0041] Figure 5 A block diagram of a general software design apparatus for SoC chips according to an embodiment of the present disclosure is shown;

[0042] Figure 6 A block diagram of an electronic device for implementing a general software design method for SoC chips according to embodiments of the present disclosure is shown. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0044] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] In view of the problems in the background art, this disclosure provides a general software design method, apparatus, device and storage medium for SoC chips.

[0046] Specifically, this paper clarifies the selection rules for state machine pulses in state machine design and divides the states within the state machine into mandatory and non-mandatory states. In this way, the readability of the software system is enhanced, the cohesion of each sub-module is improved, the software coupling between each sub-function is reduced, and the overall maintainability of the program is improved. This provides a more comprehensive design criterion for the selection of state machine driver sources and further enhances the versatility of the general software design method for SoC chips provided in this disclosure.

[0047] The following detailed description, with reference to the accompanying drawings and specific embodiments, illustrates a general software design method, apparatus, device, and storage medium for SoC chips provided in this disclosure.

[0048] Figure 1 A schematic diagram of an exemplary operating environment in which embodiments of the present disclosure can be implemented is shown. For example... Figure 1 As shown, taking a product based on a data link SoC chip as an example, the application requirements of this device are as follows: The data input of this device is a serial port command stream. By reading the command stream in the serial port, the initialization of the spread spectrum acquisition module, data link parameter loading, command issuance, data reception and reporting, and other IO control functions are realized. It is necessary to design a software state machine to adjust the device state according to the command content and realize the above functions during the state transition process.

[0049] The following is based on Figure 1 The example shown combines Figures 2-4 A detailed explanation will be provided.

[0050] Figure 2 It shows Figure 1 A schematic diagram of the working method of a state machine; Figure 3 A schematic diagram of a general software design method for SoC chips according to an embodiment of the present disclosure is shown; Figure 4 A flowchart illustrating a general software design method for SoC chips according to embodiments of this disclosure is shown; as follows: Figure 4 As shown, the general software design method 400 for SoC chips may include the following steps:

[0051] S410: Obtain the equipment requirement task book, decompose the equipment requirement task book, and generate the corresponding software task.

[0052] In some embodiments, after obtaining the device requirement task book, the requirements are decomposed and corresponding software tasks are generated, wherein the software tasks may include: handshake, reset, data parsing, data processing, etc.

[0053] S420 sets the state set of the state machine according to the application requirements of the device; the state set corresponds to the software task.

[0054] like Figure 2 As shown, based on the device application requirements, the state machine is divided into five states: idle, command parsing, command execution, exception handling, and termination. Command execution further includes three sub-states: handshake, reset, and data accumulation. The data accumulation sub-state further includes a data processing sub-state. Figure 1 The state set of the state machine in the device shown consists of the aforementioned states and sub-states.

[0055] like Figure 2As shown, each state in the state set corresponds to a generated software task. The idle state corresponds to software tasks such as receiving instruction streams, the command parsing state corresponds to software tasks such as frame header judgment, command code reading and judgment, the command execution state corresponds to software tasks such as reset, handshake, data accumulation and processing, and the exception handling state corresponds to software tasks such as receiving and processing exception data.

[0056] S430: Determine the state machine pulse and pulse type according to the device application requirements; set the input interface and input parameters for state machine transitions.

[0057] In some embodiments, the state machine pulse is a crucial driving force for state transitions in the software state machine. The state machine pulse can be a periodic timer interrupt or a closed-loop loop triggered by certain conditions. Whenever the timer expires or the trigger condition is met, the state machine enters the state transition diagram and executes the corresponding task based on the system input and the current state. The selection of the state machine pulse is related to the application requirements of the data link device. If the data link device has a minimum cycle in the software flow, then this minimum cycle can be used as the state machine pulse. At the end of one cycle of the minimum cycle, the state machine obtains system input, performs a state transition, and executes the corresponding task. If the data link device uses external instructions as system input, then a closed-loop loop can be used, with the acquisition of new external instructions serving as the state machine's operating pulse. For periodic state machine pulses, the state machine does not need to distinguish between forced and non-forced states; however, for non-periodic state machine pulses, the design methods for forced and non-forced states need to be referenced to classify the various states in the state machine.

[0058] In some embodiments, if the device has a minimum cycle in the software development process, the state machine pulse is confirmed to be periodic; if the device does not have a minimum cycle in the software development process, the state machine pulse is confirmed to be aperiodic.

[0059] According to such Figure 1 The equipment application requirements shown are determined Figure 1 The device shown responds to serial port commands, therefore, it lacks a minimum cycle in the software development process, necessitating the use of an aperiodic state machine pulse. Considering the asymmetry between the serial data stream and CPU processing speed, the device employs a circular buffer as a buffer for command data. Whenever an external command arrives, the write pointer is incremented. When the read and write pointers differ, it indicates a new external command has entered. Therefore, the device uses the consistency of the read and write pointers as the trigger for the state machine pulse.

[0060] In some embodiments, if the device has a minimum cycle in the software development process, the state machine uses the minimum cycle as its pulse; at the end of the minimum cycle, the state machine obtains input instructions and performs state transitions to execute the corresponding tasks.

[0061] In some embodiments, if the device does not have a minimum cycle in the software development process, the state machine takes the new external instructions it collects as its pulse. When a new external instruction is collected, the state machine obtains the input instruction and performs a state transition to execute the corresponding task.

[0062] Confirmed Figure 1 The state machine pulse in the device shown is aperiodic. Next, the states within the state machine need to be divided into mandatory and non-mandatory states. Based on the device application requirements, tasks such as reset, handshake, data processing, and exception data handling require immediate state transitions and execution upon receiving an instruction; therefore, these are classified as mandatory states. States such as command retrieval and data accumulation require new external instructions to arrive before further state transitions can occur; therefore, they are classified as non-mandatory states.

[0063] In some embodiments, if the state machine pulse is aperiodic, the state of the state machine needs to be divided into forced state and non-forced state according to the transition situation.

[0064] If the state of the state machine is a state that requires an immediate transition, then the state is a forced state. In a forced state, the state machine immediately transitions to the new state based on the current instruction and executes the corresponding state transition function.

[0065] If the state of the state machine is a state that needs to be transitioned to in the next state machine pulse, then the state is a non-forced state. In a non-forced state, when the state machine receives a new external instruction, it will transition to the new state according to the new external instruction and execute the corresponding state transition function.

[0066] In some embodiments, if the task to be performed during a state transition changes, the task to be performed during the state transition is modified by modifying the corresponding state transition function.

[0067] In some embodiments, when the data processing method changes, the software designer only needs to change the corresponding state transition function without having to change other parts of the state machine.

[0068] In some embodiments, if there are new requirements for the device application, corresponding states and state transition functions are added to the state machine according to the new requirements.

[0069] In some embodiments, when the software development process needs to be expanded on the existing basis, software designers can implement new functions by adding states in the state machine and corresponding state transition functions. This approach can minimize the impact of the new design on the original design.

[0070] S440, set the state transition conditions corresponding to the state set and specify the state transition function.

[0071] S450 sets the task to be executed when the state transition condition is triggered.

[0072] like Figure 2 As shown, after receiving a serial port command stream, the idle state in the state machine controls the device to transition to the command parsing state. In the command parsing state, after receiving and parsing the command stream, the device transitions to the command execution state. In the command execution state, the device transitions to a handshake, reset, or data accumulation state based on the received command. If it transitions to the handshake state, the device performs a handshake task. After completion, the device transitions to the end state. If there is no abnormal end command, the device transitions to the idle state. If it transitions to the reset state, the device performs a partial reset task. After completion, the device transitions to the end state. If there is no abnormal end command, the device transitions to the idle state. If it transitions to the data accumulation state, the device performs a data accumulation task. When the data accumulates to a set value, data reception is complete, and the device transitions to the data processing state to perform a data processing task. After completion, the state machine controls the device to the end state. If there is no abnormal end command, the device transitions to the idle state. If an abnormal termination command is received when the device jumps to the end state after command execution is completed, the device will jump from the end state to the abnormal state for exception handling. After handling, the state machine controls the device to jump to the idle state. If data abnormalities occur in the idle state or command execution state, the device will also jump to the abnormal state for exception handling. After handling, it will jump back to the idle state.

[0073] After setting up S460, the required software design task book will be generated.

[0074] like Figure 3 As shown, after setting the above content, a software design task sheet for coding guidance can be generated, which can quickly build a software framework for designers who are new to or unfamiliar with data link SoC chip software design patterns.

[0075] According to the embodiments of this disclosure, the following technical effects are achieved:

[0076] From the perspective of program readability and maintainability, the general software design method, apparatus, device and storage medium for SoC chips provided in this disclosure divides the state machine into mandatory and non-mandatory states, increases the intermediate states in software design, further subdivides the software design content based on the state machine according to design requirements, reduces the software coupling between functional modules, and improves the maintainability of software design.

[0077] From the perspective of program scalability, the general software design method, apparatus, device and storage medium for SoC chips provided in this disclosure offer a complete state machine-based software design method, enabling designers who are new to or unfamiliar with data link SoC chip software design patterns to quickly build a software framework and reduce the cost of using data link SoC chips.

[0078] From the perspective of program debuggability, the general software design method, apparatus, device and storage medium for SoC chips provided in this disclosure enable debuggers to obtain the running status of the software during the debugging process, and use status information and event information to locate problematic code more quickly, thereby improving the product iteration speed.

[0079] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0080] The above is an introduction to the method embodiments. The following describes the solution described in this disclosure further through device embodiments.

[0081] Figure 5 A block diagram of a general-purpose software design apparatus for SoC chips according to an embodiment of the present disclosure is shown. Apparatus 500 may be included in... Figure 1 The device shown may be implemented as Figure 1 The device shown. (As shown) Figure 5 As shown, the device 500 includes:

[0082] Receive module 510 obtains the equipment requirement task book.

[0083] Decompose module 520, decompose equipment requirement task book.

[0084] The first processing module 530 generates the corresponding software task; sets the state set of the state machine according to the device application requirements; the state set corresponds to the software task.

[0085] The second processing module 540 confirms the state machine pulse and pulse type; sets the input interface and input parameters for state machine transitions; sets the state transition conditions corresponding to the state set and defines the state transition function; and sets the task to be executed when the state transition conditions trigger the state transition.

[0086] The third processing module 550 generates a software design task book based on the processing results of the first and second processing modules.

[0087] In some embodiments, the device 500 further includes:

[0088] The partitioning module is used to respond to state partitioning instructions in the state machine and divide the state of the state machine in a device with an aperiodic pulse type into mandatory and non-mandatory states.

[0089] Understandable Figure 5 Each module / unit in the general software design apparatus 500 for SoC chips shown has the function of implementing each step of the vulnerability handling method provided in the embodiments of this disclosure, and can achieve its corresponding technical effect. Those skilled in the art can clearly understand that, for the sake of convenience and brevity, the specific working process of the described module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0090] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0091] Figure 6 A schematic block diagram of an electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0092] like Figure 6As shown, the electronic device 600 may include a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0093] Multiple components in electronic device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of displays, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as method 400. For example, in some embodiments, method 400 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of method 400 described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform method 400 by any other suitable means (e.g., by means of firmware).

[0095] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), computed-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0096] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0097] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0098] It should be noted that this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute method 400 and achieve the corresponding technical effects achieved by executing the method in the embodiments of this disclosure. For the sake of brevity, they will not be described in detail here.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0100] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0101] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0102] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A general software design method for SoC chips, characterized in that, include: Obtain the equipment requirement task book, decompose the equipment requirement task book, and generate the corresponding software tasks; Configure the state set of the state machine according to the application requirements of the device; The state set corresponds to the software task; Determine the state machine pulse and pulse type based on the equipment application requirements; Configure the input interface and input parameters for state machine transitions; among them, If the device has a minimum cycle in the software development process, then the state machine pulse is confirmed to be periodic. The state machine uses the minimum cycle as its pulse. When the minimum cycle ends, the state machine obtains the input instruction and performs a state transition to execute the corresponding task. If the device does not have a minimum cycle in the software development process, then the state machine pulse is confirmed to be aperiodic. The state machine takes the newly acquired external instructions as its pulse. When the new external instructions are acquired, the state machine obtains the input instructions and performs state transitions to execute the corresponding tasks. When the state machine pulse is aperiodic, the state of the state machine is divided into forced states and non-forced states according to the transition situation; wherein... The forced state is a state that requires an immediate transition. The state machine immediately transitions to the new state based on the current instruction and executes the corresponding state transition function. The non-mandatory state is a state that needs to be transitioned to in the next state machine pulse. When the state machine obtains a new external instruction, it performs a state transition according to the new external instruction and executes the corresponding state transition function at the same time. Set the state transition conditions corresponding to the state set and define the state transition function; Set the task to be executed when the state transition condition is triggered; After the settings are completed, the required software design task document will be generated.

2. The method according to claim 1, characterized in that, The method further includes: If the task to be executed during the state transition changes, the task to be executed during the state transition is changed by modifying the corresponding state transition function.

3. The method according to claim 1, characterized in that, The method further includes: If the device application has new requirements, then the corresponding state and state transition function are added to the state machine according to the new requirements.

4. A general-purpose software design apparatus for SoC chips, characterized in that, include: The receiving module obtains the equipment requirement task book; Decompose the module and break down the equipment requirements document; The first processing module generates the corresponding software tasks; The state set of the state machine is set according to the application requirements of the device; the state set corresponds to the software task. The second processing module confirms the state machine pulse and pulse type; Configure the input interface and input parameters for state machine transitions; among them, If the device has a minimum cycle in the software development process, then the state machine pulse is confirmed to be periodic. The state machine uses the minimum cycle as its pulse. When the minimum cycle ends, the state machine obtains the input instruction and performs a state transition to execute the corresponding task. If the device does not have a minimum cycle in the software development process, then the state machine pulse is confirmed to be aperiodic. The state machine takes the newly acquired external instructions as its pulse. When the new external instructions are acquired, the state machine obtains the input instructions and performs state transitions to execute the corresponding tasks. When the state machine pulse is aperiodic, the state of the state machine is divided into forced states and non-forced states according to the transition situation; wherein... The forced state is a state that requires an immediate transition. The state machine immediately transitions to the new state based on the current instruction and executes the corresponding state transition function. The non-mandatory state is a state that needs to be transitioned to in the next state machine pulse. When the state machine obtains a new external instruction, it performs a state transition according to the new external instruction and executes the corresponding state transition function at the same time. Set the state transition conditions corresponding to the state set and define the state transition function; set the task to be executed when the state transition conditions trigger the state transition; The third processing module generates a software design task book based on the processing results of the first and second processing modules.

5. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-3.

6. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-3.

Images