Branch instruction processing method and apparatus, device, and medium

Abstract

This disclosure provides a branch instruction processing method, apparatus, device, and medium for multi-threaded processors, relating to the field of computer technology, and particularly to the field of chip technology and branch prediction technology. The implementation scheme includes: obtaining a first branch instruction for a first thread and a second thread; determining a first predicted execution result for the first branch instruction based on the shared historical branch instruction execution record of the first and second threads and the first branch instruction, so that the first thread and the second thread can control instruction execution based on the first predicted execution result; obtaining a first actual execution result and a second actual execution result of the first branch instruction from the first thread and the second thread respectively; and updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result and the first predicted execution result.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of chip technology and branch prediction technology, specifically to a branch instruction processing method, apparatus, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] When the processor receives a branch instruction, in order to avoid waiting for the branch instruction execution result to determine the branch direction, branch prediction technology can be used to obtain a branch prediction result including the branch direction, thereby prompting the processor to continue to fetch and execute other instructions, avoiding delays caused by waiting for the execution result of the branch instruction.

[0003] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0004] This disclosure provides a branch instruction processing method, apparatus, electronic device, computer-readable storage medium, and computer program product.

[0005] According to one aspect of this disclosure, a branch instruction processing method for a multi-threaded processor is provided, the multi-threaded processor including a first thread and a second thread, the method comprising: acquiring a first branch instruction for the first thread and the second thread; determining a first predicted execution result for the first branch instruction based on a shared historical branch instruction execution record of the first thread and the second thread and the first branch instruction, such that the first thread and the second thread can control instruction execution based on the first predicted execution result; acquiring a first actual execution result and a second actual execution result of the first branch instruction from the first thread and the second thread respectively; and updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result and the first predicted execution result.

[0006] According to another aspect of this disclosure, a branch instruction processing apparatus for a multi-threaded processor is provided, the multi-threaded processor including a first thread and a second thread, comprising: a first acquisition unit configured to acquire a first branch instruction for the first thread and the second thread; a first determination unit configured to determine a first predicted execution result for the first branch instruction based on a shared historical branch instruction execution record of the first thread and the second thread and the first branch instruction, such that the first thread and the second thread can control instruction execution based on the first predicted execution result; a second acquisition unit configured to acquire a first actual execution result and a second actual execution result of the first branch instruction from the first thread and the second thread respectively; and an update unit configured to update the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result and the first predicted execution result.

[0007] According to another aspect of this disclosure, a chip is also provided, including the branch instruction processing apparatus as described above.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the branch instruction processing method described above.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to execute the branch instruction processing method described above.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program, when executed by a processor, is capable of implementing the above-described branch instruction processing method.

[0011] According to one or more embodiments of this disclosure, the resources consumed by branch instruction processing can be reduced, thereby improving hardware utilization.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0014] Figure 1 A schematic diagram of an exemplary system in which various methods described herein may be implemented, according to exemplary embodiments of the present disclosure;

[0015] Figure 2 A flowchart illustrating a branch instruction processing method applied to a multithreaded processor according to an exemplary embodiment of the present disclosure is shown;

[0016] Figure 3 A schematic diagram illustrating the process for determining the target execution result according to an exemplary embodiment of the present disclosure is shown;

[0017] Figure 4 A schematic diagram of a branch instruction processing procedure according to an exemplary embodiment of the present disclosure is shown;

[0018] Figure 5 A flowchart illustrating a branch instruction processing method applied to a multithreaded processor according to an exemplary embodiment of the present disclosure is shown;

[0019] Figure 6 A structural block diagram of a branch instruction processing apparatus applied to a multithreaded processor according to an exemplary embodiment of the present disclosure is shown;

[0020] Figure 7 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0021] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0022] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0023] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0024] When branch prediction technology is applied to multi-threaded processors, the relevant techniques usually perform branch prediction independently for each of the multiple threads based on the historical branch records of that thread, which has high resource consumption and low efficiency.

[0025] The applicant noted that in some application scenarios, multiple threads in a multi-threaded processor obtain the same data processing instructions but different data to be processed, and then perform data processing separately based on the different data. Based on this, this disclosure provides a branch instruction processing method that allows multiple threads to share the same historical branch instruction execution record. By obtaining the branch instructions to be processed for multiple threads, and obtaining the branch prediction result based on the historical branch instruction execution record, each thread can continue to execute the data processing task based on the branch prediction result. After obtaining the actual execution result, the historical branch instruction execution record is updated based on the actual execution result, thereby improving the accuracy of subsequent branch predictions.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of an exemplary system 100 in which the various methods and apparatus described herein can be implemented according to embodiments of this disclosure is shown. Reference Figure 1 The system 100 includes one or more client devices 101, 102, 103, 104, 105 and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105 and 106 can be configured to execute one or more applications.

[0028] In embodiments of this disclosure, server 120 may run one or more services or software applications that enable branch instruction processing methods to be executed.

[0029] In some embodiments, server 120 may also provide other services or software applications, which may include non-virtual and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to users of client devices 101, 102, 103, 104, 105, and / or 106 under a Software as a Service (SaaS) model.

[0030] exist Figure 1 In the configuration shown, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 can sequentially interact with server 120 using one or more client applications to utilize the services provided by these components. It should be understood that various different system configurations are possible and may differ from system 100. Therefore, Figure 1 This is an example of a system used to implement the various methods described herein, and is not intended to be limiting.

[0031] Users can use client devices 101, 102, 103, 104, 105, and / or 106 to send first branch instructions. The client devices can provide an interface that allows users to interact with the client devices. The client devices can also output information to the user through this interface. Although... Figure 1 Only six client devices are described, but those skilled in the art will understand that this disclosure can support any number of client devices.

[0032] Client devices 101, 102, 103, 104, 105, and / or 106 may include various categories of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptops), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors, or other sensing devices. These computer devices can run various categories and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as Google Chrome OS); or include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, and Android. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Gaming systems may include various handheld gaming devices, internet-enabled gaming devices, etc. Client devices can run a variety of different applications, such as various Internet-related applications, communication applications (e.g., email applications), short message service (SMS) applications, and can use various communication protocols.

[0033] Network 110 can be any type of network well known to those skilled in the art, and can use any of a variety of available protocols (including but not limited to TCP / IP, SNA, IPX, etc.) to support data communication. By way of example only, one or more networks 110 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0034] Server 120 may include one or more general-purpose computers, special-purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0035] The computing unit in server 120 can run one or more operating systems, including any of the aforementioned operating systems and any commercially available server operating system. Server 120 can also run any of a variety of additional server applications and / or middleware applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0036] In some implementations, server 120 may include one or more applications to analyze and merge data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0037] In some implementations, server 120 can be a server for a distributed system or a server integrated with blockchain. Server 120 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0038] System 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. Databases 130 may reside in various locations. For example, a database used by server 120 may be local to server 120, or it may be located away from server 120 and may communicate with server 120 via a network-based or dedicated connection. Databases 130 may be of different categories. In some embodiments, the database used by server 120 may be, for example, a relational database. One or more of these databases may store, update, and retrieve data from and from the databases in response to commands.

[0039] In some embodiments, one or more of the databases 130 may also be used by an application to store application data. The databases used by the application may be different categories of databases, such as key-value stores, object stores, or regular stores supported by a file system.

[0040] Figure 1The system 100 can be configured and operated in various ways to enable the application of the various methods and apparatus described in this disclosure.

[0041] Figure 2 A flowchart of a branch instruction processing method 200 applied to a multithreaded processor according to an exemplary embodiment of the present disclosure is shown. The multithreaded processor includes a first thread and a second thread.

[0042] like Figure 2 As shown, method 200 includes:

[0043] Step S201: Obtain the first branch instruction for the first thread and the second thread;

[0044] Step S202: Based on the shared historical branch instruction execution record of the first thread and the second thread and the first branch instruction, determine the first predicted execution result for the first branch instruction, so that the first thread and the second thread can control instruction execution based on the first predicted execution result;

[0045] Step S203: Obtain the first actual execution result and the second actual execution result of the first branch instruction from the first thread and the second thread, respectively; and

[0046] Step S204: Update the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result and the first predicted execution result.

[0047] Therefore, when the first thread and the second thread perform the same processing task, the first thread and the second thread can share the same historical branch instruction execution record. By obtaining the first branch instruction for the two threads, prediction is made based on the historical branch instruction execution record, so that each thread can control the instruction execution based on the prediction result. After obtaining the actual execution result, the historical record is updated based on this, realizing the sharing of historical branch instruction execution record, reducing the occupation of hardware resources by historical branch instruction execution record, and improving hardware utilization.

[0048] In some examples, the multi-threaded processor is an AI processor, in which multiple threads can perform the same AI computing task based on different data. By utilizing the method 200 described above, the occupation of hardware resources can be reduced and the AI ​​processing performance can be improved.

[0049] In some examples, the first branch instruction can be matched with the historical branch instruction execution record. For example, a hash calculation can be performed to obtain the first predicted execution result based on the historical branch instruction execution results stored in the historical branch instruction execution record.

[0050] In some examples, the execution result of a branch instruction can include either a jump or no jump.

[0051] In some examples, a larger number of threads can share the same historical branch instruction execution record to further reduce the hardware resource consumption of the historical branch instruction execution record and improve hardware utilization.

[0052] According to some embodiments, method 200 further includes: obtaining a second branch instruction for the first thread and the second thread; determining a second predicted execution result for the second branch instruction based on the updated historical branch instruction execution record and the second branch instruction, so that the first thread and the second thread can control instruction execution based on the second predicted execution result; obtaining a third actual execution result and a fourth actual execution result of the second branch instruction from the first thread and the second thread respectively; and updating the historical branch instruction execution record again based on at least one of the third actual execution result and the second predicted execution result. Thus, the updated historical branch instruction execution record can be used to determine the second predicted execution result more accurately.

[0053] In some examples, more branch instructions for the first and second threads can be obtained, and branch prediction can be performed based on this, and the historical branch record can be updated multiple times using the corresponding actual execution results. This disclosure does not limit this.

[0054] In some examples, after obtaining the predicted execution result for each branch instruction, the branch instruction can be stored in the instruction queue. After obtaining the actual execution result for the temporarily stored instruction in the queue, the historical branch instruction execution record can be updated based on the actual execution result and the predicted execution result.

[0055] Furthermore, in some examples, the predicted execution results corresponding to the branch instructions can also be stored in a prediction information queue, so that information such as the predicted execution results can be read from it when the step of updating the historical branch instruction execution record is performed.

[0056] According to some embodiments, step S204, updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result, includes: determining the generation order information of the first actual execution result and the generation order information of the second actual execution result; determining the target execution result from the first actual execution result and the second actual execution result based on the generation order information; and updating the historical branch instruction execution record based on the target execution result. Therefore, a unique target execution result can be determined based on the generation order information, ensuring that only the actual execution result of one thread among multiple threads is used to update the historical branch instruction execution record, improving update accuracy and guaranteeing the consistency of the historical branch instruction execution record.

[0057] According to some embodiments, determining the target execution result from the first and second actual execution results based on the generation order information includes: updating the target execution result identifier to indicate the latest generated actual execution result based on the generation order information; and determining the target execution result based on the target execution result identifier. Therefore, the identifier can be used to indicate the target execution result, which is simpler and more efficient.

[0058] In real-world applications, the following possibility exists: different threads execute at different speeds. Therefore, while the slowest thread may not yet have received the actual execution result for the first branch instruction, the fastest thread may have already received the actual execution result for the new second branch instruction. Based on this, Figure 3 A schematic diagram illustrating the process of determining the target execution result according to an exemplary embodiment of this disclosure is shown. In this example, a generation flag can be used to indicate whether the actual execution result corresponding to each thread has been generated. See also Figure 3 In response to determining that the actual execution result for any thread has been generated, the generation flag of that thread is updated to indicate that it has been generated; furthermore, in response to determining that the generation flag of a certain thread has been updated to indicate that it has been generated, and in response to determining that the instruction being executed by that thread is the first branch instruction, the target execution result flag is updated to indicate that the actual execution result for that thread is the target execution result.

[0059] In some examples, the instruction fetch operation of a thread can be used to determine the difference in execution speed between different threads. For example, an instruction fetch flag can be used to indicate whether each thread has successfully fetched an instruction. In this example, in response to determining that any thread has successfully fetched a new instruction, the instruction fetch flag corresponding to that thread can be updated to "fetched". Furthermore, the actual execution results can be obtained only for threads whose instruction fetch flag is "fetched" to determine the target execution result.

[0060] According to some embodiments, the historical branch instruction execution record includes a first sub-record corresponding to a first historical duration and a second sub-record corresponding to a second historical duration, where the first historical duration is different from the second historical duration. Step S202, based on the historical branch instruction execution records of the first thread and the second thread, and the first branch instruction, determines the first predicted execution result for the first branch instruction by: determining a first sub-prediction result for the first branch instruction based on the first sub-record and the first branch instruction; determining a second sub-prediction result for the first branch instruction based on the second sub-record and the first branch instruction; and determining the first predicted execution result from the first sub-prediction result and the second sub-prediction result based on a preset rule. Therefore, multiple sub-prediction results can be obtained based on multiple sub-records, and then the final result can be determined from them, thereby improving the accuracy of branch prediction.

[0061] According to some embodiments, both the first sub-record and the second sub-record include an accuracy, which indicates the accuracy of the sub-prediction result corresponding to each sub-record. Step S204, updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result, includes: in response to determining that the first sub-prediction result is the first predicted execution result, and in response to determining that the first predicted execution result is the same as the actual execution result, updating the accuracy of the first sub-record to increase the accuracy of the first sub-record; and in response to determining that the second sub-prediction result is the first predicted execution result, and in response to determining that the first predicted execution result is the same as the actual execution result, updating the accuracy of the second sub-record to increase the accuracy of the second sub-record. Furthermore, determining the first predicted execution result from the first sub-prediction result and the second sub-prediction result based on a preset rule includes: determining the sub-prediction result corresponding to the sub-record with the higher accuracy among the first and second sub-records as the first predicted execution result. Therefore, the accuracy of each sub-record can be updated based on the correctness of the prediction result corresponding to it, and the final result can be determined from multiple sub-prediction results based on the accuracy, thus improving the accuracy of branch prediction.

[0062] In some examples, step S204 further includes: in response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is different from the actual execution result, updating the accuracy of the first sub-record to reduce the accuracy of the first sub-record; and in response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is different from the actual execution result, updating the accuracy of the second sub-record to reduce the accuracy of the second sub-record. Thus, the accuracy of each sub-record can be updated based on the correctness of the prediction result corresponding to that sub-record, improving the accuracy of branch prediction.

[0063] According to some embodiments, the accuracy includes a count value, and wherein, in response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the first sub-record is updated by one; and in response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the second sub-record is updated by one. Thus, the accuracy can be updated based on the number of times each sub-record is correctly predicted, which is simpler and more efficient.

[0064] In some examples, step S240 further includes: in response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is different from the actual execution result, decrementing the accuracy of the first sub-record by one; and in response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is different from the actual execution result, decrementing the accuracy of the second sub-record by one. Thus, the accuracy can be updated based on the number of times each sub-record is correctly predicted, which is simpler and more efficient, improving the accuracy of branch prediction.

[0065] According to some embodiments, in step S202, determining the first predicted execution result for the first branch instruction based on the historical branch instruction execution records of the first thread and the second thread, and the first branch instruction, includes: determining the instruction identifier corresponding to the first branch instruction based on the historical branch instruction execution records of the first thread and the second thread, and the first branch instruction; determining the first predicted execution result from a branch prediction table based on the instruction identifier, wherein the branch prediction table stores multiple instruction identifiers and multiple first predicted execution results that are mapped one-to-one with the multiple instruction identifiers; and in step S204, updating the historical branch instruction execution records and the branch prediction table based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result. Therefore, the branch prediction table can be used to store instruction identifiers and predicted execution results, and the predicted execution result corresponding to each branch instruction can be obtained by looking up the table, thus improving prediction efficiency.

[0066] According to some embodiments, the branch prediction table also stores the prediction confidence scores of the plurality of first prediction execution results, and the first prediction execution results and their prediction confidence scores can be determined from the branch prediction table based on the instruction identifier. Therefore, the confidence scores can be used to improve the accuracy of the prediction execution results stored in the branch prediction table, further enhancing the accuracy of branch prediction.

[0067] Figure 4 A schematic diagram of a branch instruction processing procedure according to an exemplary embodiment of the present disclosure is shown. Figure 5 A flowchart of a branch instruction processing method 500 applied to a multi-threaded processor according to an exemplary embodiment of the present disclosure is shown. Figure 4 and Figure 5 As shown, method 500 includes:

[0068] Step S501: Obtain the first branch instruction for the first thread and the second thread;

[0069] Step S502: Based on the historical branch instruction execution records of the first thread and the second thread and the first branch instruction, determine the instruction identifier corresponding to the first branch instruction so that the first thread and the second thread can control instruction execution based on the first predicted execution result;

[0070] Step S503: Based on the instruction identifier, determine the first prediction execution result and its confidence level from the branch prediction table;

[0071] Step S504: Obtain the first actual execution result and the second actual execution result of the first branch instruction from the first thread and the second thread respectively;

[0072] Step S505: Determine the generation order information of the first real execution result and the generation order information of the second real execution result;

[0073] Step S506: Based on the generation order information, determine the target execution result from the first real execution result and the second real execution result; and

[0074] Step S507: Based on the target execution result, update the historical branch instruction execution record and branch prediction table.

[0075] According to another aspect of this disclosure, a branch instruction processing apparatus for a multi-threaded processor is also provided. Figure 6 A structural block diagram of a branch instruction processing apparatus 600 applied to a multithreaded processor according to an exemplary embodiment of the present disclosure is shown, the multithreaded processor including a first thread and a second thread. Figure 6 As shown, the device 600 includes:

[0076] The first acquisition unit 601 is configured to acquire a first branch instruction for the first thread and the second thread;

[0077] The first determining unit 602 is configured to determine a first predicted execution result for the first branch instruction based on the shared historical branch instruction execution record of the first thread and the second thread and the first branch instruction, so that the first thread and the second thread can control instruction execution based on the first predicted execution result.

[0078] The second acquisition unit 603 is configured to acquire, respectively, the first actual execution result and the second actual execution result of the first branch instruction from the first thread and the second thread; and

[0079] The update unit 604 is configured to update the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result and the first predicted execution result.

[0080] According to some embodiments, the first acquisition unit is further configured to acquire a second branch instruction for the first thread and the second thread; the first determination unit is further configured to determine a second predicted execution result for the second branch instruction based on the updated historical branch instruction execution record and the second branch instruction, so that the first thread and the second thread can control instruction execution based on the second predicted execution result; the second acquisition unit is further configured to acquire a third actual execution result and a fourth actual execution result of the second branch instruction from the first thread and the second thread respectively; and the update unit is further configured to update the historical branch instruction execution record again based on at least one of the third actual execution result and the second predicted execution result.

[0081] According to some embodiments, the update unit includes: a first determining subunit configured to determine the generation order information of the first real execution result and the generation order information of the second real execution result; a second determining subunit configured to determine a target execution result from the first real execution result and the second real execution result based on the generation order information; and an update subunit configured to update the historical branch instruction execution record of the branch predictor based on the target execution result.

[0082] According to some embodiments, the second determining subunit is configured to: update the target execution result identifier to indicate the latest generated actual execution result based on the generation order information; and determine the target execution result based on the target execution result identifier.

[0083] According to some embodiments, the historical branch instruction execution record includes a first sub-record corresponding to a first historical duration and a second sub-record corresponding to a second historical duration, wherein the first historical duration is different from the second historical duration, and the first determining unit includes: a third determining sub-unit configured to determine a first sub-prediction result for the first branch instruction based on the first sub-record and the first branch instruction; a fourth determining sub-unit configured to determine a second sub-prediction result for the first branch instruction based on the second sub-record and the first branch instruction; and a fifth determining sub-unit configured to determine the first prediction execution result from the first sub-prediction result and the second sub-prediction result based on a preset rule.

[0084] According to some embodiments, both the first sub-record and the second sub-record include an accuracy, the accuracy indicating the accuracy of the sub-prediction result corresponding to each sub-record, and wherein the updating unit is configured to: in response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, update the accuracy of the first sub-record to increase the accuracy of the first sub-record; and in response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, update the accuracy of the second sub-record to increase the accuracy of the second sub-record, and wherein the fifth determining sub-unit is configured to: determine that the sub-prediction result corresponding to the sub-record with higher accuracy in the first sub-record and the second sub-record is the first prediction execution result.

[0085] According to some embodiments, the accuracy includes a count value, and the update unit is configured to: in response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, perform an increment update on the accuracy of the first sub-record; and in response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, perform an increment update on the accuracy of the second sub-record.

[0086] According to some embodiments, the first determining unit includes: a sixth determining subunit configured to determine an instruction identifier corresponding to the first branch instruction based on the historical branch instruction execution records of the first thread and the second thread and the first branch instruction; and a seventh determining subunit configured to determine the first predicted execution result from a branch prediction table based on the instruction identifier, wherein the branch prediction table stores multiple instruction identifiers and multiple first predicted execution results that are mapped one-to-one with the multiple instruction identifiers, and wherein the updating unit is configured to update the historical branch instruction execution records and the branch prediction table based on at least one of the first actual execution result and the second actual execution result and the first predicted execution result.

[0087] According to some embodiments, the branch prediction table also stores the prediction confidence of the plurality of first prediction execution results, and wherein the seventh determining subunit is configured to determine the first prediction execution result and its prediction confidence from the branch prediction table based on the instruction identifier.

[0088] The operation of units 601-604 of the branch instruction processing device 600 is similar to the operation of steps S201-S204 described above, and will not be repeated here.

[0089] According to another aspect of this disclosure, a chip is also provided, including the branch instruction processing device 600 as described above.

[0090] According to another aspect of this disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the branch instruction processing method described above.

[0091] According to another aspect of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to cause the computer to execute the branch instruction processing method described above.

[0092] According to another aspect of this disclosure, a computer program product is also provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the branch instruction processing method described above.

[0093] refer to Figure 7 The present invention describes a structural block diagram of an electronic device 700 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0094] like Figure 7 As shown, device 700 includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 702 or a computer program loaded from storage unit 708 into random access memory (RAM) 703. RAM 703 may also store various programs and data required for the operation of device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0095] Multiple components in device 700 are connected to I / O interface 705, including: input unit 706, output unit 707, storage unit 708, and communication unit 709. Input unit 706 can be any type of device capable of inputting information to device 700. Input unit 706 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of the electronic device, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 707 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 708 may include, but is not limited to, a hard disk and an optical disk. Communication unit 709 allows device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0096] The computing unit 701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as branch instruction processing methods. For example, in some embodiments, the branch instruction processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by the computing unit 701, one or more steps of the branch instruction processing method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform branch instruction processing methods by any other suitable means (e.g., by means of firmware).

[0097] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0098] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0099] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0100] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0101] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet, and blockchain networks.

[0102] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0103] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0104] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A branch instruction processing method applied to a multi-threaded processor, the multi-threaded processor including a first thread and a second thread, the method comprising: Obtain the same first branch instruction executed by the first thread and the second thread respectively; Based on the shared historical branch instruction execution record of the first thread and the second thread, and the first branch instruction, a first predicted execution result is determined for the first branch instruction, so that the first thread and the second thread can control instruction execution based on the first predicted execution result. The historical branch instruction execution record includes a first sub-record corresponding to a first historical duration and a second sub-record corresponding to a second historical duration, where the first historical duration is different from the second historical duration. Determining the first predicted execution result for the first branch instruction includes: Based on the first sub-record and the first branch instruction, determine the first sub-prediction result for the first branch instruction; Based on the second sub-record and the first branch instruction, determine the second sub-prediction result for the first branch instruction; and Based on preset rules, the first prediction execution result is determined from the first sub-prediction result and the second sub-prediction result; Obtain the first and second actual execution results of the first branch instruction from the first thread and the second thread, respectively; and The historical branch instruction execution record is updated based on at least one of the first actual execution result and the second actual execution result, as well as the first predicted execution result.

2. The method of claim 1, further comprising: Obtain the second branch instruction for the first thread and the second thread; Based on the updated historical branch instruction execution record and the second branch instruction, a second predicted execution result is determined for the second branch instruction, so that the first thread and the second thread can control instruction execution based on the second predicted execution result; Obtain the third and fourth actual execution results of the second branch instruction from the first thread and the second thread, respectively; as well as Based on at least one of the third actual execution result and the second predicted execution result, the historical branch instruction execution record is updated again.

3. The method as described in claim 1 or 2, wherein, Updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result, includes: Determine the generation order information of the first real execution result and the generation order information of the second real execution result; Based on the generation order information, the target execution result is determined from the first and second actual execution results; and Based on the target execution result, update the historical branch instruction execution record.

4. The method of claim 3, wherein, The step of determining the target execution result from the first and second real execution results based on the generation order information includes: Based on the generation order information, update the target execution result identifier to indicate the latest generated actual execution result; and The target execution result is determined based on the target execution result identifier.

5. The method of claim 1, wherein, Both the first sub-record and the second sub-record include an accuracy, which indicates the accuracy of the sub-prediction result corresponding to each sub-record. The step of updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result, includes: In response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the first sub-record is updated to increase the accuracy of the first sub-record; and In response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the second sub-record is updated to increase the accuracy of the second sub-record. Furthermore, the step of determining the first prediction execution result from the first sub-prediction result and the second sub-prediction result based on preset rules includes: The sub-prediction result corresponding to the sub-record with higher accuracy between the first sub-record and the second sub-record is determined as the first prediction execution result.

6. The method of claim 5, wherein, The accuracy includes count values, and wherein, In response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the first sub-record is updated by one; and In response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the second sub-record is updated by one.

7. The method of claim 1, wherein, The step of determining the first predicted execution result for the first branch instruction based on the shared historical branch instruction execution record of the first thread and the second thread, and the first branch instruction, includes: Based on the historical branch instruction execution records of the first thread and the second thread, and the first branch instruction, the instruction identifier corresponding to the first branch instruction is determined. Based on the instruction identifier, the first prediction execution result is determined from the branch prediction table, which stores multiple instruction identifiers and multiple first prediction execution results that are mapped one-to-one with the multiple instruction identifiers. Furthermore, updating the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result, includes: Based on at least one of the first actual execution result and the second actual execution result, and the first predicted execution result, update the historical branch instruction execution record and the branch prediction table.

8. The method of claim 7, wherein, The branch prediction table also stores the prediction confidence scores of the multiple first prediction execution results. Furthermore, based on the instruction identifier, the first prediction execution result and its prediction confidence are determined from the branch prediction table.

9. A branch instruction processing apparatus for a multi-threaded processor, the multi-threaded processor including a first thread and a second thread, the apparatus comprising: The first acquisition unit is configured to acquire the same first branch instruction executed by the first thread and the second thread respectively; The first determining unit is configured to determine a first predicted execution result for the first branch instruction based on the shared historical branch instruction execution record of the first thread and the second thread, and the first branch instruction, so that the first thread and the second thread can control instruction execution based on the first predicted execution result. The historical branch instruction execution record includes a first sub-record corresponding to a first historical duration and a second sub-record corresponding to a second historical duration, the first historical duration being different from the second historical duration. The first determining unit includes: The third determining subunit is configured to determine a first sub-prediction result for the first branch instruction based on the first sub-record and the first branch instruction. The fourth determining subunit is configured to determine a second sub-prediction result for the first branch instruction based on the second sub-record and the first branch instruction; and The fifth determining subunit is configured to determine the first prediction execution result from the first sub-prediction result and the second sub-prediction result based on preset rules; The second acquisition unit is configured to acquire, respectively, the first actual execution result and the second actual execution result of the first branch instruction from the first thread and the second thread; and The update unit is configured to update the historical branch instruction execution record based on at least one of the first actual execution result and the second actual execution result, as well as the first predicted execution result.

10. The apparatus of claim 9, wherein, The first acquisition unit is further configured to acquire a second branch instruction for the first thread and the second thread; The first determining unit is further configured to determine a second predicted execution result for the second branch instruction based on the updated historical branch instruction execution record and the second branch instruction, so that the first thread and the second thread can control instruction execution based on the second predicted execution result; The second acquisition unit is further configured to acquire the third and fourth actual execution results of the second branch instruction from the first thread and the second thread, respectively; as well as The update unit is further configured to update the historical branch instruction execution record again based on at least one of the third actual execution result and the second predicted execution result.

11. The apparatus of claim 9 or 10, wherein, The update unit includes: The first determining subunit is configured to determine the generation order information of the first real execution result and the generation order information of the second real execution result; The second determining subunit is configured to determine the target execution result from the first and second real execution results based on the generation order information; and The update subunit is configured to update the historical branch instruction execution record based on the target execution result.

12. The apparatus of claim 11, wherein, The second determining subunit is configured as follows: Based on the generation order information, update the target execution result identifier to indicate the latest generated actual execution result; as well as The target execution result is determined based on the target execution result identifier.

13. The apparatus of claim 9, wherein, Both the first and second sub-records include accuracy, which indicates the accuracy of the sub-prediction result corresponding to each sub-record, and wherein the update unit is configured to: In response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the first sub-record is updated to increase the accuracy of the first sub-record; and In response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the second sub-record is updated to increase the accuracy of the second sub-record. Furthermore, the fifth determining subunit is configured as follows: The sub-prediction result corresponding to the sub-record with higher accuracy between the first sub-record and the second sub-record is determined as the first prediction execution result.

14. The apparatus of claim 13, wherein, The accuracy includes count values, and the update unit is configured to: In response to determining that the first sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the first sub-record is updated by one; as well as In response to determining that the second sub-prediction result is the first prediction execution result, and in response to determining that the first prediction execution result is the same as the actual execution result, the accuracy of the second sub-record is updated by one.

15. The apparatus of claim 9, wherein, The first determining unit includes: The sixth determining subunit is configured to determine the instruction identifier corresponding to the first branch instruction based on the historical branch instruction execution records of the first thread and the second thread and the first branch instruction; The seventh determining subunit is configured to determine the first predicted execution result from a branch prediction table based on the instruction identifier. The branch prediction table stores multiple instruction identifiers and multiple first predicted execution results that are mapped one-to-one with the multiple instruction identifiers. Furthermore, the update unit is configured to update the historical branch instruction execution record and the branch prediction table based on at least one of the first actual execution result and the second actual execution result, as well as the first predicted execution result.

16. The apparatus of claim 15, wherein, The branch prediction table also stores the prediction confidence scores of the multiple first prediction execution results. Furthermore, the seventh determining subunit is configured to determine the first prediction execution result and its prediction confidence from the branch prediction table based on the instruction identifier.

17. A chip comprising the means as claimed in any one of claims 9-16.

18. An electronic device, comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8.

20. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method according to any one of claims 1-8.

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